STTS424E02
Memory module temperature sensor
with a 2 Kb SPD EEPROM
Not recommended for new design
Features
■
STTS424E02 includes a JEDEC JC 42.4
compatible temperature sensor, integrated
with industry standard 2 Kb serial presence
detect (SPD) EEPROM (STTS2002 is
recommended for new designs)
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TDFN8
2 mm x 3 mm (max height 0.80 mm)
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Temperature sensor
■
Temperature sensor resolution:
0.25 °C (typ)/LSB
■
Temperature sensor accuracy:
– ± 1 °C from +75 °C to +95 °C
– ± 2 °C from +40 °C to +125 °C
– ± 3 °C from –40 °C to +125 °C
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ADC conversion time: 125 ms (max)
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Supply voltage: 2.7 V to 3.6 V
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Maximum operating supply current: 210 µA
(EEPROM standby)
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Hysteresis selectable set points from: 0, 1.5, 3,
6.0 °C
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Ambient temperature sensing range: –40 °C to
+125 °C
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Two-wire bus
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2-wire SMBus/I2C - compatible serial interface
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Temperature sensor supports SMBus timeout
■
Supports up to 400 kHz transfer rate
Packages
■
DN: 2 mm x 3 mm TDFN8, height: 0.80 mm
(max). Compliant to JEDEC MO-229,
WCED-3.
■
DA: 2 mm x 3 mm DFN8, height: 0.90 mm
(max). Contact local ST sales office for
availability.
■
RoHS compliant, halogen-free
2 Kb SPD EEPROM
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Functionality identical to ST’s M34E02 SPD
EEPROM
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Permanent and reversible software data
protection for the lower 128 bytes
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Single supply voltage: 2.7 V to 3.6 V
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Byte and page write (up to 16 bytes)
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Self-time WRITE cycle (5 ms, max)
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Automatic address incrementing
■
Operating temperature range:
– –40 °C to +85 °C (DA package only)
– –40 °C to +125 °C (DN package only)
October 2010
DFN8
2 mm x 3 mm (max height 0.90 mm)
Doc ID 13448 Rev 8
This is information on a product still in production but not recommended for new designs.
1/50
www.st.com
1
Contents
STTS424E02
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Serial communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3
2.1
Device type identifier (DTI) code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2
Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2.1
A0, A1, A2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2.2
VSS (ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2.3
SDA (open drain) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2.4
SCL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2.5
EVENT (open drain) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2.6
VDD (power) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
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Temperature sensor operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4
3.1
SMBus/I2C
3.2
SMBus/I2
3.3
SMBus/I2C AC timing consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
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C slave sub-address decoding . . . . . . . . . . . . . . . . . . . . . . . . . 13
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Temperature sensor registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1
Capability register (read-only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
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4.3
Alarm window trip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Critical trip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Configuration register (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.2.1
Event thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.2.2
Interrupt mode
4.2.3
Comparator mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.2.4
Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.2.5
Event output pin functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Temperature register (read-only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.3.1
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Temperature format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.4
Temperature trip point registers (R/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.5
Manufacturer ID register (read-only) . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.6
Device ID and device revision ID register (read-only) . . . . . . . . . . . . . . . 26
Doc ID 13448 Rev 8
STTS424E02
5
Contents
SPD EEPROM operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.1
2 Kb SPD EEPROM operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.2
Internal device reset - SPD EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.3
Memory addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.4
Setting the write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.5
5.6
5.7
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SWP and CWP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.4.2
PSWP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
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5.5.1
Byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.5.2
Page write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.5.3
Write cycle polling using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
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Read operations - SPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
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5.6.1
Random address read - SPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.6.2
Current address read - SPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.6.3
Sequential read - SPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.6.4
Acknowledge in read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
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Initial delivery state - SPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
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Use in a memory module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.1
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Programming the SPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.1.1
DIMM isolated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.1.2
DIMM inserted in the application motherboard . . . . . . . . . . . . . . . . . . . 36
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Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
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DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
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Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
10
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
11
Package marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
12
Landing pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
13
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Doc ID 13448 Rev 8
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List of tables
STTS424E02
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
AC SMBus and I2C compatibility timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Temperature sensor registers summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Pointer register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Pointer register select bits (type, width, and default values). . . . . . . . . . . . . . . . . . . . . . . . 17
Capability register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Capability register bit definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Configuration register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Configuration register bit definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Hysteresis as applied to temperature movement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Legend for Figure 9: Event output boundary timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Temperature register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Temperature register bit definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Temperature trip point register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Alarm temperature upper boundary register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Alarm temperature lower boundary register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Critical temperature register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Manufacturer ID register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Device ID and device revision ID register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Acknowledge when writing data or defining the write-protection (instructions with
R/W bit=0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Acknowledge when reading the write protection (instructions with R/W bit=1). . . . . . . . . . 35
DRAM DIMM connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
DC/AC characteristics - temperature sensor component with EEPROM . . . . . . . . . . . . . . 38
DFN8 – 8-lead dual flat, no-lead (2 mm x 3 mm) mechanical data (DA) . . . . . . . . . . . . . . 41
TDFN8 – 8-lead thin dual flat, no-lead (2 mm x 3 mm) mechanical data (DN) . . . . . . . . . . 42
Carrier tape dimensions for DFN8 and TDFN8 packages . . . . . . . . . . . . . . . . . . . . . . . . . 43
Reel dimensions for 8 mm carrier tape - TDFN8 and DFN8 packages . . . . . . . . . . . . . . . 44
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Parameters for landing pattern - TDFN package (DN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
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Doc ID 13448 Rev 8
STTS424E02
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
DFN8 and TDFN8 connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SMBus/I2C write to pointer register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
SMBus/I2C write to pointer register, followed by a read data word. . . . . . . . . . . . . . . . . . . 12
SMBus/I2C write to pointer register, followed by a write data word . . . . . . . . . . . . . . . . . . 13
SMBus/I2C timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Event output boundary timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Result of setting the write protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Setting the write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Write mode sequences in a non write-protected area of SPD . . . . . . . . . . . . . . . . . . . . . . 31
Write cycle polling flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Read mode sequences - SPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
DFN8 – 8-lead dual flat, no-lead (2 mm x 3 mm) package outline (DA) . . . . . . . . . . . . . . . 41
TDFN8 – 8-lead thin dual flat, no-lead (2 mm x 3 mm) package outline (DN) . . . . . . . . . . 42
Carrier tape for DFN8 and TDFN8 packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Reel schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
DA package topside marking information (DFN-8L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
DN package topside marking information (TDFN-8L). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Landing pattern - TDFN package (DN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
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Doc ID 13448 Rev 8
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Description
1
STTS424E02
Description
The STTS424E02 is targeted for DIMM modules in mobile personal computing platforms
(laptops), server memory modules and other industrial applications. The thermal sensor
(TS) in the STTS424E02 is compliant with the JEDEC specification JC 42.4, which defines
memory module thermal sensors requirements for mobile platforms. The 2 Kb serial
presence detect (SPD) I2C-compatible electrically erasable programmable memory
(EEPROM) in the STTS424E02 is organized as 256 x 8 bits and is functionally identical to
the industry standard M34E02.
The TS-SPD EEPROM combination provides space as well as cost savings for mobile and
server platform dual inline memory modules (DIMM) manufacturers, as it is packaged in the
compact 2 mm x 3 mm 8-lead DFN package which is available in two variations. The DA
package has a maximum height of 0.90 mm. The DN package has an identical footprint as
the DA package with a thinner maximum height of 0.80 mm. The DN package is compliant
to JEDEC MO-229, variation WCED-3.
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The temperature sensor includes a band gap-based temperature sensor and 10-bit analogto-digital converter (ADC) which monitor and digitize the temperature to a resolution of up to
0.25 °C. The typical accuracies over these temperature ranges are:
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±3 °C over the full temperature measurement range of –40 °C to 125 °C,
±2 °C in the +40 °C to +125 °C temperature range, and
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±1 °C in the +75 °C to +95 °C temperature range.
The temperature sensor in the STTS424E02 is specified for operating at supply voltages
from 2.7 V to 3.6 V. Operating at 3.3 V, the supply current is 100 µA (typ) with EEPROM in
standby mode.
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The on-board sigma delta ADC converts the measured temperature to a digital value that is
calibrated in °C. For Fahrenheit applications, a lookup table or conversion routine is
required. The STTS424E02 is factory-calibrated and requires no external components to
measure temperature.
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The digital temperature sensor component has user-programmable registers that provide
the capabilities for DIMM temperature-sensing applications. The open drain event output pin
is active when the monitoring temperature exceeds a programmable limit, or it falls above or
below an alarm window. The user has the option to set the event output as a critical
temperature output. This pin can be configured to operate in either a comparator mode for
thermostat operation or in interrupt mode.
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The 2 Kb serial EEPROM memory in the STTS424E02 has the ability to permanently lock
the data in its first half (upper) 128 bytes (locations 00h to 7Fh). This facility has been
designed specifically for use in DRAM DIMMs with SPD. All of the information concerning
the DRAM module configuration (e.g. access speed, size, and organization) can be kept
write protected in the first half of the memory. The second half (lower) 128 bytes of the
memory can be write protected using two different software write protection mechanisms.
By sending the device a specific sequence, the first 128 bytes of the memory become write
protected: permanently or resettable. In the STTS424E02 the EEPROM write control (WC)
is always held low. Thus, the write protection of the memory array is dependent on whether
the software protection has been set.
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Doc ID 13448 Rev 8
STTS424E02
2
Serial communications
Serial communications
The STTS424E02 has a simple 2-wire SMBus™/I2C-compatible digital serial interface
which allows the user to access both the 2 Kb serial EEPROM and the data in the
temperature register at any time. It communicates via the serial interface with a master
controller which operates at speeds of up to 400 kHz. It also gives the user easy access to
all of the STTS424E02 registers in order to customize device operation.
2.1
Device type identifier (DTI) code
The JEDEC temperature sensor and EEPROM each have their own unique I2C address,
which ensures that there are no compatibility or data translation issues. This is due to the
fact that each of the devices have their own 4-bit DTI code, while the remaining three bits
are configurable. This enables the EEPROM and thermal sensors to provide their own
individual data via their unique addresses and still not interfere with each others’ operation
in any way. The DTI codes are:
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Note:
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●
'0011' for the TS, and
●
'1010' for addressing the EEPROM memory array, and
●
‘0110’ to access the software write protection settings of the EEPROM.
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The EEPROM in the STTS424E02 package has its WC pin internally tied to the VSS
(Ground) pad inside the package while the A0, A1, and A2 pins in the logic diagram (see
Figure 1 on page 8) correspond to the chip enable pins E0, E1 and E2 of EEPROM.
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Serial communications
Figure 1.
STTS424E02
Logic diagram
VDD
SDA(1)
EVENT(1)
SCL
A2
A1
A0
STTS424E02
)
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VSS
AI12261
1. SDA and EVENT are open drain.
Table 1.
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Signal names
Pr
Pin
Symbol
Description
1
A0
Serial bus address selection pin. Can be tied to VSS or VDD.
Input
2
A1
Serial bus address selection pin. Can be tied to VSS or VDD.
Input
3
A2
Serial bus address selection pin. Can be tied to VSS or VDD.
4
VSS
Supply ground.
5
(1)
Serial data.
SDA
6
SCL
7
EVENT(1)
8
VDD
)-
Serial clock.
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Input
Input/output
Input
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Direction
Event output pin. Open drain and active-low.
Output
Supply power (2.7 V to 3.6 V).
1. SDA and EVENT are open drain.
Note:
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P
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See Section 2.2: Pin descriptions on page 10 for details.
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Figure 2.
DFN8 and TDFN8 connections (top view)
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A0
A1
A2
GND
1
2
3
4
8
7
6
5
VDD
EVENT(1)
SCL
SDA(1)
AI12262
1. SDA and EVENT are open drain.
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Doc ID 13448 Rev 8
STTS424E02
Figure 3.
Serial communications
Block diagram
8
VDD
Temperature
Sensor
EVENT
Logic Control
Comparator
Timing
7
ADC
Capability
Register
Upper
Register
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Temperature
Register
WC
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VSS
1
2
3
A0
A1
A2
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Pr
od
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Address Pointer
Register
)
(s
E0 E1 E2
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Configuration
Register
2Kb SPD EEPROM
Software Write Protect
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Lower
Register
Critical
Register
Manufacturer
ID
Device ID/
Revision
SCL
6
2
SMBus/I C
Interface
SDA
5
VSS
4
AI12278a
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Serial communications
STTS424E02
2.2
Pin descriptions
2.2.1
A0, A1, A2
A2, A1, and A0 are selectable address pins for the 3 LSBs of the I2C interface address.
They can be set to VDD or GND to provide 8 unique address selections. These pins are
internally connected to the E2, E1, E0 (chip selects) of EEPROM.
2.2.2
VSS (ground)
This is the reference for the power supply. It must be connected to system ground.
2.2.3
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SDA (open drain)
This is the serial data input/output pin.
2.2.4
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SCL
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This is the serial clock input pin.
2.2.5
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EVENT (open drain)
This output pin is open drain and active-low, and functions as an alert interrupt.
2.2.6
VDD (power)
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This is the supply voltage pin, and ranges from +2.7 V to +3.6 V.
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STTS424E02
3
Temperature sensor operation
Temperature sensor operation
The temperature sensor continuously monitors the ambient temperature and updates the
temperature data register at least eight times per second. Temperature data is latched
internally by the device and may be read by software from the bus host at any time.
The SMBus/I2C slave address selection pins allow up to 8 such devices to co-exist on the
same bus. This means that up to 8 memory modules can be supported, given that each
module has one such slave device address slot.
After initial power-on, the configuration registers are set to the default values. The software
can write to the configuration register to set bits per the bit definitions in Section 3.1:
SMBus/I2C communications.
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For details of operation and usage of 2 Kb SPD EEPROM, refer to Section 5: SPD
EEPROM operation.
3.1
SMBus/I2C
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communications
The registers in this device are selected by the pointer register. At power-up, the pointer
register is set to “00”, which is the capability register location. The pointer register latches
the last location it was set to. Each data register falls into one of three types of user
accessibility:
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1.
Read-only
2.
Write-only, and
3.
WRITE/READ same address
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A WRITE to this device will always include the address byte and the pointer byte. A WRITE
to any register other than the pointer register, requires two data bytes.
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Reading this device is achieved in one of two ways:
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Note:
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If the location latched in the pointer register is correct (most of the time it is expected
that the pointer register will point to one of the read temperature registers because that
will be the data most frequently read), then the READ can simply consist of an address
byte, followed by retrieval of the two data bytes.
If the pointer register needs to be set, then an address byte, pointer byte, repeat start,
and another address byte will accomplish a READ.
The data byte transfers the MSB first. At the end of a READ, this device can accept either an
acknowledge (ACK) or no acknowledge (NoACK) status from the master. The NoACK status
is typically used as a signal for the slave that the master has read its last byte. This device
subsequently takes up to 125 ms to measure the temperature.
STTS424E02 does not initiate clock stretching which is an optional I2C bus feature.
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Temperature sensor operation
Figure 4.
STTS424E02
SMBus/I2C write to pointer register
1
SCL
9
1
9
SDA
0
0
1
Start
by
Master
1
A2 A1 A0 R/W
0
0
0
0
0
D2 D1 D0
Pointer Byte
Address Byte
ACK
by
STTS424E02
ACK
by
STTS424E02
AI12264
Figure 5.
1
SCL
9
0
0
Start
by
Master
1
1
A2 A1 A0 R/W
9
SDA
(continued)
Repeat
Start
by
Master
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0
1
0
0
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0
)
(s
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1
Pr
A2 A1 A0 R/W
0
D2 D1 D0
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Pointer Byte
ACK
by
STTS424E02
9
0
0
Address Byte
1
SCL
(continued)
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1
SDA
ACK
by
STTS424E02
1
D15
D14
Address Byte
D13
9
D12 D11 D10
D9
D8
MSB Data Byte
ACK
by
STTS424E02
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SMBus/I2C write to pointer register, followed by a read data word
1
D7
9
D6
D5
D4
D3
D2
LSB Data Byte
ACK
by
Master
D1
D0
Stop
Cond.
No ACK
by
by
Master
Master
AI12265
Doc ID 13448 Rev 8
STTS424E02
Temperature sensor operation
Figure 6.
SMBus/I2C write to pointer register, followed by a write data word
1
SCL
9
1
9
SDA
0
0
Start
by
Master
SCL
(continued)
SDA
(continued)
1
1
A2 A1 A0 R/W
0
0
0
0
0
D2 D1 D0
Pointer Byte
Address Byte
ACK
by
STTS424E02
ACK
by
STTS424E02
1
D15
9
D14
D13
D12 D11 D10
D9
D8
1
D7
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9
D6
MSB Data Byte
D5
D4
D3
D2
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LSB Data Byte
ACK
by
STTS424E02
D1
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Stop
Cond.
ACK
by
by
Master
STTS424E02
AI14012
3.2
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SMBus/I C slave sub-address
decoding
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2
The physical address for the TS is different than that used by the EEPROM. The TS physical
address is binary 0 0 1 1 A2 A1 A0 RW, where A2, A1, and A0 are the three slave subaddress pins, and the LSB “RW” is the READ/WRITE flag.
The EEPROM physical address is binary 1 0 1 0 A2 A1 A0 RW for the memory array and is
0 1 1 0 A2 A1 A0 RW for permanently set write protection mode.
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Temperature sensor operation
STTS424E02
SMBus/I2C AC timing consideration
3.3
In order for this device to be both SMBus- and I2C-compatible, it complies to a subset of
each specification. The requirements which enable this device to co-exist with devices on
either an SMBus or an I2C bus include:
Note:
●
The SMBus minimum clock frequency is required.
●
The 300 ns SMBus data hold time (THD:DAT) is required (see Figure 7 and Table 2 on
page 15.
●
The SMBus timeout is maximum 50 ms (temperature sensor only).
Since the voltage levels are specified only within 3.3 V ±10%, there are no compatibility
concerns with the SMBus/I2C DC specifications.
Figure 7.
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SMBus/I2C timing diagram
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tR
tLOW
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tF
SCL
VIH
VIL
let
tHD:STA
tHIGH
tBUF
tHD:DAT
SDA
VIH
VIL
P
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tSU:DAT
O
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Doc ID 13448 Rev 8
tSU:STA
tSU:STO
S
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A12266
STTS424E02
Temperature sensor operation
AC SMBus and I2C compatibility timings
Table 2.
DA package
DN package
Min
Max
Min
Max
Bus free time between stop (P) and start (S) conditions
4.7
–
1.3
–
µs
Hold time after (repeated) start condition. After this
period, the first clock cycle is generated.
4.0
–
0.6
–
µs
Repeated start condition setup time
4.7
–
0.6
–
µs
Clock high period
4.0
–
0.6
–
µs
Clock low period
4.7
–
1.3
–
µs
300
Symbol
tBUF
tHD:STA
tSU:STA(1)
tHIGH
tLOW
(2)
Parameter
Units
tF
Clock/data fall time
–
300
–
tR
Clock/data rise time
–
1000
–
ns
–
ns
300
–
ns
–
0.6
–
µs
–
10
–
10
ms
10
100
10
400
KHz
25
50
25
50
ms
Data setup time
250
–
tHD:DAT
Data hold time
300
–
tSU:STO
Stop condition setup time
4.0
tW
fSCL
ttimeout
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SMBUS/I2C clock frequency
bs
Bus timeout (temperature sensor only)
1. For a restart condition, or following a WRITE cycle.
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WRITE time for EEPROM
ct
ns
300
tSU:DAT
(3)
(s)
100
O
)
2. STTS424E02 will not initiate clock stretching which is an I2C bus optional feature.
3. This parameter reflects maximum WRITE time for EEPROM.
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Temperature sensor registers
4
STTS424E02
Temperature sensor registers
The temperature sensor component is comprised of various user-programmable registers.
These registers are required to write their corresponding addresses to the pointer register.
They can be accessed by writing to their respective addresses (see Table 3). Pointer
register bits 7-3 must always be written to '0' (see Table 4). This must be maintained, as not
setting these bits to '0' may keep the device from performing to specifications.
The main registers include:
●
Capability register (read-only)
●
Configuration register (read/write)
●
Temperature register (read-only)
●
Temperature trip point registers (R/W), including
–
Alarm temperature upper boundary,
–
Alarm temperature lower boundary, and
–
Critical temperature.
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●
Manufacturer ID register format
●
Device ID and device revision ID register format
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See Table 5 on page 17 for pointer register selection bit details.
Table 3.
Address (Hex)
Not applicable
00
01
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Register name
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Address pointer
Power-on default
Undefined
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Capability
C-grade
0x002D
B-grade
0x002F
od
Configuration
0x0000
Alarm temperature upper boundary trip
0x0000
03
Alarm temperature lower boundary trip
0x0000
04
Critical temperature trip
0x0000
05
Temperature
06
Manufacturer’s ID
07
Device ID/revision
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Temperature sensor registers summary
Table 4.
Undefined
0x104A
DA package
0x0000
DN package
0x0001
Pointer register format
MSB
LSB
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0
0
0
0
0
P2
P1
P0
Pointer/register select bits
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Doc ID 13448 Rev 8
STTS424E02
Table 5.
Temperature sensor registers
Pointer register select bits (type, width, and default values)
P2
P1
P0
0
0
0
Name
Default state
(POR)
Width Type
(bits) (R/W)
Register description
C-grade
CAPA
Thermal sensor capabilities
0x002D
16
R
B-grade
0x002F
0
0
1
CONF
Configuration
16
R/W
0x0000
0
1
0
UPPER
Alarm temperature upper boundary
16
R/W
0x0000
0
1
1
LOWER
Alarm temperature lower boundary
16
R/W
0x0000
1
0
0
CRITICAL Critical temperature
16
R/W
0x0000
1
0
1
TEMP
Temperature
16
R
1
1
0
MANU
Manufacturer ID
16
R
1
1
1
ID
Device ID/revision
DA package
du
16
DN package
4.1
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Capability register (read-only)
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P
R
0x0000
0x104A
0x0000
0x0001
This 16-bit register is read-only, and provides the TS capabilities which comply with the
minimum JEDEC JC 42.4 specifications (see Table 6 and Table 7 on page 18). The
STTS424E02 provides temperatures at 0.25 resolution (10-bit).
4.1.1
)
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Alarm window trip
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The device provides a comparison window with an upper temperature trip point in the alarm
upper boundary register, and a lower trip point in the alarm lower boundary register. When
enabled, the event output will be triggered whenever entering or exiting (crossing above or
below) the alarm window.
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4.1.2
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Critical trip
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The device can be programmed in such a way that the event output is only triggered when
the temperature exceeds the critical trip point. The critical temperature setting is
programmed in the critical temperature register. When the temperature sensor reaches the
critical temperature value in this register, the device is automatically placed in comparator
mode, which means that the critical event output cannot be cleared by using software to set
the clear event bit.
Doc ID 13448 Rev 8
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Temperature sensor registers
Table 6.
STTS424E02
Capability register format
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
RFU
RFU
RFU
RFU
RFU
RFU
RFU
RFU
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
RFU
RFU
VHV
TRES1
TRES0
Wider
range
Higher
precision
Alarm and
critical trips
Table 7.
Capability register bit definitions
Bit
0
Basic capability
– 0 = Alarm and critical trips turned OFF.
– 1 = Alarm and critical trips turned ON.
1
Accuracy
– 0 = Accuracy ±2 °C over the active range and ±3 °C over the monitoring range
(C-Grade).
– 1 = High accuracy ±1 °C over the active range and ±2 °C over the monitoring range
(B-Grade) (default).
2
Range width
– 0 = Values lower than 0 °C will be clamped and represented as binary value '0'.
– 1 = Temperatures below 0 °C can be read and the Sign bit will be set accordingly.
4:3
Temperature resolution
– 01 = This 10-bit value is fixed for STTS424E02, providing temperatures at 0.25 °C
resolution (LSB).
5
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(VHV) High voltage support for A0 (pin 1)
– 1 = STTS424E02 supports a voltage up to 10 volts on the A0 pin - (default)
P
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15:6
Reserved
These values must be set to '0'.
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Definition
Doc ID 13448 Rev 8
STTS424E02
4.2
Temperature sensor registers
Configuration register (read/write)
The 16-bit configuration register stores various configuration modes that are used to set up
the sensor registers and configure according to application and JEDEC requirements (see
Table 8 on page 19 and Table 9 on page 20).
4.2.1
Event thresholds
All event thresholds use hysteresis as programmed in register address 0x01 (bits 10 through
9) to be set when they de-assert.
4.2.2
Interrupt mode
)
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The interrupt mode allows an event to occur where software may write a '1' to the clear
event bit (bit 5) to de-assert the event interrupt output until the next trigger condition occurs.
4.2.3
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Comparator mode
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P
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Comparator mode enables the device to be used as a thermostat. READs and WRITEs on
the device registers will not affect the event output in comparator mode. The event signal will
remain asserted until temperature drops outside the range or is re-programmed to make the
current temperature “out of range”.
4.2.4
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Shutdown mode
s
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The STTS424E02 features a shutdown mode which disables all power-consuming activities
(e.g. temperature sampling operations), and leaves the serial interface active. This is
selected by setting shutdown bit (bit 8) to '1'. In this mode, the devices consume the
minimum current (ISHDN), as shown in Table 27 on page 38.
)
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Note:
Bit 8 cannot be set to '1' while bits 6 and 7 (the lock bits) are set to '1'.
d
o
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The device may be enabled for continuous operation by clearing bit 8 to '0'. In shutdown
mode, all registers may be read or written to. Power recycling will also clear this bit and
return the device to continuous mode as well.
P
e
let
Table 8.
O
o
s
b
Configuration register format
Bit15
Bit14
Bit13
Bit12
Bit11
RFU
RFU
RFU
RFU
RFU
Bit7
Bit6
Bit5
Bit4
Bit3
Critical
lock bit
Alarm lock
bit
Clear
event
Bit10
Hysteresis Hysteresis
Bit2
Event output Event output
Critical
status
control
event only
Doc ID 13448 Rev 8
Bit9
Bit8
Shutdown
mode
Bit1
Bit0
Event
polarity
Event
mode
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Temperature sensor registers
Table 9.
STTS424E02
Configuration register bit definitions
Bit
Definition
0
Event mode
– 0 = Comparator output mode (this is the default).
– 1 = Interrupt mode; when either of the lock bits is set, this bit cannot be altered until it is unlocked.
1
Event polarity(1)
The event polarity bit controls the active state of the EVENT pin. The EVENT pin is driven to this state
when it is asserted.
– 0 = Active-low (this is the default). Requires a pull-up resistor to set the inactive state of the opendrain output. The power to the pull-up resistor should not be greater than VDD + 0.2 V. Active
state is logical “0”.
– 1 = Active-high. The active state of the pin is then logical “1”.
2
Critical event only
– 0 = Event output on alarm or critical temperature event (this is the default).
– 1 = Event only if the temperature is above the value in the critical temperature register; when the alarm
window lock bit is set, this bit cannot be altered until it is unlocked.
3
Event output control
– 0 = Event output disabled (this is the default).
– 1 = Event output enabled; when either of the lock bits is set, this bit cannot be altered until it is unlocked.
4
Event status (read-only)(2)
– 0 = Event output condition is not being asserted by this device.
– 1 = Event output condition is being asserted by this device via the alarm window or critical trip event.
5
Clear event (write-only)(3)
– 0 = No effect.
– 1 = Clears the active event in interrupt mode.
6
Alarm window lock bit
– 0 = Alarm trips are not locked and can be altered (this is the default).
– 1 = Alarm trip register settings cannot be altered. This bit is initially cleared. When set, this bit returns a
logic '1' and remains locked until cleared by an internal power-on reset. These bits can be written to with
a single WRITE, and do not require double WRITEs.
)
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8
20/50
Critical trip lock bit
– 0 = Critical trip is not locked and can be altered (this is the default).
– 1 = Critical trip register settings cannot be altered. This bit is initially cleared. When set, this bit returns a
logic '1' and remains locked until cleared by an internal power-on reset. These bits can be written to with
a single WRITE, and do not require double WRITEs.
Shutdown mode
– 0 = TS is enabled (this is the default).
– 1 = Shutdown TS when the shutdown, device, and A/D converter are disabled in order to save power. No
event conditions will be asserted; when either of the lock bits is set, this bit cannot be altered until it is
unlocked. However, it can be cleared at any time.
Doc ID 13448 Rev 8
STTS424E02
Table 9.
Temperature sensor registers
Configuration register bit definitions
Bit
Definition
10:9
Hysteresis enable (see Figure 8 and Table 10)
– 00 = Hysteresis is disabled (this is the default).
– 01 = Hysteresis is enabled at 1.5 °C.
– 10 = Hysteresis is enabled at 3 °C.
– 11 = Hysteresis is enabled at 6 °C.
Hysteresis applies to all limits when the temperature is dropping below the threshold so that once the
temperature is above a given threshold, it must drop below the threshold minus the hysteresis in order to
be flagged as an interrupt event. Note that hysteresis is also applied to the EVENT pin functionality. When
either of the lock bits is set, these bits cannot be altered.
15:11
Reserved for future use. These bits will always read ‘0’ and writing to them will have no effect. For
future compatibility, all RFU bits must be programmed as ‘0’.
1.
)
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As this device is used in DIMM (memory modules) applications, it is strongly recommended that only the active-low polarity (default) is used.
This is the recommended configuration for the STTS424E02.
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2. The actual incident causing the event can be determined from the read temperature register. Interrupt events can be cleared by writing to the
clear event bit (writing to this bit will have no effect on overall device functioning).
3.
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Writing to this register has no effect on overall device functioning in comparator mode. When read, this bit will always return a logic '0' result.
Figure 8.
t
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Hysteresis
TH
s
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TH - HYS
)
(s
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TL
TL - HYS
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Below Window bit
t
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Above Window bit
AI12270
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1. TH = Value stored in the alarm temperature upper boundary trip register.
2. TL = Value stored in the alarm temperature lower boundary trip register.
3. HYS = Absolute value of selected hysteresis
Table 10.
Hysteresis as applied to temperature movement
Below alarm window bit
Above alarm window bit
Temperature slope
Temperature
threshold
Temperature slope
Temperature
threshold
Sets
Falling
TL - HYS
Rising
TH
Clears
Rising
TL
Falling
TH - HYS
Doc ID 13448 Rev 8
21/50
Temperature sensor registers
4.2.5
STTS424E02
Event output pin functionality
The event outputs can be programmed to be configured as either a comparator output or as
an interrupt. This is done by enabling the output control bit (bit 3) and setting the event
mode bit (bit 0). The output pin polarity can also be specified as active-high or active-low by
setting the event polarity bit (bit 1).
When the hysteresis bits (bits 10 and 9) are enabled, hysteresis may be used to sense
temperature movement around trigger points. For example, when using the “Above Alarm
window” bit (temperature register bit 14, see Table 12 on page 24) and hysteresis is set to
3 °C, as the temperature rises, bit 14 is set (bit 14 = 1). The temperature is above the alarm
window and the temperature register contains a value that is greater than the value set in
the alarm temperature upper boundary register (see Table 15 on page 25).
)
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If the temperature decreases, bit 14 will remain set until the measured temperature is less
than or equal to the value in the alarm temperature upper boundary register minus 3 °C (see
Figure 8 on page 21 and Table 10 on page 21 for details.
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Similarly, when using the “Below Alarm window” bit (temperature register bit 13, see
Table 12 on page 24) will be set to '0'. The temperature is equal to or greater than the value
set in the alarm temperature lower boundary register (see Table 16 on page 25). As the
temperature decreases, bit 13 will be set to '1' when the value in the temperature register is
less than the value in the alarm temperature lower boundary register minus 3 °C (see
Figure 8 on page 21 and Table 10 on page 21 for details.
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The device will retain the previous state when entering the shutdown mode. If the device
enters the shutdown mode while the EVENT pin is low, the shutdown current will increase
due to the additional event output pull-down current.
)
(s
Note:
Hysteresis is also applied to the EVENT pin functionality. When either of the lock bits (bits 6
and 7) are set, these bits cannot be altered.
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22/50
Doc ID 13448 Rev 8
STTS424E02
Temperature sensor registers
Figure 9.
Event output boundary timings
TCRIT - THYS
TCRIT
TUPPER - THYS
TUPPER - THYS
TUPPER
TA
TLOWER - THYS
TLOWER
Event Output (active-low)
TLOWER - THYS
)
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Comparator
Interrupt
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P
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S/W Int. Clear
t
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Critical
1
Table 11.
Note
)
(s
1 3
4
s
b
O
35 7 6 4
2
ai12271
Legend for Figure 9: Event output boundary timings.
t
c
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Event output
TA bits
Event output boundary conditions
od
Comparator Interrupt Critical
15
14
13
TA ≥ TLOWER
H
L
H
0
0
0
TA < TLOWER - THYS
L
L
H
0
0
1
TA > TUPPER
L
L
H
0
1
0
4
TA ≤ TUPPER - THYS
H
L
H
0
0
0
5
TA ≥ TCRIT
L
L
L
1
1
0
6
TA < TCRIT - THYS
L
H
H
0
1
0
1
2
3
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2
7
Pr
When TA ≥ TCRIT and TA < TCRIT - THYS, the event output is in comparator mode and bit 0 of
the configuration register (interrupt mode) is ignored.
Doc ID 13448 Rev 8
23/50
Temperature sensor registers
4.3
STTS424E02
Temperature register (read-only)
This 16-bit, read-only register stores the temperature measured by the internal band gap TS
as shown in Table 12. The STTS424E02 meets the JEDEC mandatory 0.25 °C resolution
requirement. When reading this register, the MSBs (bit 15 to bit 8) are read first, and then
the LSBs (bit 7 to bit 0) are read. The result is the current-sensed temperature. The data
format is 2s complement with one LSB = 0.25 °C. The MSB has a 128 °C resolution.
The trip status bits represent the internal temperature trip detection, and are not affected by
the status of the event or configuration bits (e.g. event output control or clear event). If
neither of the above or below values are set (i.e. both are 0), then the temperature is exactly
within the user-defined alarm window boundaries.
4.3.1
)
s
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Temperature format
The 16-bit value used in the trip point set and temperature read-back registers is 2s
complement, with the LSB equal to 0.0625 °C (see Table 13). For example:
1.
a value of 019Ch represents 25.75 °C,
2.
a value of 07C0h represents 124 °C, and
3.
a value of 1E74h represents –24.75 °C
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All unused resolution bits are set to zero. The MSB will have a resolution of 128 °C. The
STTS424E02 supports the 0.25 °C/LSB only.
s
b
O
The upper 3 bits indicate trip status based on the current temperature, and are not affected
by the event output status.
Table 12.
)
(s
Temperature register format
Bit
15
Above critical
input(1)
Bit
14
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od
Above alarm
window(1)
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Bit
13
Sign
MSB
Bit
12
LSB
Bit Bit Bit Bit Bit Bit Bit Bit Bit
11 10 9
8
7
6
5
4
3
Below alarm
window(1)
Temperature
1. See Table 13 for explanation.
s
b
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Table 13.
Bit
Temperature register bit definitions
Definition with hysteresis = 0
13
Below (temperature) alarm window
– 0 = Temperature is equal to or above the alarm window lower boundary temperature.
– 1 = Temperature is below the alarm window.
14
Above (temperature) alarm window.
– 0 = Temperature is equal to or below the alarm window upper boundary temperature.
– 1 = Temperature is above the alarm window.
15
Above critical trip
– 0 = Temperature is below the critical temperature setting.
– 1 = Temperature is equal to or above the critical temperature setting.
24/50
Doc ID 13448 Rev 8
Bit
2
Bit
1
Bit
0
0
0
STTS424E02
4.4
Temperature sensor registers
Temperature trip point registers (R/W)
The STTS424E02 alarm mode registers provide for 11-bit data in 2s compliment format.
The data provides for one LSB = 0.25 °C. All unused bits in these registers are read as '0'.
The STTS424E02 has three temperature trip point registers (see Table 14):
Note:
●
Alarm temperature upper boundary threshold (Table 15),
●
Alarm temperature lower boundary threshold (Table 16), and
●
Critical temperature trip point value (Table 17).
If the upper or lower boundary threshold values are being altered in-system, all interrupts
should be turned off until a known state can be obtained to avoid superfluous interrupt
activity.
Table 14.
Name
P1
P0
Register description
0
1
0
UPPER
Alarm temperature upper boundary
0
1
1
LOWER
Alarm temperature lower boundary
1
0
0
CRITICAL Critical temperature
Bit
15
Bit
14
Bit
13
0
0
0
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O
16
00 00
R/W
00 00
R/W
00 00
Bit
12
)
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Bit
11
Bit
10
-O
Bit
9
Bit
8
Bit
7
LSB
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Alarm window upper boundary temperature
Bit
1
Bit
0
0
0
Bit
1
Bit
0
0
0
Bit
1
Bit
0
0
0
Alarm temperature lower boundary register format
Bit
15
Bit
14
Bit
13
0
0
0
Table 17.
16
Default
state (POR)
R/W
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P
Table 16.
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Pr
16
Type
(R/W)
Alarm temperature upper boundary register format
Sign
MSB
o
s
b
Width
(bits)
P2
Table 15.
)
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(
ct
Temperature trip point register format
Sign
MSB
Bit
12
LSB
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Alarm window lower boundary temperature
Critical temperature register format
Sign
MSB
Bit
15
Bit
14
Bit
13
0
0
0
Bit
12
LSB
Bit
11
Bit
10
Bit
9
Bit
8
Bit
7
Bit
6
Bit
5
Critical temperature trip point
Doc ID 13448 Rev 8
Bit
4
Bit
3
Bit
2
25/50
Temperature sensor registers
4.5
STTS424E02
Manufacturer ID register (read-only)
The manufacturer’s ID (programmed value 104Ah) in this register is the STMicroelectronics
identification provided by the Peripheral Component Interconnect Special Interest Group
(PCiSIG).
Table 18.
Manufacturer ID register format
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
0
0
0
1
0
0
0
0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0
1
0
0
1
0
1
)
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0
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4.6
Device ID and device revision ID register (read-only)
r
P
e
The device IDs and device revision IDs are maintained in this register. The register format is
shown in Table 19. The device IDs and device revision IDs are currently '0' and will be
incremented whenever an update of the device is made.
Table 19.
Device ID and device revision ID register format
Bit15
Bit14
Bit13
0
0
0
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Bit6
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0
Bit12
)-
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Bit7
0
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Bit11
Bit10
Bit9
Bit8
0
0
0
0
0
Device ID
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0(1)
0
0
0
0
0
0 or 1
Device revision ID
1. DA package, bit0 is 0 (see Table 27 on page 38).
DN package, bit0 is 1 (see Table 27 on page 38).
Doc ID 13448 Rev 8
STTS424E02
SPD EEPROM operation
5
SPD EEPROM operation
5.1
2 Kb SPD EEPROM operation
The 2 Kb serial EEPROM is able to lock permanently the data in its first half (from location
00h to 7Fh). This facility has been designed specifically for use in DRAM DIMMs (dual inline
memory modules) with serial presence detect. All the information concerning the DRAM
module configuration (such as its access speed, its size, its organization) can be kept write
protected in the first half of the memory.
The first half of the memory area can be write-protected using two different software write
protection mechanisms. By sending the device a specific sequence, the first 128 bytes of
the memory become write protected: permanently or resetable.
)
s
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These I2C-compatible electrically erasable programmable memory (EEPROM) devices are
organized as 256x8 bits.
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I2C uses a two wire serial interface, comprising a bi-directional data line and a clock line.
The device carries a built-in 4-bit device type identifier code (1010) in accordance with the
I2C bus definition to access the memory area and a second device type identifier code
(0110) to define the protection. These codes are used together with the voltage level applied
on the three chip enable inputs (A2, A1, A0). These input signals are used to set the value
that is to be looked for on the three least significant bits (b3, b2, b1) of the 7-bit device select
code. In the end application, A0, A1 and A2 must be directly (not through a pull-up or pulldown resistor) connected to VDD or VSS to establish the device select code. When these
inputs are not connected, an internal pull-down circuitry makes (A0,A1,A2) = (0,0,0).
r
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)
(s
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The A0 input is used to detect the VHV voltage, when decoding an SWP or CWP instruction
(refer to Table 20: Device select code).
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The device behaves as a slave device in the I2C protocol, with all memory operations
synchronized by the serial clock. Read and write operations are initiated by a START
condition, generated by the bus master. The START condition is followed by a device select
code and R/W bit (as described in Table 20: Device select code), terminated by an
acknowledge bit.
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5.2
When writing data to the memory, the memory inserts an acknowledge bit during the 9th bit
time, following the bus master’s 8-bit transmission. When data is read by the bus master,
the bus master acknowledges the receipt of the data byte in the same way. Data transfers
are terminated by a STOP condition after an ACK for WRITE, and after a NoACK for READ.
Internal device reset - SPD EEPROM
In order to prevent inadvertent write operations during power-up, a power on reset (POR)
circuit is included.
At power-up (phase during which VDD is lower than VDDmin but increases continuously), the
device will not respond to any instruction until VDD has reached the power on reset
threshold voltage (this threshold is lower than the minimum VDD operating voltage defined in
Table 2: AC SMBus and I2C compatibility timings). Once VDD has passed the POR
threshold, the device is reset.
Doc ID 13448 Rev 8
27/50
SPD EEPROM operation
STTS424E02
Prior to selecting the memory and issuing instructions, a valid and stable VDD voltage must
be applied. This voltage must remain stable and valid until the end of the transmission of the
instruction and, for a write instruction, until the completion of the internal write cycle (tW).
At power-down (phase during which VDD decreases continuously), as soon as VDD drops
from the normal operating voltage below the power on reset threshold voltage, the device
stops responding to any instruction sent to it.
Table 20.
Device select code
Chip enable
signals
Memory area select code
(two arrays)(2)
A2
A1
A0
Set write protection
(SWP)
VSS
VSS
VHV
Clear write protection
(CWP)
VSS
VDD
VHV
Permanently set write
protection (PSWP)(2)
A2
A1
A0
Read SWP
VSS
VSS
VHV
Read CWP
VSS
VDD
VHV
Read PSWP(2)
A2
A1
A0
)
(s
1. The most significant bit, b7, is sent first.
Device type identifier
Chip enable bits
R/W
b7(1)
b6
b5
b4
b3
b2
1
0
1
0
A2
A1
A0
R/W
0
0
1
0
0
1
1
0
A2
A1
A0
0
0
0
1
1
0
1
1
1
A2
A1
A0
1
0
1
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0
b0
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1
b1
2. A0, A1 and A2 are compared against the respective external pins on the memory device.
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5.3
Memory addressing
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r
To start communication between the bus master and the slave device, the bus master must
initiate a Start condition. Following this, the bus master sends the device select code, shown
in Table 20: Device select code (on serial data (SDA), most significant bit first).
P
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The device select code consists of a 4-bit device type identifier, and a 3-bit chip enable
“Address” (A2, A1, A0). To address the memory array, the 4-bit device type identifier is
1010b; to access the write-protection settings, it is 0110b.
Up to eight memory devices can be connected on a single I2C bus. Each one is given a
unique 3-bit code on the chip enable (A0, A1, A2) inputs. When the device select code is
received, the device only responds if the chip enable address is the same as the value on
the chip enable (A0, A1, A2) inputs.
The 8th bit is the Read/Write bit (R/W). This bit is set to 1 for read and 0 for write operations.
If a match occurs on the device select code, the corresponding device gives an
acknowledgment on serial data (SDA) during the 9th bit time. If the device does not match
the device select code, it deselects itself from the bus, and goes into standby mode. The
operating modes are detailed in Table 21.
28/50
Doc ID 13448 Rev 8
STTS424E02
SPD EEPROM operation
Table 21.
Operating modes
Mode
R/W bit
Bytes
1
1
Current address read
Initial sequence
START, device select, R/W = 1
0
START, device select, R/W = 0, address
Random address read
1
reSTART, device select, R/W = 1
1
Sequential read
1
≥1
Byte write
0
1
START, device select, R/W = 0
Page write
0
≤ 16
START, device select, R/W = 0
TS write
0
2
START, device select, R/W = 0, pointer data, stop
TS read
1
2
START, device select, R/W = 1, pointer data, stop
Similar to current or random address read
)
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Figure 10. Result of setting the write protection
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P
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FFh
Standard
Array
Memory
Area
t
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80h
7Fh
Standard
Array
00h
s
b
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Default EEPROM memory area
state before write access
to the Protect Register
)
(s
FFh
Standard
Array
Write
Protected
Array
80h
7Fh
00h
State of the EEPROM memory
area after write access
to the Protect Register
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AI01936c
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5.4
Setting the write protection
P
e
The Write Control (WC) is tied low, hence the write protection of the memory array is
dependent on whether software write-protection has been set.
s
b
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Software write-protection allows the bottom half of the memory area (addresses 00h to 7Fh)
to be write protected irrespective of subsequent states of the write control (WC) signal.
Software write-protection is handled by three instructions:
●
SWP: Set write protection
●
CWP: Clear write protection
●
PSWP: Permanently set write protection
The level of write-protection (set or cleared) that has been defined using these instructions,
remains defined even after a power cycle.
Doc ID 13448 Rev 8
29/50
SPD EEPROM operation
5.4.1
STTS424E02
SWP and CWP
If the software write-protection has been set with the SWP instruction, it can be cleared
again with a CWP instruction.
The two instructions (SWP and CWP) have the same format as a byte write instruction, but
with a different device type identifier (as shown in Table 20). Like the byte write instruction, it
is followed by an address byte and a data byte, but in this case the contents are all “Don’t
Care” (Figure 11). Another difference is that the voltage, VHV, must be applied on the A0 pin,
and specific logical levels must be applied on the other two address pins A1 and A2 (as
shown in Table 20).
5.4.2
PSWP
)
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If the software write-protection has been set with the PSWP instruction, the first 128 bytes of
the memory are permanently write-protected. This write-protection cannot be cleared by any
instruction, or by power-cycling the device. Also, once the PSWP instruction has been
successfully executed, the SPD EEPROM no longer acknowledges any instruction (with a
device type identifier of 0110) to access the write-protection settings.
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START
BUS ACTIVITY
MASTER
s
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WORD
ADDRESS
bs
O
)
SDA LINE
BUS ACTIVITY
t
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CONTROL
BYTE
ACK
ACK
STOP
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Figure 11. Setting the write protection
DATA
ACK
VALUE
VALUE
(DON'T CARE) (DON'T CARE)
AI01935b
5.5
r
P
Write
operations
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Following a start condition the bus master sends a device select code with the R/W bit reset
to 0. The device acknowledges this, as shown in Figure 12, and waits for an address byte.
The device responds to the address byte with an acknowledge bit, and then waits for the
data byte.
When the bus master generates a stop condition immediately after the ACK bit (in the “10th
bit” time slot), either at the end of a byte write or a page write, the internal memory write
cycle is triggered. A stop condition at any other time slot does not trigger the internal write
cycle.
During the internal write cycle, serial data (SDA) and serial clock (SCL) are ignored, and the
device does not respond to any requests.
30/50
Doc ID 13448 Rev 8
STTS424E02
5.5.1
SPD EEPROM operation
Byte write
After the device select code and the address byte, the bus master sends one data byte. If
the addressed location is hardware write-protected, the device replies to the data byte with
NoACK, and the location is not modified. If, instead, the addressed location is not writeprotected, the device replies with ACK. The bus master terminates the transfer by
generating a stop condition, as shown in Figure 12.
5.5.2
Page write
The page write mode allows up to 16 bytes to be written in a single write cycle, provided that
they are all located in the same page in the memory: that is, the most significant memory
address bits are the same. If more bytes are sent than will fit up to the end of the page, a
condition known as ‘roll-over’ occurs. This should be avoided, as data starts to become
overwritten in an implementation dependent way.
)
s
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The bus master sends from 1 to 16 bytes of data, each of which is acknowledged by the
device. After each byte is transferred, the internal byte address counter (the 4 least
significant address bits only) is incremented. The transfer is terminated by the bus master
generating a stop condition.
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Figure 12. Write mode sequences in a non write-protected area of SPD
s
b
O
ACK
DEV SEL
START
s
(
t
c
ro
du
t
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bs
DEV SEL
ACK
BYTE ADDR
ACK
DATA IN 1
DATA IN 2
R/W
ACK
ACK
DATA IN N
STOP
P
e
DATA IN
R/W
ACK
START
PAGE WRITE
BYTE ADDR
ACK
STOP
)-
BYTE WRITE
ACK
O
AI01941
Doc ID 13448 Rev 8
31/50
SPD EEPROM operation
5.5.3
STTS424E02
Write cycle polling using ACK
During the internal write cycle, the device disconnects itself from the bus, and writes a copy
of the data from its internal latches to the memory cells. The maximum write time (tw) is
shown inTable 2: AC SMBus and I2C compatibility timings , but the typical time is shorter. To
make use of this, a polling sequence can be used by the bus master.
The sequence, as shown in Figure 13, is:
●
Initial condition: a write cycle is in progress.
●
Step 1: the bus master issues a start condition followed by a device select code (the
first byte of the new instruction).
●
Step 2: if the device is busy with the internal write cycle, no ACK will be returned and
the bus master goes back to step 1. If the device has terminated the internal write
cycle, it responds with an ACK, indicating that the device is ready to receive the second
part of the instruction (the first byte of this instruction having been sent during step 1).
)
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Figure 13. Write cycle polling flowchart using ACK
r
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WRITE Cycle
in Progress
t
e
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START Condition
s
b
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DEVICE SELECT
with RW = 0
)
(s
NO
First byte of instruction
with RW = 0 already
decoded by the device
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NO
ACK
Returned
YES
Next
Operation is
Addressing the
Memory
YES
Send Address
and Receive ACK
ReSTART
STOP
NO
START
Condition
YES
DATA for the
WRITE Operation
DEVICE SELECT
with RW = 1
Continue the
WRITE Operation
Continue the
Random READ Operation
AI01847c
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Doc ID 13448 Rev 8
STTS424E02
5.6
SPD EEPROM operation
Read operations - SPD
Read operations are performed independently of whether hardware or software protection
has been set.
The device has an internal address counter which is incremented each time a byte is read.
Figure 14. Read mode sequences - SPD
ACK
DATA OUT
STOP
R/W
ACK
START
DEV SEL(1)
ACK
R/W
b
O
s
b
O
ACK
NO ACK
DATA OUT N
ACK
DEV SEL(1)
ACK
ACK
DEV SEL(1)
BYTE ADDR
R/W
ACK
ACK
DATA OUT 1
R/W
NO ACK
DATA OUT N
STOP
so
e
t
e
l
u
d
o
DATA OUT
R/W
s
(
t
c
du
o
r
P
)-
START
SEQUENTIAL
RANDOM
READ
R/W
DATA OUT 1
START
START
DEV SEL
ACK
NO ACK
r
P
e
t
e
l
o
ACK
SEQUENTIAL
CURRENT
READ
ACK
DEV SEL(1)
BYTE ADDR
START
RANDOM
ADDRESS
READ
)
s
(
ct
STOP
START
DEV SEL
STOP
CURRENT
ADDRESS
READ
NO ACK
AI01942
1. The seven most significant bits of the device select code of a random read (in the 1st and 3rd bytes) must
be identical.
5.6.1
Random address read - SPD
A dummy write is first performed to load the address into this address counter (as shown in
Figure 14) but without sending a stop condition. Then, the bus master sends another start
condition, and repeats the device select code, with the R/W bit set to 1. The device
acknowledges this, and outputs the contents of the addressed byte. The bus master must
not acknowledge the byte, and terminates the transfer with a stop condition.
Doc ID 13448 Rev 8
33/50
SPD EEPROM operation
5.6.2
STTS424E02
Current address read - SPD
For the current address read operation, following a start condition, the bus master only
sends a device select code with the R/W bit set to 1. The device acknowledges this, and
outputs the byte addressed by the internal address counter. The counter is then
incremented. The bus master terminates the transfer with a stop condition, as shown in
Figure 14, without acknowledging the byte.
5.6.3
Sequential read - SPD
This operation can be used after a current address read or a random address read. The bus
master does acknowledge the data byte output, and sends additional clock pulses so that
the device continues to output the next byte in sequence. To terminate the stream of bytes,
the bus master must not acknowledge the last byte, and must generate a stop condition, as
shown in Figure 14.
)
s
(
ct
The output data comes from consecutive addresses, with the internal address counter
automatically incremented after each byte output. After the last memory address, the
address counter ‘rolls-over’, and the device continues to output data from memory address
00h.
u
d
o
5.6.4
r
P
e
t
e
l
o
Acknowledge in read mode
For all read commands, the device waits, after each byte read, for an acknowledgment
during the 9th bit time. If the bus master does not drive serial data (SDA) low during this
time, the device terminates the data transfer and switches to its standby mode.
)
(s
s
b
O
Table 22 and Table 23 show how the ACK bits can be used to identify the write-protection
status.
Table 22.
t
c
u
Acknowledge when writing data or defining the write-protection (instructions with
R/W bit=0)
Status
WC
Input
Level
P
e
let
Permanently
protected
o
s
b
d
o
r
Instruction
ACK
PSWP, SWP or CWP NoACK
ACK
Data byte
ACK
Write
cycle(tW)
Not
significant
NoACK
Not
significant
NoACK
No
X
O
Page or byte write in
lower 128 bytes
ACK
Address
ACK
Data
NoACK
No
SWP
NoACK
Not
significant
NoACK
Not
significant
NoACK
No
CWP
ACK
Not
significant
ACK
Not
significant
ACK
Yes
PSWP
ACK
Not
significant
ACK
Not
significant
ACK
Yes
Page or byte write in
lower 128 bytes
ACK
Address
ACK
Data
NoACK
No
PSWP, SWP or CWP
ACK
Not
significant
ACK
Not
significant
ACK
Yes
Page or byte write
ACK
Address
ACK
Data
ACK
Yes
Protected with
SWP
0
0
Not Protected
34/50
Address
Doc ID 13448 Rev 8
STTS424E02
Table 23.
SPD EEPROM operation
Acknowledge when reading the write protection (instructions with R/W bit=1)
Status
Instruction
ACK
Address
ACK
Data byte
ACK
Permanently
protected
PSWP, SWP or CWP
NoACK
Not significant
NoACK
Not significant
NoACK
SWP
NoACK
Not significant
NoACK
Not significant
NoACK
CWP
ACK
Not significant
NoACK
Not significant
NoACK
PSWP
ACK
Not significant
NoACK
Not significant
NoACK
PSWP, SWP or CWP
ACK
Not significant
NoACK
Not significant
NoACK
Protected with
SWP
Not protected
5.7
)
s
(
ct
Initial delivery state - SPD
The device is delivered with all bits in the memory array set to ‘1’ (each byte contains FFh).
u
d
o
r
P
e
t
e
l
o
)
(s
s
b
O
t
c
u
d
o
r
P
e
t
e
l
o
s
b
O
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Use in a memory module
6
STTS424E02
Use in a memory module
In the dual inline memory module (DIMM) application, the SPD is soldered directly on to the
printed circuit module. The three chip enable inputs (A0, A1, A2) must be connected to VSS
or VDD directly (that is without using a pull-up or pull-down resistor) through the DIMM
socket (see Table 24).
The write control (WC) of the device is tied to ground to maintain full read and write access.
Table 24.
DRAM DIMM connections
DIMM position
A2
A1
0
VSS (0)
VSS (0)
1
VSS(0)
VSS (0)
2
VSS (0)
VDD (1)
3
VSS (0)
VDD (1)
4
VDD (1)
5
VDD (1)
6
VDD (1)
P
e
7
VDD (1)
VSS (0)
t
e
l
o
bs
A0
)
s
(
ct
VSS (0)
VDD (1)
du
ro
VSS (0)
VDD(1)
VSS (0)
VSS (0)
VDD (1)
VDD (1)
VSS (0)
VDD (1)
VDD (1)
O
)
6.1
Programming the SPD
s
(
t
c
The situations in which the SPD EEPROM is programmed can be considered under two
headings:
6.1.1
when the DIMM is isolated (not inserted on the PCB motherboard)
●
when the DIMM is inserted on the PCB motherboard
r
P
e
DIMM isolated
t
e
l
o
s
b
O
6.1.2
u
d
o
●
With specific programming equipment, it is possible to define the SPD EEPROM content,
using byte and page write instructions, and its write-protection using the SWP and CWP
instructions. To issue the SWP and CWP instructions, the DIMM must be inserted in the
application-specific slot where the A0 signal can be driven to VHV during the whole
instruction. This programming step is mainly intended for use by DIMM makers, whose end
application manufacturers will want to clear this write-protection with the CWP on their own
specific programming equipment, to modify the lower 128 bytes, and finally to set
permanently the write-protection with the PSWP instruction.
DIMM inserted in the application motherboard
As the final application cannot drive the A0 pin to VHV, the only possible action is to freeze
the write-protection with the PSWP instruction.
36/50
Doc ID 13448 Rev 8
STTS424E02
7
Maximum ratings
Maximum ratings
Stressing the device above the ratings listed in the absolute maximum ratings table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Table 25.
Absolute maximum ratings
Symbol
TSTG
Parameter
Value
TSLD(1)
Storage temperature
Input or output voltage
VDD
Supply voltage
IO
Output current
PD
Power dissipation
θJA
Thermal resistance
)
s
(
ct
–65 to 150
°C
260
°C
Lead solder temperature for 10 seconds
VIO
Unit
A0
VSS – 0.3 to 10.0
others
u
d
o
V
VSS – 0.3 to 6.5
V
VSS – 0.3 to 6.5
V
10
mA
320
mW
DA package
128
°C/W
DN package
87.4
°C/W
s
b
O
e
t
e
ol
Pr
1. Reflow at peak temperature of 260 °C. The time above 255 °C must not exceed 30 seconds.
)
(s
t
c
u
d
o
r
P
e
t
e
l
o
s
b
O
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DC and AC parameters
8
STTS424E02
DC and AC parameters
This section summarizes the operating measurement conditions, and the DC and AC
characteristics of the device. The parameters in the dc and ac characteristics tables that
follow, are derived from tests performed under the measurement conditions summarized in
Table 26, Operating and AC measurement conditions. Designers should check that the
operating conditions in their circuit match the operating conditions when relying on the
quoted parameters.
Table 26.
Operating and AC measurement conditions
Parameter
Conditions
VDD supply voltage - temperature sensor
2.7 to 3.6
Operating temperature
–40 to 85
Input rise and fall times
≤ 50
Load capacitance
100
Input pulse voltages
Table 27.
IDD1
ISINK
IILI
IILO
38/50
°C
ns
pf
V
0.3 to 0.7VDD
V
Test condition(1)
s
(
t
c
Supply voltage
e
t
e
ol
O
od
Pr
O
)
Description
o
r
P
VDD supply current (no load)
bs
uc
DC/AC characteristics - temperature sensor component with EEPROM
du
IDD
V
o
s
b
Sym
VDD
)
s
(
t
0.2 to 0.8VDD
e
t
e
l
Input and output timing reference voltages
Unit
VDD supply current,
communication only
(no conversions)
TS shutdown mode supply current
SMBUS output low sink current
Input leakage current (SCL, SDA)
Output leakage current
Min
2.7
Typ(2) Max
3.3
EEPROM active, TS shutdown
F = 400 kHz
EEPROM (standby)
active temperature conversions
F = 400 kHz
EEPROM
(standby)
100
Unit
3.6
V
2
mA
210
µA
100 kHz
40
µA
400 kHz
115
µA
DA package at
85 °C
EEPROM standby,
TS shutdown
DN package at
125 °C
SDA forced to 0.6 V
1.0
3
µA
1.0
5
µA
6
mA
VIN = VSS or VDD
±4
µA
VOUT = VSS or VDD,
SDA in Hi-Z
±4
µA
Doc ID 13448 Rev 8
STTS424E02
Table 27.
DC and AC parameters
DC/AC characteristics - temperature sensor component with EEPROM (continued)
Sym
Test condition(1)
VPOR(3)
Description
Accuracy for corresponding range
2.7 V ≤ VDD ≤ 3.6 V
B-grade
Resolution
0.6
V
VDD falling edge:
DN package
2.0
V
+75 °C < TA < +95
±1.0
±2.0
°C
+40 °C < TA < +125
±2.0
±3.0
°C
–40 °C < TA < +125
±3.0
±4.0
°C
+75 °C < TA < +95
±0.5
+40 °C < TA 0.7 VCC
800
kΩ
DA package
–40
85
°C
DN package
–40
125
°C
TA
Ambient operating temperature(3)
1. Guaranteed operating temperature for DA package: TA = –40 °C to 85 °C and for DN package: TA = –40 °C to 125 °C;
VDD = 2.7 V to 3.6 V (except where noted).
2. Typical numbers taken at VDD = 3.3 V, TA = 25 °C.
3. DN is TDFN package max 0.80 mm height.
DA is DFN package max 0.90 mm height.
4. Contact local ST sales office for availability.
Doc ID 13448 Rev 8
39/50
Package mechanical data
9
STTS424E02
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
)
s
(
ct
u
d
o
r
P
e
t
e
l
o
)
(s
s
b
O
t
c
u
d
o
r
P
e
t
e
l
o
s
b
O
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Doc ID 13448 Rev 8
STTS424E02
Package mechanical data
Figure 15. DFN8 – 8-lead dual flat, no-lead (2 mm x 3 mm) package outline (DA)
)
s
(
ct
u
d
o
r
P
e
t
e
l
o
)
(s
1. Drawing is not to scale.
Table 28.
s
b
O
7904084_B
t
c
u
DFN8 – 8-lead dual flat, no-lead (2 mm x 3 mm) mechanical data (DA)
Sym
Pr
od
Min
mm
inches
Typ
Max
Min
Typ
Max
A
e
t
e
ol
0.80
0.85
0.90
0.031
0.033
0.035
A1
0.00
0.00
0.05
0.000
0.000
0.002
b
0.20
0.25
0.30
0.008
0.010
0.012
D
1.95
2.00
2.05
0.077
0.079
0.081
D2
1.35
1.40
1.45
0.053
0.055
0.057
E
2.95
3.00
3.05
0.116
0.118
0.120
E2
1.25
1.30
1.35
0.049
0.051
0.053
A3
s
b
O
0.20
e
L
ddd
0.008
0.50
0.20
0.30
0.020
0.40
0.08
Doc ID 13448 Rev 8
0.008
0.012
0.016
0.003
41/50
Package mechanical data
STTS424E02
Figure 16. TDFN8 – 8-lead thin dual flat, no-lead (2 mm x 3 mm) package outline (DN)
)
s
(
ct
u
d
o
r
P
e
t
e
l
o
bs
8089094_A
O
)
Note:
JEDEC MO-229, variation WCED-3 proposal
Table 29.
TDFN8 – 8-lead thin dual flat, no-lead (2 mm x 3 mm) mechanical data (DN)
s
(
t
c
mm
u
d
o
Sym
Min
r
P
e
A
0.70
let
A1
A3
o
s
b
b
O
0.00
Max
Min
Typ
Max
0.75
0.80
0.028
0.030
0.031
0.00
0.05
0.000
0.000
0.002
0.20
0.008
0.25
0.30
0.008
0.010
0.012
D
1.95
2.00
2.05
0.077
0.079
0.081
D2
1.35
1.40
1.45
0.053
0.055
0.057
E
2.95
3.00
3.05
0.116
0.118
0.120
E2
1.25
1.30
1.35
0.049
0.051
0.053
L
ddd
42/50
Typ
0.20
e
Note:
inches
0.50
0.30
0.35
0.020
0.40
0.08
JEDEC MO-229, variation WCED-3 proposal
Doc ID 13448 Rev 8
0.012
0.014
0.016
0.003
STTS424E02
Package mechanical data
Figure 17. Carrier tape for DFN8 and TDFN8 packages
P0
E
P2
D
T
A0
F
TOP COVER
TAPE
W
B0
P1
CENTER LINES
OF CAVITY
K0
)
s
(
ct
u
d
o
r
P
e
USER DIRECTION OF FEED
Table 30.
AM03073v1
t
e
l
o
Carrier tape dimensions for DFN8 and TDFN8 packages
Package
W
D
DFN8
8.00
+0.30
–0.10
1.50
+0.10/
–0.00
TDFN8
8.00
+0.30
–0.10
1.50
+0.10/
–0.00
E
P0
P2
)
(s
s
b
O
F
4.00
2.00
3.50
1.75
±0.10 ±0.10 ±0.10 ±0.05
r
P
e
od
t
c
u
4.00
2.00
3.50
1.75
±0.10 ±0.10 ±0.10 ±0.05
Unit
Bulk
Qty
A0
B0
K0
P1
T
2.30
±0.10
2.80
±0.10
1.10
±0.01
4.00
±0.10
0.30
±0.05
mm 3000
2.30
±0.10
3.20
±0.10
1.10
±0.10
4.00
±0.10
0.30
±0.05
mm 3000
t
e
l
o
s
b
O
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Package mechanical data
STTS424E02
Figure 18. Reel schematic
T
40mm min.
Access hole
At slot location
B
D
C
G measured
Tape slot
In core for
Full radius
u
d
o
At hub
r
P
e
Tape start
2.5mm min.width
t
e
l
o
Table 31.
)
s
(
ct
N
A
s
b
O
AM04928v1
Reel dimensions for 8 mm carrier tape - TDFN8 and DFN8 packages
A
B
(max)
(min)
180 mm
(7-inch)
1.5 mm
C
)-
s
(
t
c
13 mm
± 0.2 mm
u
d
o
D
N
(min)
(min)
20.2 mm
60 mm
r
P
e
G
8.4 mm
+ 2/–0 mm
T
(max)
14.4 mm
The dimensions given in Table 31 incorporate tolerances that cover all variations on critical
parameters.
t
e
l
o
s
b
O
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STTS424E02
10
Part numbering
Part numbering
Table 32.
Ordering information scheme
Example:
STTS424E02
B
DN
3
F
Device type
STTS424E02(1)
Grade
)
s
(
ct
B: Maximum accuracy 75 °C to 95 °C = ± 1 °C
C: Maximum accuracy 75 °C to 95 °C = ±2 °C(2)
u
d
o
Package
r
P
e
DN = TDFN8 (0.80 mm max height)(3)
t
e
l
o
DA = DFN8 (0.90 mm max height)(4)
Temperature
3 = –40 °C to 125 °C (DN package only)
)
(s
6 = –40 °C to 85 °C (DA package only)
s
b
O
t
c
u
Shipping method
F = ECOPACK® package, tape & reel packing
d
o
r
P
e
1. Not recommended for new design (refer to the STTS2002 as drop-in replacement). Contact ST sales office
for availability.
t
e
l
o
2. Contact local ST sales office for availability.
3. DN package is only available in B accuracy grade and in temperature grade 3.
O
bs
4. DA package available only in temperature grade 6.
For other options, or for more information on any aspect of this device, please contact the
ST sales office nearest you.
Doc ID 13448 Rev 8
45/50
Package marking information
11
STTS424E02
Package marking information
Figure 19. DA package topside marking information (DFN-8L)
E42X (1)
xxxx (2)
)
s
(
ct
ai13907
u
d
o
1. Option codes:
X = B or C accuracy grade. For example, E42C is C-grade.
2. Traceability codes
Note:
Contact local ST sales office for availability.
r
P
e
t
e
l
o
Figure 20. DN package topside marking information (TDFN-8L)
)
(s
t
c
u
d
o
r
s
b
O
E42X (1)
xxxx (2)
xxxx (3)
P
e
t
e
l
o
bs
O
46/50
ai13907b
1. Option codes:
X = B or C accuracy grade. For example, E42C is C-grade.
2. Package/fab code identifier
3. Traceability codes
Doc ID 13448 Rev 8
STTS424E02
12
Landing pattern
Landing pattern
The landing pattern recommendations per the JEDEC proposal for the TDFN package (DN)
are shown in Figure 21.
The preferred implementation with wide corner pads enhances device centering during
assembly, but a narrower option is defined for modules with tight routing requirements.
Figure 21. Landing pattern - TDFN package (DN)
e4
)
s
(
ct
e2
e/2
e
e/2
u
d
o
r
P
e
L
t
e
l
o
K
)-
E3
s
b
O
D2
D2/2
D2/2
s
(
t
c
du
E2/2
E2
o
r
P
E2/2
E3
s
b
O
e
t
e
ol
K
L
b2
b
b
K2
K2
K2
b4
ai14000
Doc ID 13448 Rev 8
47/50
Landing pattern
STTS424E02
Table 33 lists variations of landing pattern implementations, ranked as “Preferred” and
“Minimum Acceptable” based on the JEDEC proposal.
Table 33.
Parameters for landing pattern - TDFN package (DN)
Dimension
Parameter
Description
Min
Nom
Max
D2
Heat paddle width
1.40
-
1.60
E2
Heat paddle height
1.40
-
1.60
E3
Heat paddle centerline to contact inner locus
1.00
-
-
L
Contact length
0.70
K
Heat paddle to contact keepout
0.20
K2
Contact to contact keepout
0.20
)
s
(
ct
e
Contact centerline to contact centerline pitch for inner contacts
b
Contact width for inner contacts
e2
Landing pattern centerline to outer contact centerline, “minimum
acceptable” option(1)
b2
Corner contact width, “minimum acceptable option”(1)
e4
Landing pattern centerline to outer contact centerline, “preferred”
option(2)
b4
Corner contact width, “preferred” option(2)
)-
ol
s
b
O
s
(
t
c
ete
1. Minimum acceptable option to be used when routing prevents preferred width contact.
2. Preferred option to be used when possible.
u
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o
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O
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Doc ID 13448 Rev 8
-
0.80
-
-
-
-
-
0.50
-
0.25
-
0.30
-
0.50
-
0.25
-
0.30
-
0.60
-
0.45
-
0.50
u
d
o
Pr
STTS424E02
13
Revision history
Revision history
Table 34.
Document revision history
Date
Revision
Changes
13-Apr-2007
1
Initial release.
09-May-2007
2
Updated Table 3, 5, 6, 7, 27, 28 and 32.
04-Jun-2007
3
Updated Table 27.
02-Jul-2007
4
Added POR threshold values to Table 27, updated Table 28.
18-Mar-2008
5
Added TDFN package (cover page, Figure 16, Table 29) and landing
pattern recommendations (Figure 21, Table 33); updated Section 1, 2,
Table 2, 3, 5, 6, 7, 11, 19, 25, 27, 28, 29, 32, Figure 2, 15, 19, 20).
12-Jun-2008
6
Updated cover page, Figure 4, 5, 8, 14; Section 4.3.1,Section 5.4.1;
Table 5, 11, 25, 27, 32; added Figure 6; removed TSSOP8 package
throughout datasheet.
08-Oct-2009
7
Reformatted document; added tape and reel specifications (Figure 17,
Table 30); updated Features, text in Section 1, Section 3.1, Section 3.3,
Section 5.3, Section 5.4.2, Section 5.5.2, Section 5.5.3, Section 9;
updated Figure 5, 16, 19, 20, Table 2, 7, 9, 11, 13, 21, 25, 26, 27, 29, 32.
12-Oct-2010
8
Device is not recommended for new design; updated document status,
cover page, Table 32, Figure 19, 20; added Figure 18, Table 31.
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