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STEVAL-ISA019V2

STEVAL-ISA019V2

  • 厂商:

    STMICROELECTRONICS(意法半导体)

  • 封装:

    -

  • 描述:

    BOARD EVAL SMPS L6565 3PHASE APP

  • 数据手册
  • 价格&库存
STEVAL-ISA019V2 数据手册
AN2495 Application note 3-phase 80 W SMPS with very wide-range input voltage based on the L6565 and ESBT® STC04IE170HV 1 Introduction The purpose of this application note is to explain the design of an 80 W 3-phase auxiliary power supply for motor drives and welding applications. To reach a high level system in terms of both efficiency and cost, the L6565 PWM controller has been selected as well as the STC04IE170HV as the main switch. The combination of these STMicroelectronics™ parts provides a highly efficient solution for high DC input voltage, a typical requirement of any three-phase application. The L6565 driver is a variable frequency PWM driver suitable for a design flyback converter working in quasi-resonant mode. It also includes some very useful additional features. The frequency response study reported in the this document is carried out using MATLAB. All the design choices are thoroughly discussed to allow the user to adapt the project to specific needs. The input voltage can also be extended up to 1000 VDC as enough margin exists to do so. Finally, the experimental results are analyzed to better understand the benefits offered by the use of ESBT® in this application. The document is associated with demonstration boards STEVAL-ISA019V1, STEVALISA019V2 and STEVAL-ISA019V3 (Figure 1). Figure 1. April 2011 80 W 3-phase SMPS (working prototype) Doc ID 13127 Rev 5 1/36 www.st.com Contents AN2495 Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 Design specifications and L6565 brief description . . . . . . . . . . . . . . . . 5 3 Flyback stage design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.1 Transformer design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1.1 Core size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1.2 Transformer losses and air gap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1.3 Wire size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4 Base driving circuit design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5 Output circuit design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6 Startup network design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7 Frequency response and loop compensation . . . . . . . . . . . . . . . . . . . 18 8 Efficiency, waveforms and experimental results . . . . . . . . . . . . . . . . . 22 9 Board modifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 10 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2/36 Doc ID 13127 Rev 5 AN2495 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Converter specification data and fixed parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Skin effect AC-DC resistance ratios for square-wave currents. . . . . . . . . . . . . . . . . . . . . . 11 Transfer function main parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Bill of material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Doc ID 13127 Rev 5 3/36 List of figures AN2495 List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. 4/36 80 W 3-phase SMPS (working prototype) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Flyback topology basic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Demonstration board schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Dynamic magnetization curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Relative core losses versus frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Proportional driving schematic and equivalent circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Converter feedback network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Stabilized open loop transfer function G(s) = G1(s) · G2(s) (Bode plots) . . . . . . . . . . . . . . 21 Overall efficiency versus output power for two different values of input voltage. . . . . . . . . 22 Minimum input voltage-maximum load (250 V - 80 W) in steady state. . . . . . . . . . . . . . . . 23 Medium input voltage-maximum load (500 V - 80 W) in steady state . . . . . . . . . . . . . . . . 23 Maximum input voltage-maximum load (850 V - 80 W) in steady state . . . . . . . . . . . . . . . 24 Very low load condition (750 V - 5 W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Low load condition (750 V - 24 W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 High load condition (750 V - 80 W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Proportional base driving circuit relevant waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 STEVAL-ISA019V3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 STEVAL-ISA019V3 schematic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Power transformer EGSTON 45371 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Silk screen (top side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Silk screen (bottom side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Copper tracks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Doc ID 13127 Rev 5 AN2495 2 Design specifications and L6565 brief description Design specifications and L6565 brief description Table 1 lists the converter specification data and the main parameters set for the demonstration board. Table 1. Converter specification data and fixed parameters Symbol Description Values Vinmin Rectified minimum input voltage 250 Vinmax Rectified maximum input voltage 850 Vout Output voltage 1 24 V/3.33 A Vaux Auxiliary output voltage 15 V/0.1 A Pout Maximum output power 80 W h Converter efficiency > 80% F Minimum switching frequency 50 kHz Max. overvoltage limited by clamping circuit 200 V Vspike Figure 2 shows a simplified schematic diagram of a flyback converter. The L6565 features a current mode control and is designed for flyback converters working in quasi-resonant mode and ZVS (zero voltage switching) at turn-on, or at least quasi ZVS, which means valley switching during turn-on. This condition allows the designer to reduce the power losses at turn-on as much as possible. Since the input range is from 250 V up to 850 V, the ZVS is obtained only when Vin = Vinmin = Vfl = 250 V. The L6565 has 8 pins. For a detailed explanation of each pin function, please refer to the L6565 datasheet. Figure 2. Flyback topology basic diagram PKC-136 Doc ID 13127 Rev 5 5/36 6/36 Doc ID 13127 Rev 5 # N& 2   7    2   7 2  2   P& #  5 ,. $ . 1 34#)%(6 #3 #/-0    2    ).6 2  6 $  2 4   6 6&& 2  2  2  344( 6/'43,     344(  TURNS  TURNS $ 344( $ #  N& 6## #  '.$ 6!# # 6##  N& # $ #  N&  K6 2 /54   # :#$ 6## * 6!#   * $ . $ .     P& # N& # 2     .S     0#  )3/  42/.)#  . .AUX $    4, 5  2  6 2  2  2  # 2  #  N& 2  6 3403$ # $ !-V 6$#   * Figure 3. & &53% $ . $ . 4 3 .P  Flyback stage design AN2495 Flyback stage design In Figure 3 the complete schematic of the 80 W SMPS is shown. Demonstration board schematic AN2495 Flyback stage design As commonly known, the voltage stress on the device (power switch) is given by: Equation 1 V off = V inmax – V f l – V spike where Vfl = flyback voltage = (Vout + VF, diode) *Np/Ns and Vspike is the maximum overvoltage allowed by the clamping network. It has been set at 200 V. Np is the number of turns on the primary side, while Ns is the number of turns on the main output secondary winding. Taking into account a 200 V margin, the maximum flyback voltage that can be chosen is: Equation 2 V fl = BV – V inmax – V spike – V m arg in = 1700 – 1000 – 200 – 250 = 250V After calculating the flyback voltage, proceed with the next step in the converter design. The turn ratio between primary and secondary side is calculated with the following equation: Equation 3 V fl N 250 ------p- = ----------------------------------------- = ---------------- = 10 V out + V F, diode 24 + 1 Ns As a first approximation, since the turn-on of the device occurs immediately after the energy stored on the primary side inductance has been totally transferred to the secondary side: Equation 4 V dcmin T onmax = V f l T reset and Equation 5 T onmax + T reset = T S where Tonmax is the maximum on time, Treset is the time needed to demagnetize the transformer inductance and TS is the switching time. Combining the two previous equations, Tonmax is: Equation 6 V fl • T S T onmax = ------------------------------- ≅ 10μs V dcmin + V fl The next step is to calculate the peak current. According to the converter specification in Table 1, output power of 80 W and desired efficiency (at least 80%), by using a formula that does not take into account the losses on the power switch, on the input bridge, and on the rectified network, we have: Equation 7 P IN 1 2 --- • L P IP 2 = 1.25P OU T = ------------------------ = TS Doc ID 13127 Rev 5 1 --- V dcmin2 T onmax2 2 ----------------------------------------------LP TS 7/36 Flyback stage design AN2495 Hence: Equation 8 2 2 V dcmin T onmax L P = ------------------------------------------- = 1.56mH 2.5T S P OUT Now we can calculate the peak current on primary. Equation 9 V dcmin T onmax I P = ------------------------------------- = 1.6A LP 3.1 Transformer design 3.1.1 Core size The core size must be chosen according to the power that must be managed, to the primary inductance, and to the saturation current as well. An approximate but efficient formula could be used as a starting point. Eventually, the designer may choose a bigger core and repeat the following steps. Equation 10 1.316 A P = 10 3 L P I rms ( primary ) ------------------------------------------1 --2 [cm4] ΔT • K u • B max where: ● ΔT is the maximum temperature variation with respect to the ambient temperature ● KU is the utilization factor of the window (say the portion of the window used for winding that generally ranges between 0.4 and 0.7) ● Bmax is the maximum flux in the core. From Equation 10, we can deduct that the final best choice is an ETD34. 3.1.2 Transformer losses and air gap From Faraday's law we can define the minimum primary winding turns to avoid saturation of the core. Looking at the saturation curve of the core, we can safely work up to 200 mT: Equation 11 V in, min • T O ( N, max ) 250 • 10μ N pmin = ------------------------------------------------------ = ------------------------------- = 117 0.200 • 97μ ΔB • A e 8/36 Doc ID 13127 Rev 5 AN2495 Flyback stage design Figure 4. Dynamic magnetization curves Concerning the gap, from the EPCOS datasheet, we can use the following approximate equation: Equation 12 1 ------ AL K2 l g = gaplenght = ⎛ ------⎞ ⎝ K 1⎠ K1 = 153, K2 = -0.713, while AL has to be calculated. Knowing that Lp = 1.56mH and Np = 120, Equation 13 LP 1.56m - = ----------------- = 108nH A L = --------2 2 N P 120 1 ----------------- 108 –0.713 = 1.63mm Hence: l g = gaplenght = ⎛⎝ ----------⎞⎠ 153 Doc ID 13127 Rev 5 9/36 Flyback stage design Figure 5. AN2495 Relative core losses versus frequency From Figure 5, operating at 50 kHz with 220 mT flux excursion, the power dissipation density is about 300 mW/cm3. Once again, referring to the EPCOS datasheet, the total volume of ETD 34 is 7.63 cm3, therefore: Equation 14 P core = 0.3 • 7.6 = 2.29W Assuming a 95% efficiency for the transformer, only 4 W can be lost on it, of which about 2.3 is lost on the core while the residual 1.7 W is dissipated on the copper. Achieving this efficiency is detailed in the following Section 3.1.3: Wire size. 3.1.3 Wire size To chose the right wire size we must know the rms current on both the primary and secondary sides. Since Ipeak, primary = 1.6 A and I peak, secondary = 16 A Equation 15 Irms, primary = 0.65A and I rms, sec ondary = 6.53A By imposing a 1 W loss on the primary side wire, the maximum series resistance can be calculated as follows: From Joule’s law we can calculate the resistance of both the primary and secondary windings. Equation 16 P C U, pri R P = -------------------⇒R P = 2.36Ω 2 I PRMS 10/36 P CU, sec - ⇒R S = 0.016Ω R S = -----------------------2 I SR MS Doc ID 13127 Rev 5 AN2495 Flyback stage design From that, knowing the copper resistivity at 100 °C (ρ 100 = 2.303 10-6 Ω cm), and the average wind length Lt (Lt = 5.6 cm), we can easily calculate the wire sections (in cm2). Equation 17 ρ 100 N p L t –4 A PCU = ------------------------ = 6.54 • 10 RP 2 [ cm ] ⇒d p = 0.028 [ cm ] Equation 18 ρ 100 N S L t A SCU = ------------------------ = 0.0096 RS 2 [ cm ] ⇒d s = 0.011 [ cm ] Table 2 provides the skin effect resistance ratios due to Eddy currents for different frequencies. Table 2. Skin effect AC-DC resistance ratios for square-wave currents 25 kHz Wire Diameter no. d, mils Skin depth S, mils d/S 50 kHz R ac/ Rdc 100 kHz 200 kHz Skin depth S, mils d/S R ac/ Rdc Skin depth S, mils d/S Rac/ Rdc Skin depth S, mils d/S Rac/ Rdc 12 81.6 17.9 4.56 1.45 12.7 6.43 1.55 8.97 9.10 2.55 6.34 12.87 3.50 14 64.7 17.9 3.61 1.30 12.7 5.08 1.54 8.97 7.21 2.00 6.34 10.21 2.90 16 51.3 17.9 2.87 1.10 12.7 4.04 1.25 8.97 5.72 1.70 6.34 8.09 2.30 18 40.7 17.9 2.27 1.05 12.7 3.20 1.15 8.97 4.54 1.40 6.34 6.42 1.85 20 32.3 17.9 1.80 1.00 12.7 2.54 1.05 8.97 3.60 1.25 6.34 5.09 1.54 22 25.6 17.9 1.43 1.00 12.7 2.02 1.00 8.97 2.85 1.10 6.34 4.04 1.30 24 20.3 17.9 1.13 1.00 12.7 1.60 1.00 8.97 2.26 1.04 6.34 3.20 1.15 26 16.1 17.9 0.90 1.00 12.7 1.27 1.00 8.97 1.79 1.00 6.34 2.54 1.05 28 12.7 17.9 0.71 1.00 12.7 1.00 1.00 8.97 1.42 1.00 6.34 2.00 1.00 30 10.1 17.9 0.56 1.00 12.7 0.80 1.00 8.97 1.13 1.00 6.34 1.59 1.00 32 8.1 17.9 0.45 1.00 12.7 0.84 1.00 8.97 0.90 1.00 6.34 1.28 1.00 34 6.4 17.9 0.36 1.00 12.7 0.50 1.00 8.97 0.71 1.00 6.34 1.01 1.00 Note: To completely avoid the skin effect, the maximum diameter allowed is 20.3 mils, which is equal to 0.5 mm. Doc ID 13127 Rev 5 11/36 Flyback stage design AN2495 For practical considerations, to better optimize the utilization of the transformer window, and comply with Equation 15 to Equation 18 and Table 2, it can be determined that: Equation 19 d s = 0.05 [ cm ]3inparallel The specifications of the transformer according to the above calculations are listed below. Application specifications Safety information - IEC EN60950 ● Vinmin = 250 V DC ● Vinmax = 850 V DC ● Poutmax = 80 W ● Vout = 24 V (power output 80 W) ● Ioutmax = 3.33 A ● Vaux = 15 V (to drive the IC < 1 W) ● Fswmin = 50 kHz (max. load, min. Vin) ● Vflyback = 250 V ● Ipeak(primary) = 1.6 A ● Irms(primary) = 0.65 A ● Ipeak(secondary) = 16 A ● Irms(secondary) = 6.5 A ● Lp (primary inductance) = 1.56 mH ● Np/Ns = 10 ● Np/Naux = 17 Wires and ferrite used 12/36 ● Np = 120 d = 0.28 mm ● Ns = 12 d = 0.5 mm 3 in parallel ● Naux = 7 d = 0.28 or smaller ● The core used is an ETD 34, N67 material from EPCOS or equivalent. ● Air gap = 1.8 mm Doc ID 13127 Rev 5 AN2495 4 Base driving circuit design Base driving circuit design In practical applications such as SMPS where the load is variable, the collector current is variable as well. As a consequence it is very important to provide a base current to the device which is related to the collector. In this way it is possible to avoid device oversaturation at low load and to optimize the performance in terms of power dissipation. The best and simplest way to do this is the proportional driving method provided by the current transformer in Figure 6. At the same time, it is very useful to provide a short pulse to the base to make the turn-on as fast as possible and to reduce the dynamic saturation phenomenon. The pulse is achieved by using the capacitor and the Zener diode in Figure 6. Figure 6. Proportional driving schematic and equivalent circuit Lp Dz Ic Ic Cb LTp IM Rb Ip Is LTp Ib The IC/IB ratio is fixed once the current transformer turn ratio has been chosen. From the ESBT STC04DE170 datasheet, and especially looking at the storage time characterization, it is clear that a turn ratio equal to 5 is a good value to ensure the right saturation of the ESBT at IC = 2 A, so that in the current transformer we can first fix: Equation 20 NP 1 ------- = --5 NS The core magnetic permeability of current transformer must be as high as possible to minimize the magnetization current IM (which is not transferred to the secondary side but only drives the core into saturation). On the contrary, a too high permeability core may lead the core into saturation even with a very small magnetization current. To avoid saturation, it is necessary to increase the number of primary turns and the size of the core as well. If a core with a very small magnetic permeability is chosen, it is possible to reduce the number of primary turns and the core size. If the permeability is too small, we may not have current on the secondary side because almost all the collector current becomes magnetization current. As a compromise, a ferrite material with a relative permeability in the range 45007000 is the best choice. Doc ID 13127 Rev 5 13/36 Base driving circuit design AN2495 After selecting the ferrite ring diameter, the minimum primary turns is determined to avoid core saturation from the preliminarily fixed turn ratio N with 0.2. By applying Faraday's law and imposing the maximum flux Bmax equal to Bsat/2: Equation 21 V 1 • T onmax ΔB dϕ V 1 = N TP • ------ ≅ N TP • A e • -------- ⇒N TP = 2 • -------------------------------ΔT dt A e • B sat where Bsat is the saturation flux of the core which depends on the magnetic permeability. During the conduction time, the junction base-emitter of the ESBT can be seen as a forward-biased diode. To complete the secondary side load loop, the voltage drop on both diode D and resistor RB must be added in series with the base of the ESBT. The equivalent secondary side voltage source is given by: Equation 22 V S = V BEon – V D – V RB ≅ 2.5V Since the magnetization inductance cannot be neglected, only IP, a fraction of the total collector current, is transferred to the secondary. As a result, the magnetization current has to be first as low as possible. Meanwhile, the value of the magnetization inductance must be taken into account for the proper calculation of transformer primary turns and turns ratio. The magnetization voltage drop, that is, the voltage at the primary of the current transformer, can now be easily calculated: Equation 23 N 1T 1 V 1 = V S • ---------- = 2.5 • --- = 0.5 ( V ) 5 N 2T The magnetization current will be: Equation 24 V 1 T ONmax I Mmax = --------------------------L TP The number of primary turns should be increased if IMmax is relatively high. The core must have a window area large enough to hold all primary and secondary windings. Otherwise it is necessary to choose a bigger core size. Once both core material and size are fixed, the turn ratio must be adjusted to get the desiderated IC/IB ratio according to Equation 25 below: Equation 25 IP I C max – I Mmax N eff = ----- = -----------------------------------IB IC ---5 where IMmax is the maximum magnetization current. 14/36 Doc ID 13127 Rev 5 AN2495 Base driving circuit design The insulation between primary and secondary should be considered since the voltage on the primary side during the off time can surpass 1500 V. The next step is to select the Zener diode, the capacitor Cb, and the resistor Rb. The turn-on performance of the ESBT is related to the initial base peak current and its duration tpeak, which is given approximately by Equation 26: Equation 26 tpeak = 3R b C b A suitable value for Rb is 0.56 Ω. It can eliminate the ringing on the base current after the peak, and at the same time, it generates negligible power dissipation. The value tpeak can be determined once the minimum ON time is set based on the operating frequency. Bear in mind that in practical applications, it should never be lower than 200 ns. The value of Cb can be counted since the values of tpeak and Rb are known. Ipeak must be limited to avoid extra saturation of the device. The Zener diode Dz controls this and clamps the voltage across the small capacitor Cb. The Zener diode must be chosen according to the following empirical formulas and inside the range of VZmin and VZmax: Equation 27 V Zmax = 2 ( I peak R b + 1 ) V Zmin = 2 ( I peak R b ) The base peak current is higher with higher clamp voltage (Dz) or smaller capacitance (Cb), which in turn will lead to shorter duration of the peak time. The higher and longer the base peak current is, the lower the power dissipation during turnon. The designer must limit the Ib peak both in terms of amplitude and time duration. Otherwise, at low load a very high saturation level may result. If the device is oversaturated, the storage time is too long with higher power dissipation during turn-off. Moreover, a long storage time can also lead to output oscillation, especially at high input voltage. To overcome these problems, it is recommended to set the peak duration to 1/3 the minimum duty cycle. Following all the equations mentioned in this section applied to the present work gives: Equation 28 V 1 • T onmax N TP = 2 • -------------------------------- ≈ 2 A e • B sat where Ae is the magnetic area, considering a ring core with 12.5 mm diameter, and the saturation field Bsat is 400 mT. From the first approximated assumption NS should be 10. From bench verification it is very simple to verify that the turn ratio to get the best trade-off between conduction and turn-off losses is 6. Of course, this verification and final decision has been taken after setting all the other components in the driving network and exactly: Equation 29 t peak = 3R b C c = 400ns = C b = 238nF = C b = 220nF (closet commercial value) Finally, the Zener diode has been set to 3 V. Doc ID 13127 Rev 5 15/36 Output circuit design 5 AN2495 Output circuit design To choose the output capacitor, the series resistance of the electrolytic capacitor must be defined. It is well known that the main cause of the output ripple is the series resistance of the electrolytic capacitor, known as ESR, while the capacitive ripple is absolutely negligible. Therefore, with a known secondary side peak current of 16 A and imposing a resistive ripple equal to 2% (0.48 V), we have: Equation 30 V ripple 0.48 ESR < ----------------- = ----------- = 0.03Ω 16 I SP Using very low ESR output capacitances, from the catalogue we get the equation ESR*C = 32e-6s from which: Equation 31 –6 32 • 10 C out > ------------------------ = 1066μF ESR To obtain some margin and better thermal spread, the final choice is to use two 680 µF capacitors in parallel. From Kirchoff’s voltage law we can calculate the maximum voltage stress on the output diode: Equation 32 NS V of f – diode = V out + ------- • V inmax = 109V NP Finally, adding a 10% margin, the STPS20120D has been selected. 16/36 Doc ID 13127 Rev 5 AN2495 6 Startup network design Startup network design To allow the circuit to start as soon as the line voltage is applied, it is necessary to precharge both C5 and C8 capacitances. A resistor connected to the DC bus directly makes the pre-charge of C5 electrolytic capacitance. The circuit must start at a minimum DC input voltage of 250 V. The current required by the L6565 driver during the startup time determines the (R 1+ R2+ R3+ R4) value. Considering that the L6565 driver needs a 0.07 mA maximum startup current, we obtain: Equation 33 V inmin 250V ( R 1 + R 2 + R 3 + R 4 ) < ---------------- = --------------------- ≅ 3.6MΩ 0.07mA I SU Startup resistance must be lower than 3.6 MΩ to reach the best trade-off between power dissipation and time-to-start. As a consequence, before choosing the startup resistor, we must determine the C5 capacitance value, which is set according to another requirement. C5 must be able to supply the L6565 driver until the steady state behavior of the converter is established. The time from bench verification is 20 ms maximum. Given a L6565 minimum hysteresis-voltage (difference between startup threshold and undervoltage threshold) of 3.7 V, the voltage across C5 must decrease less than 3.7 V during the startup period. From the L6565 datasheet we know that maximum quiescent current after turn-on is 3.5 mA, so C5 must be chosen such that: Equation 34 I Q • Δt 3.5mA • 20ms ΔV = ----------------- < 3.7V ⇒C 5 > --------------------------------------- ≅ 19μF 3.7V C5 C5 = 33 µF is a good choice to guarantee a good margin. Finally, we can set the startup resistance value to reduce time-to-start and simultaneously optimize standby power dissipation. The L6565 has a maximum startup threshold of 14.5 V, therefore the maximum time-to-start is approximately: Equation 35 C 5 • 14.5V Time - to - start = ------------------------------------------------------------------------- ≤2 sec ⇒( R 1 + R 2 + R 3 + R 4 ) ≤808kΩ V inmin ⎛ ---------------------------------------------------- ⎞ – I ⎝ ( R 1 + R 2 + R 3 + R 4 ) ⎠ SU A good choice is to put in series four 200 kΩ resistors (R1 = R2 = R3 = R4 = 200 kΩ), which dissipate less than 1 W of standby power. The pre-charge of C8 base capacitance is carries out by connecting it to the OUT pin of the L6565 through a diode in series with a 2.2 kΩ resistor. Doc ID 13127 Rev 5 17/36 Frequency response and loop compensation 7 AN2495 Frequency response and loop compensation The transfer function in the complex frequency domain of the discontinuous current mode (DCM) flyback converter with L6565 driver is given by: Equation 36 L p D max ⎛ ⎞ ( 1 + s • C out • ESR ) ⎜ 1 – s • ------------------------------------------------⎟ 2 2 ⎝ n R out ( 1 – D max ) ⎠ V out ( s ) n • R out • ( 1 – D max ) G 1 ( s ) = ----------------------- = -------------------------------------------------------- • --------------------------------------------------------------------------------------------------------------------------------C out R out V comp ( s ) 2 • R S • ( 1 + D max ) 1 + s • ----------------------1 + D max The parameters and values are listed in Table 3. Table 3. Transfer function main parameters Parameter Description Value n Primary/secondary turn-ratio 10 RS Sensing resistor 0.8 Ω Dmax Maximum duty-cycle 0.5 ESR Electrolytic series resistance 16 mΩ Rout = Vout/Iout Output load 7.2 Ω Cout Output capacitance 2 mF Lp Primary inductance 1.56 mH It is worth noting that the transfer function has one pole and one zero on the left half plane and an additional zero on the right half plane. The RHP zero is very difficult, if not impossible, to compensate and therefore must be kept well beyond the closed-loop bandwidth. As a result, the transient response of such a system will not be extremely fast. Poles and zeros are given in Equation 37 and Equation 38: Equation 37 5 3 f p = 25Hz ;f Z1 = 3.5 • 10 Hz ;fZ2 = 5 • 10 Hz A good line and load regulation implies a high DC gain, thus the open loop gain should have a pole at the origin. Normally in this case we need a feedback network like the one in Figure 7. 18/36 Doc ID 13127 Rev 5 AN2495 Frequency response and loop compensation Figure 7. Converter feedback network .OTNEEDED INTHE,! 6OUT 6&" )& , ,$ ,! 2" 2( #/-0 ##/-0 6#/-0 2#/-0 6+ #& )#  2& 4, 2,  M! )# !- Its transfer function, which comprises a pole at the origin and a zero-pole pair, is given by: Equation 38 v comp ( s ) CTR max • R C OMP 1 1 + s ( R H + R F )C F G 2 ( s ) = ----------------------- = ------------------------------------------------ • --- • -------------------------------------------------s 1 + sR COMP C comp V out ( s ) R BR H CF The task of the control loop design is then to determine the transfer function G2(s) to ensure that the resulting closed-loop system is stable and performs well in terms of dynamic response, and line and load regulation. It is well known that the characteristics of the closedloop system can be inferred from its open loop transfer function properties, that is G(s) = G1(s) · G2(s). Frequency response requirements are summarized below: 1. Optimum dynamic performance requires a large gain bandwidth, that is the open loop cross-over frequency fC to be typically chosen equal to fsw/5 (fc = 10 kHz). 2. Phase margin ϕm comprised between 45° and 90° is used as a design guideline. This ensures fast transient response with very little ringing. Sometimes this is not enough and so phase shift should be lower than 180° at any frequency below fC, because a phase shift over 180° would result in a conditionally stable system. 3. Good load and line regulation implies a high DC gain (this requirement is ensured by the feedback network, whose transfer function has a pole at the origin). First choose a typical value for RL = R22 = 2.7 kΩ. Doc ID 13127 Rev 5 19/36 Frequency response and loop compensation AN2495 From the L6565 datasheet we know that Icomp = 5 mA (source current) and Rcomp = 15 kΩ. and can obtain: Equation 39 V out – ( V ref – V diode ) 24V – 3.5V R B = R 24 < ------------------------------------------------------- = ----------------------------- = 4.1kΩ 5mA Icomp R24 = 1.5 kΩ is a good choice. It is good practice to put a 3.3 kΩ resistor (R23 = 3.3 kΩ) in parallel to the photodiode. The resistive partition must be set with high precision according to the following equation: Equation 40 V out – V ref R high = R 22 • --------------------------- = 23.2kΩ V ref There is no next close commercial value so it is a good idea to put two 47 kΩ resistors (R19 = R20 = 47 kΩ) in series. Now C11 (Ccomp), C 13 (CF) and R 21 (RF) must be set in order to satisfy frequency response requirements. A good choice is to set the pole of G2(s) so as to cancel the low frequency zero of G1(s): Equation 41 1 ----------------------------------------------------- = 5kHz ⇒C 11 = C comp ≅ 2.12nF 2π • R comp • C comp The next close commercial value for C11 = 2.2 nF has been chosen. Similarly C13 and R21 have been determined by setting the corresponding zero close to the pole of G1(s) and imposing the open loop gain to cross the 0 dB axis only once at f = fc = 10 kHz: Equation 42 1 ⎧ ---------------------------------------------------- = 400Hz ⇒C 13 = 10nF ⎪ 2π • ( R + R ) • C H F F ⎨ ⎪ G ( jω) = 1 ⇒R 21 ≅ 15k –4 ω = 2π • 10 rad/sec ⎩ In such a way we ideally get a phase margin of 90 degrees and an adequate closed-loop bandwidth. 20/36 Doc ID 13127 Rev 5 AN2495 Frequency response and loop compensation Figure 8 shows Bode plots of the stabilized open loop transfer function. Figure 8. Stabilized open loop transfer function G(s) = G1(s) · G2(s) (Bode plots) As expected, all requirements have been satisfied by properly choosing the feedback network. Gain bandwidth is quite large, phase margin is around 90°, and system stability margin is improved. Doc ID 13127 Rev 5 21/36 Efficiency, waveforms and experimental results 8 AN2495 Efficiency, waveforms and experimental results Overall efficiency variation versus output power is illustrated in Figure 9 for two different values of input voltage. Figure 9. Overall efficiency versus output power for two different values of input voltage It is worth noting that with low input voltage (red curve), total efficiency is over 80%, and at medium and high load working conditions, reaching almost 85%. Efficiency decreases with input voltage. However, it is above 75% at loads higher than 30% even with maximum input voltage. Theoretical assumptions made so far have been validated with the use of a demonstration board. A complete description of this board has been carried out and the most meaningful waveforms in any working condition are shown in Figure 10 through Figure 15. Figure 10, Figure 11 and Figure 12 show the prototype steady state behavior, by indicating the gate voltage (blue waveform), the base current (violet waveform) and the collector voltage (sky blue waveform) at maximum load for different input voltages. 22/36 Doc ID 13127 Rev 5 AN2495 Efficiency, waveforms and experimental results Figure 10. Minimum input voltage-maximum load (250 V - 80 W) in steady state Figure 11. Medium input voltage-maximum load (500 V - 80 W) in steady state Doc ID 13127 Rev 5 23/36 Efficiency, waveforms and experimental results AN2495 Figure 12. Maximum input voltage-maximum load (850 V - 80 W) in steady state Waveforms in Figure 13, Figure 14, and Figure 15 describe the function of the converter at both low and high load conditions with the same input rectified voltage. Figure 13. Very low load condition (750 V - 5 W) Figure 14. Low load condition (750 V - 24 W) 24/36 Doc ID 13127 Rev 5 AN2495 Efficiency, waveforms and experimental results Figure 15. High load condition (750 V - 80 W) The waveform in Figure 16 illustrates the function of the proportional base driving network. In this graph, collector current is the violet line, while the base current line is light green. Figure 16. Proportional base driving circuit relevant waveform Doc ID 13127 Rev 5 25/36 Board modifications 9 AN2495 Board modifications This paragraph has been added following the release of more recent versions of the board STEVAL-ISA019V2 and STEVAL-ISA019V3. For the design procedure and rules, all the preceding paragraphs remain valid. Working conditions have not been changed. The new version was released to take advantage of the size reduction of the SMD components and to insert a new transformer with better coupling between primary inductance and auxiliary winding. The new transformer has been provided in accordance with the application requirements by EGSTON System Electronics Eggenburg GmbH. Moreover, the J2 connector (voltage doubler) has been removed from the board and an NTC resistor 10R (EPCOS B57237S100M) was added in series with the input line to suppress overcurrent peaks during the charge of the bulk capacitor. The complete solution is shown in Figure 17. Figure 17. STEVAL-ISA019V3 In Figure 18 the complete schematic of the STEVAL-ISA019V3 is provided. 26/36 Doc ID 13127 Rev 5 Doc ID 13127 Rev 5   6!#   * $ . $ . & 4! .4# $ . $ . N& # 6## # N&    2  7 2  2 2 #3 #/-0     $ . ).6  $   .P P& # N& # 2  3403 .AUX  6&& P&  #  5 ,. 1 34#)%(6  TURNS #  N& /54 '.$ 2  2  7 2 4    6 6## # 2 6## 2 6 $ $ $ 344( 344( $ # N&K 6   344( TURNS  2B 7 2 7 :#$ 2 2 # # 2  4   $    # 2 6  # N& 2 6 4,  5  2  3403$ #  0# )3/    .S    2   6$# !- 2 2    * AN2495 Board modifications Figure 18. STEVAL-ISA019V3 schematic diagram The specifications of the transformer provided by EGSTON System Electronics Eggenburg GmbH are shown in Figure 19. 27/36 Board modifications AN2495 Figure 19. Power transformer EGSTON 45371 The STEVAL-ISA019V2 printed circuit board is shown in Figure 20, Figure 21 and Figure 22. 28/36 Doc ID 13127 Rev 5 AN2495 Board modifications Figure 20. Silk screen (top side) Doc ID 13127 Rev 5 29/36 Board modifications AN2495 Figure 21. Silk screen (bottom side) 30/36 Doc ID 13127 Rev 5 AN2495 Board modifications Figure 22. Copper tracks Doc ID 13127 Rev 5 31/36 Board modifications AN2495 Table 4. Reference Bill of material Value / generic part number C1, C2 220 μF/450 V Electrolytic capacitor, 450 V, snap-in, 25*45 C3, C4 1000 μF/35 V Electrolytic capacitor, 35 V, 105°C, 12.5*25, low ESR C5 47 μF/35 V Electrolytic capacitor, 35 V, 105 °C, 5*11 C6 100 nF SMD ceramic capacitor CERCAP X7R/50V - 1206 C12 1 nF SMD ceramic capacitor CERCAP X7R/50V - 0805 C9 470 pF SMD ceramic capacitor CERCAP NPO/50V - 0805 C10 10 pF SMD ceramic capacitor CERCAP NPO/50V - 0805 C11 2.2 nF SMD ceramic capacitor CERCAP X7R/50V - 0805 C13 10 nF SMD ceramic capacitor CERCAP X7R/50V - 0805 C7 6.8 nF; 1600 VDC B32653A1682000; polypropylene film pulse capacitor, 1600 VDC, 7.5*16*26.5; 22.5 C8 150 nF SMD ceramic capacitor CERCAP X7R/50V - 1206 D11 LL4148 SMD universal diode D9 BZV55C3.0V Zener diode SMD - SOD80, 3.0 V Manufacturer EPCOS B43504-A5227-M EPCOS B32653A1682K D7, D8, STTH108A D10 SMD diode, high voltage ultrafast, 800 V, 1 A, SMA STMicroelectronics D6 STPS1150A SMD diode, power Schottky, 150 V, 1 A, SMA ST D5 STPS20120D SMD diode, power Schottky, 120 V, 20 A, TO220AB ST D1, D2, 1N4007 D3, D4 HV diode, 1000 V, 1A, DO-41 F1 Fuseholder vertical montage, SI-HA#122100 T1A F1 32/36 Package / class SCHURTER Fuse 1 A slow, 250 VAC het1, het2 8437/38/STB Heatsink, 8437/38/STB pin 2.2 mm, Rthjc = 11.5 °C/W J1 ARK700I/2 Connector ARK700I/2, RM = 5.08 mm J3 ARK500/2 Connector ARK500/2, RM = 5 mm KDI6M3X08 Distance column M3, 8 mm clip 00002952 Clip for heatsink 8437 Q1 STC04IE170HP 4 A, 1700 V ESBT switch, TO-247 4 leads, isolated ST R2, R3 200 kΩ Resistor, size 0204, metal film, 250 V, 0.4 W, 1% R12 10 Ω SMD standard film resistor - 1206 - 1% R6, R7 39 kΩ Resistor, size 0414, metal film, 500 V, 2 W, 5% R9, R10 1.1 MΩ SMD standard film resistor - 1206 - 1% Doc ID 13127 Rev 5 AN2495 Board modifications Table 4. Reference Bill of material (continued) Value / generic part number Package / class Manufacturer R18 10 kΩ SMD standard film resistor - 1206 - 1% R11 1Ω SMD standard film resistor - 1206 - 1% R11b 0Ω SMD standard film resistor - 0805 - 1% R13 1 kΩ SMD standard film resistor - 0805 - 1% R14 56 kΩ SMD standard film resistor - 0805 - 1% R15 1 kΩ SMD standard film resistor - 0805 - 1% R16, R17 1.6 Ω Resistor, size 0207, metal film, 250 V, 0.6 W, 1% R24 1.5 kΩ SMD standard film resistor - 0805 - 1% R23 3.3 kΩ SMD standard film resistor - 0805 - 1% R19, R20 47 kΩ SMD standard film resistor - 0805 - 1% R21 15 kΩ SMD standard film resistor - 0805 - 1% R22 2.7 kΩ SMD standard film resistor - 0805 - 1% R5 2.2 Ω Resistor, size 0207, metal film, 250 V, 0.6 W, 1% R8 1.1 MΩ Resistor, size 0207, metal film, 250 V, 0.6 W, 1% R26 1.2 kΩ Resistor, size 0207, metal film, 250 V, 0.6 W, 5% R1, R4 180 kΩ Resistor, size 0204, metal film, 250 V, 0.4 W, 1% T1 45371 EGSTON power transformer EGSTON 45371 T2 46836 Current transformer, toroid 12.5 mm, 46836 EGSTON 46836 U1 L6565N STMicroelectronics, PWM SMPS controller, DIP-8 ST ISO1 PC817B Optocoupler, SHARP, DIP-4 U4 TL431AID Voltage reference, 2.5 V, 1%, TO-92, -40...105 °C ST NTC1 10 Ω NTC resistor 10 Ω; 16 mm EPCOS B57237S 100M Doc ID 13127 Rev 5 33/36 References 10 34/36 AN2495 References ● STMicroelectronics application note AN1889 “ESBT STC03DE170HV in 3-phase auxiliary power supply” ● STMicroelectronics application note AN1262 “OFFLINE FLYBACK CONVERTERS DESIGN METHODOLOGY WITH THE L6590 FAMILY” ● STMicroelectronics application note AN2131 “HIGH POWER 3-PHASE AUXILIARY POWER SUPPLY DESIGN BASED ON L5991 AND ESBT STC08DE150” ● STMicroelectronics L6565 datasheet “QUASI-RESONANT SMPS CONTROLLER” ● STMicroelectronics STC04IE170HV datasheet “Monolithic emitter switched bipolar transistor ESBT® 1700 V - 4 A - 0.17 Ω“ ● “Switching Power Supply Design”, McGraw-Hill, Inc. Doc ID 13127 Rev 5 AN2495 11 Revision history Revision history Table 5. Document revision history Date Revision 28-Mar-2007 1 First issue 10-Apr-2007 2 Equation 5 and Equation 15 modified 02-Jul-2007 3 ESBT part number has been updated 20-May-2009 4 – Section 9: Board modifications added – Minor text changes throughout the document 5 Document reformatted, updated title, Section 1, Section 3.1.2, Section 3.1.3 (modified and added Application specifications and Wires and ferrite used), Section 8, Section 9, (Figure 17 to Figure 22, removed Figure 6 and 8 and Section “PCB layout and list of material”, Section “Bill of material” replaced by Table 4), minor text changes and corrected typo throughout the document. 19-Apr-2011 Changes Doc ID 13127 Rev 5 35/36 AN2495 Please Read Carefully: Information in this document is provided solely in connection with ST products. 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