STFI10LN80K5

STFI10LN80K5 N-channel 800 V, 0.55 Ω typ., 8 A MDmesh™ K5 Power MOSFET in a I²PAKFP package Datasheet - production data Features  12 3      2 I PAKFP (TO-281) Order code VDS RDS(on) max. ID STFI10LN80K5 800 V 0.63 Ω 8A Fully insulated and low profile package with increased creepage path from pin to heatsink plate Industry’s RDS(on) x area Industry’s best FoM (figure of merit) Ultra-low gate charge 100% avalanche tested Zener-protected Figure 1: Internal schematic diagram Applications D(2)  Switching applications Description This very high voltage N-channel Power MOSFET is designed using MDmesh™ K5 technology based on an innovative proprietary vertical structure. The result is a dramatic reduction in on-resistance and ultra-low gate charge for applications requiring superior power density and high efficiency. G(1) S(3) AM15572v1_no_tab Table 1: Device summary Order code Marking Package Packing STFI10LN80K5 10LN80K5 I²PAKFP Tube February 2016 DocID028981 Rev 1 This is information on a product in full production. 1/13 www.st.com Contents STFI10LN80K5 Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ..................................................................................... 9 4 Package information ..................................................................... 10 4.1 5 2/13 I2PAKFP (TO-281) package information ......................................... 10 Revision history ............................................................................ 12 DocID028981 Rev 1 STFI10LN80K5 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol VGS Parameter Value Unit ± 30 V ID Gate-source voltage Drain current (continuous) at TC = 25 °C 8 A (1) ID Drain current (continuous) at TC = 100 °C 5 A (2) ID Drain current pulsed 32 A PTOT Total dissipation at TC = 25 °C 20 W VISO Insulation withstand voltage (RMS) from all three leads to external heat sink (t=1s; TC=25°C) 2500 V (1) dv/dt (3) Peak diode recovery voltage slope 4.5 dv/dt (4) MOSFET dv/dt ruggedness 50 Tj Tstg Operating junction temperature range V/ns - 55 to 150 Storage temperature range °C Notes: (1) (2) Limited by maximum junction temperature. Pulse width limited by safe operating area (3) ISD≤ 8 A, di/dt≤100 A/μs; VDS peak ≤ V(BR)DSS (4) VDS ≤ 640 V Table 3: Thermal data Symbol Parameter Value Unit Rthj-case Thermal resistance junction-case 6.25 °C/W Rthj-amb Thermal resistance junction-ambient 62.5 °C/W Value Unit Table 4: Avalanche characteristics Symbol Parameter IAR Avalanche current, repetitive or not repetitive (pulse width limited by Tjmax) 2.7 A EAS Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) 240 mJ DocID028981 Rev 1 3/13 Electrical characteristics 2 STFI10LN80K5 Electrical characteristics TC = 25 °C unless otherwise specified Table 5: On/off-state Symbol V(BR)DSS Parameter Drain-source breakdown voltage Test conditions Min. VGS = 0 V, ID = 1 mA 800 Typ. Max. Unit V VGS = 0 V, VDS = 800 V 1 µA IDSS Zero gate voltage drain current VGS = 0 V, VDS = 800 V (1) TC = 125 °C 50 µA IGSS Gate body leakage current VDS = 0 V, VGS = ±20 V ±10 µA VGS(th) Gate threshold voltage VDS = VGS, ID = 100 µA 4 5 V RDS(on) Static drain-source on-resistance VGS = 10 V, ID = 4 A 0.55 0.63 Ω Min. Typ. Max. Unit - 427 - pF - 43 - pF - 0.25 - pF - 72 - pF 27 - pF 3 Notes: (1) Defined by design, not subject to production test. Table 6: Dynamic Symbol Ciss Parameter Input capacitance VDS = 100 V, f = 1 MHz, VGS = 0 V Coss Output capacitance Crss Reverse transfer capacitance (1) Co(tr) (2) Co(er) Test conditions Equivalent capacitance time related Equivalent capacitance energy related VDS = 0 to 640 V, VGS = 0 V Rg Intrinsic gate resistance f = 1 MHz , ID= 0 A - 7 - Ω Qg Total gate charge - 15 - nC Qgs Gate-source charge - 4.2 - nC Qgd Gate-drain charge VDD = 640 V, ID = 8 A VGS= 10 V (see Figure 16: "Test circuit for gate charge behavior") - 9 - nC Notes: (1) Time related is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS (2) Energy related is defined as a constant equivalent capacitance giving the same stored energy as C oss when VDS increases from 0 to 80% VDSS 4/13 DocID028981 Rev 1 STFI10LN80K5 Electrical characteristics Table 7: Switching times Symbol td(on) tr Parameter Turn-on delay time Rise time td(off) tf Turn-off delay time Fall time Test conditions Min. Typ. Max. Unit VDD= 400 V, ID = 4 A, RG = 4.7 Ω VGS = 10 V (see Figure 15: "Test circuit for resistive load switching times" and Figure 20: "Switching time waveform") - 11.8 - ns - 10 - ns - 28 - ns - 13 - ns Min. Typ. Max. Unit Table 8: Source-drain diode Symbol ISD Parameter Test conditions Source-drain current - 8 A (1) Source-drain current (pulsed) - 32 A (2) ISDM VSD Forward on voltage ISD = 8 A, VGS = 0 V - trr Reverse recovery time - 350 ns Qrr Reverse recovery charge - 3.9 µC IRRM Reverse recovery current ISD = 8 A, di/dt = 100 A/µs, VDD = 60 V (see Figure 17: "Test circuit for inductive load switching and diode recovery times") - 22.5 A ISD = 8 A, di/dt = 100 A/µs, VDD = 60 V, Tj = 150 °C (see Figure 17: "Test circuit for inductive load switching and diode recovery times") - 505 ns - 5 µC - 20 A trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current 1.5 V Notes: (1) (2) Pulse width limited by safe operating area Pulsed: pulse duration = 300 µs, duty cycle 1.5% Table 9: Gate-source Zener diode Symbol V (BR)GSO Parameter Gate-source breakdown voltage Test conditions IGS= ± 1 mA, ID= 0 A Min Typ. Max Unit 30 - - V The built-in back-to-back Zener diodes are specifically designed to enhance the ESD performance of the device. The Zener voltage facilitates efficient and cost-effective device integrity protection,thus eliminating the need for additional external componentry. DocID028981 Rev 1 5/13 Electrical characteristics 2.2 STFI10LN80K5 Electrical characteristics (curves) Figure 2: Safe operating area Figure 3: Thermal impedance K GC20940_ZTH δ=0.5 0.1 δ=0.2 0.05 0.02 10 -1 0.01 Single pulse 10 -2 10 6/13 -3 10-4 10-3 10 -2 10 -1 10 0 tp(s) Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance DocID028981 Rev 1 STFI10LN80K5 Electrical characteristics Figure 8: Capacitance variations Figure 9: Normalized gate threshold voltage vs temperature Figure 10: Normalized on-resistance vs temperature Figure 11: Normalized V(BR)DSS vs temperature Figure 12: Output capacitance stored energy Figure 13: Source-drain diode forward characteristics DocID028981 Rev 1 7/13 Electrical characteristics STFI10LN80K5 Figure 14: Maximum avalanche energy vs starting TJ 8/13 DocID028981 Rev 1 STFI10LN80K5 3 Test circuits Test circuits Figure 15: Test circuit for resistive load switching times Figure 16: Test circuit for gate charge behavior Figure 17: Test circuit for inductive load switching and diode recovery times Figure 18: Unclamped inductive load test circuit Figure 19: Unclamped inductive waveform Figure 20: Switching time waveform DocID028981 Rev 1 9/13 Package information 4 STFI10LN80K5 Package information In order to meet environmental requirements, ST offers these devices in different grades of ® ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ® ECOPACK is an ST trademark. 4.1 I2PAKFP (TO-281) package information Figure 21: I²PAKFP (TO-281) package outline 8291506 Re v. C 10/13 DocID028981 Rev 1 STFI10LN80K5 Package information Table 10: I²PAKFP (TO-281) mechanical data mm Dim. Min. Typ. Max. A 4.40 4.60 B 2.50 2.70 D 2.50 2.75 D1 0.65 0.85 E 0.45 0.70 F 0.75 1.00 F1 1.20 G 4.95 5.20 H 10.00 10.40 L1 21.00 23.00 L2 13.20 14.10 L3 10.55 10.85 L4 2.70 3.20 L5 0.85 L6 7.50 DocID028981 Rev 1 1.25 7.60 7.70 11/13 Revision history 5 STFI10LN80K5 Revision history Table 11: Document revision history 12/13 Date Revision 10-Feb-2016 1 DocID028981 Rev 1 Changes First release. STFI10LN80K5 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2016 STMicroelectronics – All rights reserved DocID028981 Rev 1 13/13