STLD200N4F6AG

STLD200N4F6AG Automotive N-channel 40 V, 1.27 mΩ typ., 120 A STripFET™ F6 Power MOSFET in a PowerFLAT™ 5x6 dual side cooling Datasheet - preliminary data Features      Order code VDS RDS(on) max. ID STLD200N4F6AG 40 V 1.5 mΩ 120 A Designed for automotive applications Very low on-resistance Very low gate charge High avalanche ruggedness Low gate drive power loss Applications  Switching applications Figure 1: Internal schematic diagram D(5, 6, 7, 8) Description This device is an N-channel Power MOSFET developed using the STripFET™ F6 technology with a new trench gate structure. The resulting Power MOSFET exhibits very low RDS(on) in all packages. G(4) S(1, 2, 3) Table 1: Device summary Order code Marking Package Packaging STLD200N4F6AG 200 PowerFLAT™ 5x6 dual side cooling Tape and reel January 2016 DocID028892 Rev 1 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 1/12 www.st.com Contents STLD200N4F6AG Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ..................................................................................... 8 4 Package information ....................................................................... 9 4.1 5 2/12 PowerFLAT™ 5X6 dual side cooling package information ............... 9 Revision history ............................................................................ 11 DocID028892 Rev 1 STLD200N4F6AG 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage 40 V VGS Gate-source voltage ± 20 V ID(1)(2) Drain current (continuous) at TC = 25 °C 120 A ID(1)(2) Drain current (continuous) at TC = 100 °C 120 A IDM(2)(3) Drain current (pulsed) 480 A Total dissipation at TC = 25 °C 158 W - 55 to 175 °C PTOT (2) TJ Operating junction temperature range Tstg Storage temperature range Notes: (1)Limited (2)The by package. value is rated according to Rthj-case bottom side. (3)Pulse width limited by safe operating area. Table 3: Thermal data Symbol Rthj-c top side Rthj-c bottom side Rthj-pcb (1) Parameter Value Thermal resistance junction-case top side 2.8 Thermal resistance junction-case bottom side 0.95 Thermal resistance junction-pcb 31.3 Unit °C/W Notes: (1)When mounted on 1 inch² 2 Oz. Cu board, t ≤ 10 s Table 4: Avalanche characteristics Symbol Parameter Value Unit IAV Avalanche current, repetitive or not repetitive (pulse width limited by maximum junction temperature) 90 A EAS Single pulse avalanche energy (Tj = 25 °C, IC = IAV, VDD = 16 V) 400 mJ DocID028892 Rev 1 3/12 Electrical characteristics 2 STLD200N4F6AG Electrical characteristics (TC= 25 °C unless otherwise specified) Table 5: On/off states Symbol Parameter Test conditions V(BR)DSS Drain-source breakdown voltage IDSS Zero gate voltage Drain current IGSS Min. VGS = 0 V, ID = 1 mA Typ. Max. 40 Unit V VGS = 0 V, VDS = 16 V 1 µA VGS = 0 V, VDS = 16 V, Tj = 125 °C 10 µA Gate-body leakage current VDS = 0 V, VGS = ± 20 V ±100 nA VGS(th) Gate threshold voltage VDS = VGS, ID = 1 mA 4 V RDS(on) Static drain-source onresistance VGS = 10 V, ID = 75 A 1.27 1.50 VGS = 6.5 V, ID = 75 A 1.48 2.00 2 mΩ Table 6: Dynamic Symbol Parameter Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Qg Total gate charge Qgs Gate-source charge Qgd Gate-drain charge Test conditions VDS= 10 V, f = 1 MHz, VGS = 0 V VDD = 32 V, ID = 90 A, VGS = 10 V (see Figure 14: "Test circuit for gate charge behavior") Min. Typ. Max. Unit - 10700 - pF - 1530 - pF - 1100 - pF - 172 - nC - 56 - nC - 48 - nC Min. Typ. Max. Unit - 150 - ns - 440 - ns - 600 - ns - 410 - ns Table 7: Switching times Symbol td(on) tr td(off) tf 4/12 Parameter Turn-on delay time Rise time Turn-off-delay time Fall time Test conditions VDD = 20 V, ID = 90 A RG = 30 Ω, VGS = 10 V (see Figure 13: "Test circuit for resistive load switching times") DocID028892 Rev 1 STLD200N4F6AG Electrical characteristics Table 8: Source drain diode Symbol Parameter Test conditions ISD(1) Source-drain current ISDM(1)(2) Source-drain current (pulsed) VSD (3) Forward on voltage trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current Min. Typ. Max. Unit - 120 A - 480 A VGS = 0 V, ISD = 90 A - 1.2 V ISD = 90 A, di/dt = 100 A/µs, VDD = 20 V (see Figure 15: "Test circuit for inductive load switching and diode recovery times") - 40 ns - 53 nC - 2.5 A Notes: (1)Limited (2) by package. Pulse width is limited by safe operating area (3)Pulse test: pulse duration = 300 µs, duty cycle 1.5% DocID028892 Rev 1 5/12 Electrical characteristics 2.1 6/12 STLD200N4F6AG Electrical characteristics (curves) Figure 2: Safe operating area Figure 3: Thermal impedance Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance DocID028892 Rev 1 STLD200N4F6AG Electrical characteristics Figure 8: Capacitance variations Figure 9: Normalized gate threshold voltage vs temperature Figure 10: Normalized on-resistance vs temperature Figure 11: Normalized V(BR)DSS vs temperature Figure 12: Source-drain diode forward characteristics DocID028892 Rev 1 7/12 Test circuits 3 8/12 STLD200N4F6AG Test circuits Figure 13: Test circuit for resistive load switching times Figure 14: Test circuit for gate charge behavior Figure 15: Test circuit for inductive load switching and diode recovery times Figure 16: Unclamped inductive load test circuit Figure 17: Unclamped inductive waveform Figure 18: Switching time waveform DocID028892 Rev 1 STLD200N4F6AG 4 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 4.1 PowerFLAT™ 5X6 dual side cooling package information Figure 19: PowerFLAT™ 5x6 dual side cooling package outline Plated Area 8548760_1 DocID028892 Rev 1 9/12 Package information STLD200N4F6AG Table 9: PowerFLAT™ 5x6 dual side cooling mechanical data mm Dim. Min. Typ. Max. A 0.66 0.71 0.76 A1 0.60 b 0.33 0.43 0.53 c 0.15 0.203 0.30 D D1 5.00 BSC 4.06 D2 D3 0.75 4.21 4.36 2.40 BSC 2.80 E 3.30 3.80 6.00 BSC E1 3.525 3.675 3.825 E2 1.05 1.20 1.35 E3 E4 3.80 BSC 4.20 e 4.70 5.20 1.27 BSC I 0.15 L 0.15 0.25 0.35 L1 0.925 1.05 1.175 L2 0.45 0.575 0.70 ϑ 12° BSC ϑ1 7° BSC j 0.20 BSC Figure 20: PowerFLAT™ 5x6 dual side cooling recommended footprint (dimensions are in mm) 10/12 DocID028892 Rev 1 STLD200N4F6AG 5 Revision history Revision history Table 10: Document revision history Date Revision 19-Jan-2016 1 DocID028892 Rev 1 Changes First release. 11/12 STLD200N4F6AG IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2016 STMicroelectronics – All rights reserved 12/12 DocID028892 Rev 1