STM32F101VDT6

STM32F101xC STM32F101xD STM32F101xE High-density access line, ARM®-based 32-bit MCU with 256 KB to 512 MB Flash, 9 timers, 1 ADC and 10 communication interfaces Datasheet − production data Features • Core: ARM® 32-bit Cortex®-M3 CPU – 36 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance – Single-cycle multiplication and hardware division • Memories – 256 to 512 Kbytes of Flash memory – up to 48 Kbytes of SRAM – Flexible static memory controller with 4 Chip Select. Supports Compact Flash, SRAM, PSRAM, NOR and NAND memories – LCD parallel interface, 8080/6800 modes • Clock, reset and supply management – 2.0 to 3.6 V application supply and I/Os – POR, PDR, and programmable voltage detector (PVD) – 4-to-16 MHz crystal oscillator – Internal 8 MHz factory-trimmed RC – Internal 40 kHz RC with calibration capability – 32 kHz oscillator for RTC with calibration • Low power – Sleep, Stop and Standby modes – VBAT supply for RTC and backup registers • 1 x 12-bit, 1 µs A/D converters (up to 16 channels) – Conversion range: 0 to 3.6 V – Temperature sensor This is information on a product in full production. LQFP64 10 × 10 mm – 51/80/112 I/Os, all mappable on 16 external interrupt vectors and almost all 5 V-tolerant • Debug mode – Serial wire debug (SWD) & JTAG interfaces – Cortex-M3 Embedded Trace Macrocell™ • Up to 9 timers – Up to four 16-bit timers, each with up to 4 IC/OC/PWM or pulse counters – 2 × watchdog timers (Independent and Window) – SysTick timer: a 24-bit downcounter – 2 × 16-bit basic timers to drive the DAC • Up to 10 communication interfaces – Up to 2 x I2C interfaces (SMSTM32F101xC, STM32F101xD, STM32F101xE7816 interface, LIN, IrDA capability, modem control) – Up to 3 SPIs (18 Mbit/s) • CRC calculation unit, 96-bit unique ID Table 1. Device summary Reference • DMA – 12-channel DMA controller – Peripherals supported: timers, ADC, DAC, SPIs, I2Cs and USARTs May 2015 LQFP100 14 × 14 mm • ECOPACK® packages • 2 × 12-bit D/A converters • Up to 112 fast I/O ports LQFP144 20 × 20 mm Part number STM32F101xC STM32F101RC STM32F101VC STM32F101ZC STM32F101xD STM32F101RD STM32F101VD STM32F101ZD STM32F101xE STM32F101RE STM32F101ZE STM32F101VE DocID14610 Rev 9 1/121 www.st.com Contents STM32F101xC, STM32F101xD, STM32F101xE Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 2/121 2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 2.2 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3.1 ARM® Cortex®-M3 core with embedded Flash and SRAM . . . . . . . . . . 14 2.3.2 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.3 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 15 2.3.4 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.5 FSMC (flexible static memory controller) . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.6 LCD parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.7 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 16 2.3.8 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . 16 2.3.9 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3.10 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3.11 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.12 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.13 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.14 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.15 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3.16 RTC (real-time clock) and backup registers . . . . . . . . . . . . . . . . . . . . . . 18 2.3.17 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3.18 I²C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.3.19 Universal synchronous/asynchronous receiver transmitters (USARTs) . 20 2.3.20 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.3.21 GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . 20 2.3.22 ADC (analog to digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.3.23 DAC (digital-to-analog converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.3.24 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.3.25 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.3.26 Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Pinouts and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 DocID14610 Rev 9 STM32F101xC, STM32F101xD, STM32F101xE Contents 4 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.1 6 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 40 5.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 41 5.3.4 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.3.6 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5.3.7 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5.3.8 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 5.3.9 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 5.3.10 FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 5.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 5.3.12 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 80 5.3.13 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 5.3.14 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 5.3.15 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 5.3.16 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 5.3.17 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 5.3.18 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 5.3.19 DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 5.3.20 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 6.1 LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 6.2 LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 DocID14610 Rev 9 3/121 4 Contents STM32F101xC, STM32F101xD, STM32F101xE 6.3 LQFP64 information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 6.4 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 6.4.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 6.4.2 Evaluating the maximum junction temperature for an application . . . . 114 7 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 4/121 DocID14610 Rev 9 STM32F101xC, STM32F101xD, STM32F101xE List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 STM32F101xC, STM32F101xD and STM32F101xE features and peripheral counts . . . . 11 STM32F101xx family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 STM32F101xC/STM32F101xD/STM32F101xE pin definitions. . . . . . . . . . . . . . . . . . . . . . 25 FSMC pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 41 Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Maximum current consumption in Run mode, code with data processing running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Maximum current consumption in Run mode, code with data processing running from RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Maximum current consumption in Sleep mode, code running from Flash or RAM. . . . . . . 45 Typical and maximum current consumptions in Stop and Standby modes . . . . . . . . . . . . 45 Typical current consumption in Run mode, code with data processing running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Typical current consumption in Sleep mode, code running from Flash or RAM . . . . . . . . . 49 Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Low-speed user external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 HSE 4-16 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . . 60 Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . 61 Asynchronous multiplexed NOR/PSRAM read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Asynchronous multiplexed NOR/PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . 69 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Switching characteristics for PC Card/CF read and write cycles . . . . . . . . . . . . . . . . . . . . 75 Switching characteristics for NAND Flash read and write cycles . . . . . . . . . . . . . . . . . . . . 78 EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 DocID14610 Rev 9 5/121 6 List of tables Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. 6/121 STM32F101xC, STM32F101xD, STM32F101xE I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 SCL frequency (fPCLK1= 36 MHz, VDD = VDD_I2C = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . 91 STM32F10xxx SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 RAIN max for fADC = 14 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 ADC accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 LQPF100 – 14 x 14 mm, 100-pin low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 LQFP64 – 10 x 10 mm, 64 pin low-profile quad flat package mechanical data . . . . . . . . 110 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 DocID14610 Rev 9 STM32F101xC, STM32F101xD, STM32F101xE List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. STM32F101xC, STM32F101xD and STM32F101xE access line block diagram . . . . . . . . 12 Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals enabled. . . . . . . . . . . . . . . . . . 44 Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals disabled . . . . . . . . . . . . . . . . . 44 Typical current consumption on VBAT with RTC on vs. temperature at different VBAT values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Typical current consumption in Stop mode with regulator in run mode versus temperature at different VDD values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Typical current consumption in Stop mode with regulator in low-power mode versus temperature at different VDD values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Typical current consumption in Standby mode versus temperature at different VDD values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . . 60 Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . . 61 Asynchronous multiplexed NOR/PSRAM read waveforms. . . . . . . . . . . . . . . . . . . . . . . . . 62 Asynchronous multiplexed NOR/PSRAM write waveforms . . . . . . . . . . . . . . . . . . . . . . . . 64 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . 69 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 PC Card/CompactFlash controller waveforms for common memory read access . . . . . . . 72 PC Card/CompactFlash controller waveforms for common memory write access . . . . . . . 72 PC Card/CompactFlash controller waveforms for attribute memory read access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 PC Card/CompactFlash controller waveforms for attribute memory write access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 PC Card/CompactFlash controller waveforms for I/O space read access . . . . . . . . . . . . . 74 PC Card/CompactFlash controller waveforms for I/O space write access . . . . . . . . . . . . . 75 NAND controller waveforms for read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . . 77 NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . . 78 Standard I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Standard I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 DocID14610 Rev 9 7/121 8 List of figures Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. 8/121 STM32F101xC, STM32F101xD, STM32F101xE 5 V tolerant I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 5 V tolerant I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 I2C bus AC waveforms and measurement circuit(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 SPI timing diagram - slave mode and CPHA=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 SPI timing diagram - slave mode and CPHA=1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . . 99 Power supply and reference decoupling (VREF+ connected to VDDA) . . . . . . . . . . . . . . 100 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package outline . . . . . . . . . . . . . . 103 LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 LQFP144 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 LQFP100 – 14 x 14 mm, 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . 107 LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 LQFP100 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 LQFP64 – 10 x 10 mm, 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . 110 Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 LQFP64 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 LQFP64 PD max vs. TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 DocID14610 Rev 9 STM32F101xC, STM32F101xD, STM32F101xE 1 Introduction Introduction This datasheet provides the ordering information and mechanical device characteristics of the STM32F101xC, STM32F101xD and STM32F101xE high-densityaccess line microcontrollers. For more details on the whole STMicroelectronics STM32F101xx family, please refer to Section 2.2: Full compatibility throughout the family. The high-density STM32F101xx datasheet should be read in conjunction with the STM32F10xxx reference manual. For information on programming, erasing and protection of the internal Flash memory please refer to the STM32F10xxx Flash programming manual. The reference and Flash programming manuals are both available from the STMicroelectronics website www.st.com. For information on the Cortex®-M3 core please refer to the Cortex®-M3 Technical Reference Manual, available from the www.arm.com website. DocID14610 Rev 9 9/121 120 Description 2 STM32F101xC, STM32F101xD, STM32F101xE Description The STM32F101xC, STM32F101xD and STM32F101xE access line family incorporates the high-performance ARM® Cortex®-M3 32-bit RISC core operating at a 36 MHz frequency, high-speed embedded memories (Flash memory up to 512 Kbytes and SRAM up to 48 Kbytes), and an extensive range of enhanced I/Os and peripherals connected to two APB buses. All devices offer one 12-bit ADC, four general-purpose 16-bit timers, as well as standard and advanced communication interfaces: up to two I2Cs, three SPIs and five USARTs. The STM32F101xx high-density access line family operates in the –40 to +85 °C temperature range, from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving mode allows the design of low-power applications. These features make the STM32F101xx high-density access line microcontroller family suitable for a wide range of applications such as medical and handheld equipment, PC peripherals and gaming, GPS platforms, industrial applications, PLC, printers, scanners alarm systems and video intercom. 10/121 DocID14610 Rev 9 STM32F101xC, STM32F101xD, STM32F101xE 2.1 Description Device overview The STM32F101xx high-density access line family offers devices in 3 different package types: from 64 pins to 144 pins. Depending on the device chosen, different sets of peripherals are included, the description below gives an overview of the complete range of peripherals proposed in this family. Figure 1 shows the general block diagram of the device family. Table 2. STM32F101xC, STM32F101xD and STM32F101xE features and peripheral counts Peripherals STM32F101Rx Flash memory in Kbytes 256 SRAM in Kbytes 32 FSMC Timers Comm 384 512 48 No STM32F101Vx 256 384 32 48 Yes Generalpurpose 4 Basic 2 SPI 3 2C 2 I USART 512 (1) STM32F101Zx 256 384 32 48 Yes 5 GPIOs 51 80 112 12-bit ADC Number of channels Yes 16 Yes 16 Yes 16 12-bit DAC Number of channels 1 2 CPU frequency 36 MHz Operating voltage Operating temperatures Package 512 2.0 to 3.6 V Ambient temperature: –40 to +85 °C (see Table 10) Junction temperature: –40 to +105 °C (see Table 10) LQFP64 LQFP100 LQFP144 1. For the LQFP100 package, only FSMC Bank1 and Bank2 are available. Bank1 can only support a multiplexed NOR/PSRAM memory using the NE1 Chip Select. Bank2 can only support a 16- or 8-bit NAND Flash memory using the NCE2 Chip Select. The interrupt line cannot be used since Port G is not available in this package. DocID14610 Rev 9 11/121 120 Description STM32F101xC, STM32F101xD, STM32F101xE Figure 1. STM32F101xC, STM32F101xD and STM32F101xE access line block diagram 6:-7$* 7UDFHWULJ 7UDFH FRQWUROOHU 3EXV )ODVK REO LQWHUIDFH 1-7567 -7', -7&.6:&/. -7066:',2 -7'2 DV$) #9 '' 73,8 ,EXV &RUWH[0 &38 9'' )ODVK.E\WHV ELW 'EXV )PD[ 0+] 6\VWHP 19,& 65$0 .% %XV 0DWUL[ 75$&(&/. 75$&('>@ DV$6 #9''$ 325 5HVHW 5&0+] *3'0$ 5&N+] FKDQQHOV 3// *3'0$ $>@ '>@ &/. 12( 1:( 1(>@ 1%/>@ 1:$,7 1/ DV$) FKDQQHOV 5HVHW &ORFN FRQWURO 6WDQGE\ LQWHUIDFH #9%$7 $+% $3% $3%)PD[ 0+] (;7,7 :.83 *3,2SRUW$ *3,2SRUW% 3&>@ *3,2SRUW& 3'>@ *3,2SRUW' 3(>@ *3,2SRUW( 3)>@ *3,2SRUW) 3*>@ *3,2SRUW* 026,0,626&. 166DV$) 63, 5;7;&76576 DV$) 86$57 ELW$'& 9 5()± 26&B,1 26&B287 9%$7 9WR9 26&B,1 26&B287 7$03(557& $/$506(&21'287 FKDQQHOVDV$) 7,0 FKDQQHOVDV$) 7,0 FKDQQHOVDV$) 7,0 86$57 86$57 FKDQQHOVDV$) 5;7;&76576  &.DV$) 5;7;&76576 &.DV$) 8$57 5;7;DV$) 8$57 5; 7;DV$) 63, ,) 1567 9''$ 966$ 7,0 63, 7HPSVHQVRU 9 5() #9 '' ;7$/26& 0+] 57& %DFNXS UHJ $:8 %DFNXSLQWHUIDF H 3%>@ $'&B,1>@ 39' ;7$/ N+] $3%)PD[ 0+] 3$>@ #9''$ 6XSSO\ VXSHUYLVLRQ 3253'5 966 ,:'* 3&/. 3&/. +&/. )&/. )60& $+% $3% $) ,QW 3RZHU 9ROWUHJ 9WR9 026,0,62 6&.166DV$)  026,0,62 6&.166DV$)  ,& 6&/6'$60%$DV$) ::'* ,& 6&/6'$60%$DV$) 7,0 ,) ELW'$& ,) ELW'$& 7,0 #9 ''$ '$&B287 DV$) '$&B287 DV$) #9''$ DLG 1. TA = –40 °C to +85 °C (junction temperature up to 105 °C). 2. AF = alternate function on I/O port pin. 12/121 DocID14610 Rev 9 STM32F101xC, STM32F101xD, STM32F101xE Description Figure 2. Clock tree -(Z (3)2# &,)4&#,+ TO&LASHPROGRAMMINGINTERFACE (3) &3-##,+ 0ERIPHERALCLOCK ENABLE -(ZMAX  0,,32#  37 0,,-5, (3) X XXX 0,, 393#,+ !(" 0RESCALER -(Z  MAX 0,,#,+ 0#,+ TO!0" PERIPHERALS 0ERIPHERAL#LOCK %NABLEBITS 4)- )F!0"PRESCALER X ELSEX #33 !0" 0RESCALER   -(Z (3%/3# /3#?/54 0#,+ -(ZMAX 0ERIPHERAL#LOCK %NABLEBITS PERIPHERALSTO!0"  !$# 0RESCALER   /3#?). TO4)-AND 4)-8#,+ 0ERIPHERAL#LOCK %NABLEBITS 0,,8402% /3#?). TO#ORTEX3YSTEMTIMER &#,+#ORTEX FREERUNNINGCLOCK -(ZMAX (3% /3#?/54 (#,+ TO!("BUSCORE MEMORYAND$-! #LOCK %NABLEBITS !0" 0RESCALER  TO&3-# ,3%/3# K(Z TO!$# !$##,+ TO24# ,3% 24##,+ 24#3%,;= ,3)2# K(Z TO)NDEPENDENT7ATCHDOG)7$' ,3) )7$'#,+ -AIN #LOCK/UTPUT  -#/ 0,,#,+ ,EGEND (3%(IGH3PEED%XTERNALCLOCKSIGNAL (3) (3)(IGH3PEED)NTERNALCLOCKSIGNAL (3% ,3),OW3PEED)NTERNALCLOCKSIGNAL 393#,+ ,3%,OW3PEED%XTERNALCLOCKSIGNAL -#/ AI 1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is 36 MHz. 2. To have an ADC conversion time of 1 µs, APB2 must be at 14 MHz or 28 MHz. DocID14610 Rev 9 13/121 120 Description 2.2 STM32F101xC, STM32F101xD, STM32F101xE Full compatibility throughout the family The STM32F101xx is a complete family whose members are fully pin-to-pin, software and feature compatible. In the reference manual, the STM32F101x4 and STM32F101x6 are identified as low-density devices, the STM32F101x8 and STM32F101xB are referred to as medium-density devices, and the STM32F101xC, STM32F101xD and STM32F101xE are referred to as high-density devices . Low- and high-density devices are an extension of the STM32F101x8/B medium-density devices, they are specified in the STM32F101x4/6 and STM32F101xC/D/E datasheets, respectively. Low-density devices feature lower Flash memory and RAM capacities, less timers and peripherals. High-density devices have higher Flash memory and RAM densities, and additional peripherals like FSMC and DAC, while remaining fully compatible with the other members of the family. The STM32F101x4, STM32F101x6, STM32F101xC, STM32F101xD and STM32F101xE are a drop-in replacement for the STM32F101x8/B devices, allowing the user to try different memory densities and providing a greater degree of freedom during the development cycle. Moreover, the STM32F101xx access line family is fully compatible with all existing STM32F103xx performance line and STM32F102xx USB access line devices. Table 3. STM32F101xx family Memory size Low-density devices Pinout 16 KB Flash 32 KB Flash(1) Medium-density devices 64 KB Flash 128 KB Flash 4 KB RAM 6 KB RAM 10 KB RAM 16 KB RAM 144 100 64 48 36 2 × USARTs 2 × 16-bit timers 1 × SPI, 1 × I2C 1 × ADC 3 × USARTs 3 × 16-bit timers 2 × SPIs, 2 × I2Cs, 1 × ADC High-density devices 256 KB Flash 384 KB Flash 512 KB Flash 32 KB RAM 48 KB RAM 48 KB RAM 5 × USARTs 4 × 16-bit timers. 2 × basic timers 3 × SPIs, 2 × I2Cs, 1 × ADC. 2 × DACs FSMC (100 and 144 pins) 1. For orderable part numbers that do not show the A internal code after the temperature range code (6), the reference datasheet for electrical characteristics is that of the STM32F101x8/B medium-density devices. 2.3 Overview 2.3.1 ARM® Cortex®-M3 core with embedded Flash and SRAM The ARM® Cortex®-M3 processor is the latest generation of ARM® processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while 14/121 DocID14610 Rev 9 STM32F101xC, STM32F101xD, STM32F101xE Description delivering outstanding computational performance and an advanced system response to interrupts. The ARM® Cortex®-M3 32-bit RISC processor features exceptional code-efficiency, delivering the high-performance expected from an ARM® core in the memory size usually associated with 8- and 16-bit devices. The STM32F101xC, STM32F101xD and STM32F101xE access line family having an embedded ARM® core, is therefore compatible with all ARM® tools and software. Figure 1 shows the general block diagram of the device family. 2.3.2 Embedded Flash memory 256 to 512 Kbytes of embedded Flash are available for storing programs and data. 2.3.3 CRC (cyclic redundancy check) calculation unit The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location. 2.3.4 Embedded SRAM Up to 48 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states. 2.3.5 FSMC (flexible static memory controller) The FSMC is embedded in the STM32F101xC, STM32F101xD and STM32F101xE access line family. It has four Chip Select outputs supporting the following modes: PC Card/Compact Flash, SRAM, PSRAM, NOR and NAND. Functionality overview: 2.3.6 • The three FSMC interrupt lines are ORed in order to be connected to the NVIC • Write FIFO • Code execution from external memory except for NAND Flash and PC Card • The targeted frequency is HCLK/2, so external access is at 18 MHz when HCLK is at 36 MHz LCD parallel interface The FSMC can be configured to interface seamlessly with most graphic LCD controllers. It supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to specific LCD interfaces. This LCD parallel interface capability makes it easy to build costeffective graphic applications using LCD modules with embedded controllers or highperformance solutions using external controllers with dedicated acceleration. DocID14610 Rev 9 15/121 120 Description 2.3.7 STM32F101xC, STM32F101xD, STM32F101xE Nested vectored interrupt controller (NVIC) The STM32F101xC, STM32F101xD and STM32F101xE access line embeds a nested vectored interrupt controller able to handle up to 60 maskable interrupt channels (not including the 16 interrupt lines of Cortex®-M3) and 16 priority levels. • Closely coupled NVIC gives low-latency interrupt processing • Interrupt entry vector table address passed directly to the core • Closely coupled NVIC core interface • Allows early processing of interrupts • Processing of late arriving higher priority interrupts • Support for tail-chaining • Processor state automatically saved • Interrupt entry restored on interrupt exit with no instruction overhead This hardware block provides flexible interrupt management features with minimal interrupt latency. 2.3.8 External interrupt/event controller (EXTI) The external interrupt/event controller consists of 19 edge detector lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 112 GPIOs can be connected to the 16 external interrupt lines. 2.3.9 Clocks and startup System clock selection is performed on startup, however the internal RC 8 MHz oscillator is selected as default CPU clock on reset. An external 4-16 MHz clock can be selected, in which case it is monitored for failure. If failure is detected, the system automatically switches back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full interrupt management of the PLL clock is available when necessary (for example with failure of an indirectly used external oscillator). Several prescalers are used to configure the AHB frequency, the high-speed APB (APB2) domain and the low-speed APB (APB1) domain. The maximum frequency of the AHB and APB domains is 36 MHz. See Figure 2 for details on the clock tree. 2.3.10 Boot modes At startup, boot pins are used to select one of three boot options: • Boot from user Flash: you have an option to boot from any of two memory banks. By default, boot from Flash memory bank 1 is selected. You can choose to boot from Flash memory bank 2 by setting a bit in the option bytes. • Boot from system memory • Boot from embedded SRAM The bootloader is located in system memory. It is used to reprogram the Flash memory by using USART1. 16/121 DocID14610 Rev 9 STM32F101xC, STM32F101xD, STM32F101xE 2.3.11 Description Power supply schemes • VDD = 2.0 to 3.6 V: external power supply for I/Os and the internal regulator. Provided externally through VDD pins. • VSSA, VDDA = 2.0 to 3.6 V: external analog power supplies for ADC, DAC, Reset blocks, RCs and PLL (minimum voltage to be applied to VDDA is 2.4 V when the ADC or DAC is used). VDDA and VSSA must be connected to VDD and VSS, respectively. • VBAT = 1.8 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present. For more details on how to connect power pins, refer to Figure 9: Power supply scheme. 2.3.12 Power supply supervisor The device has an integrated power-on reset (POR)/power-down reset (PDR) circuitry. It is always active, and ensures proper operation starting from/down to 2 V. The device remains in reset mode when VDD is below a specified threshold, VPOR/PDR, without the need for an external reset circuit. The device features an embedded programmable voltage detector (PVD) that monitors the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. Refer to Table 12: Embedded reset and power control block characteristics for the values of VPOR/PDR and VPVD. 2.3.13 Voltage regulator The regulator has three operation modes: main (MR), low power (LPR) and power down. • MR is used in the nominal regulation mode (Run) • LPR is used in the Stop modes. • Power down is used in Standby mode: the regulator output is in high impedance: the kernel circuitry is powered down, inducing zero consumption (but the contents of the registers and SRAM are lost) This regulator is always enabled after reset. It is disabled in Standby mode. 2.3.14 Low-power modes The STM32F101xC, STM32F101xD and STM32F101xE access line supports three lowpower modes to achieve the best compromise between low-power consumption, short startup time and available wakeup sources: • Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. • Stop mode Stop mode achieves the lowest power consumption while retaining the content of SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can also be put either in normal or in low-power mode. DocID14610 Rev 9 17/121 120 Description STM32F101xC, STM32F101xD, STM32F101xE The device can be woken up from Stop mode by any of the EXTI line. The EXTI line source can be one of the 16 external lines, the PVD output or the RTC alarm. • Standby mode The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.8 V domain is powered off. The PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering Standby mode, SRAM and register contents are lost except for registers in the Backup domain and Standby circuitry. The device exits Standby mode when an external reset (NRST pin), a IWDG reset, a rising edge on the WKUP pin, or an RTC alarm occurs. Note: The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop or Standby mode. 2.3.15 DMA The flexible 12-channel general-purpose DMAs (7 channels for DMA1 and 5 channels for DMA2) are able to manage memory-to-memory, peripheral-to-memory and memory-toperipheral transfers. The two DMA controllers support circular buffer management, removing the need for user code intervention when the controller reaches the end of the buffer. Each channel is connected to dedicated hardware DMA requests, with support for software trigger on each channel. Configuration is made by software and transfer sizes between source and destination are independent. DMA can be used with the main peripherals: SPI, I2C, USART, general-purpose and basic timers TIMx, DAC and ADC. 2.3.16 RTC (real-time clock) and backup registers The RTC and the backup registers are supplied through a switch that takes power either on VDD supply when present or through the VBAT pin. The backup registers are forty-two 16-bit registers used to store 84 bytes of user application data when VDD power is not present. They are not reset by a system or power reset, and they are not reset when the device wakes up from the Standby mode. The real-time clock provides a set of continuously running counters which can be used with suitable software to provide a clock calendar function, and provides an alarm interrupt and a periodic interrupt. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low-power RC oscillator or the high speed external clock divided by 128. The internal low-speed RC has a typical frequency of 40 kHz. The RTC can be calibrated using an external 512 Hz output to compensate for any natural quartz deviation. The RTC features a 32-bit programmable counter for long term measurement using the Compare register to generate an alarm. A 20-bit prescaler is used for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32.768 kHz. 2.3.17 Timers and watchdogs The high-density STM32F101xx access line devices include up to four general-purpose timers, two basic timers, two watchdog timers and a SysTick timer. Table 4 compares the features of the general-purpose and basic timers. 18/121 DocID14610 Rev 9 STM32F101xC, STM32F101xD, STM32F101xE Description Table 4. Timer feature comparison Timer Counter resolution Counter type Prescaler factor DMA request Capture/compare Complementary generation channels outputs TIM2, TIM3, TIM4, TIM5 16-bit Up, down, up/down Any integer between 1 and 65536 Yes 4 No TIM6, TIM7 16-bit Up Any integer between 1 and 65536 Yes 0 No General-purpose timers (TIMx) There are up to 4 synchronizable general-purpose timers (TIM2, TIM3, TIM4 and TIM5) embedded in the STM32F101xC, STM32F101xD and STM32F101xE access line devices. These timers are based on a 16-bit auto-reload up/down counter, a 16-bit prescaler and feature 4 independent channels each for input capture/output compare, PWM or one-pulse mode output. This gives up to 16 input captures / output compares / PWMs on the largest packages. The general-purpose timers can work together with the advanced-control timer via the Timer Link feature for synchronization or event chaining. Their counter can be frozen in debug mode. Any of the general-purpose timers can be used to generate PWM outputs. They all have independent DMA request generation. These timers are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 3 hall-effect sensors. Basic timers TIM6 and TIM7 These timers are mainly used for DAC trigger generation. They can also be used as a generic 16-bit time base. Independent watchdog The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 40 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. It is hardware or software configurable through the option bytes. The counter can be frozen in debug mode. Window watchdog The window watchdog is based on a 7-bit downcounter that can be set as free running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. DocID14610 Rev 9 19/121 120 Description STM32F101xC, STM32F101xD, STM32F101xE SysTick timer This timer is dedicated to real-time operating systems, but could also be used as a standard down counter. It features: 2.3.18 • A 24-bit down counter • Autoreload capability • Maskable system interrupt generation when the counter reaches 0. • Programmable clock source I²C bus Up to two I²C bus interfaces can operate in multi-master and slave modes. They support standard and fast modes. They support 7/10-bit addressing mode and 7-bit dual addressing mode (as slave). A hardware CRC generation/verification is embedded. They can be served by DMA and they support SMBus 2.0/PMBus. 2.3.19 Universal synchronous/asynchronous receiver transmitters (USARTs) The STM32F101xC, STM32F101xD and STM32F101xE access line embeds three universal synchronous/asynchronous receiver transmitters (USART1, USART2 and USART3) and two universal asynchronous receiver transmitters (UART4 and UART5). These five interfaces provide asynchronous communication, IrDA SIR ENDEC support, multiprocessor communication mode, single-wire half-duplex communication mode and have LIN Master/Slave capability. The five interfaces are able to communicate at speeds of up to 2.25 Mbit/s. USART1, USART2 and USART3 also provide hardware management of the CTS and RTS signals, Smart Card mode (ISO 7816 compliant) and SPI-like communication capability. All interfaces can be served by the DMA controller except for UART5. 2.3.20 Serial peripheral interface (SPI) Up to three SPIs are able to communicate up to 18 Mbits/s in slave and master modes in full-duplex and simplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic SD Card/MMC modes. All SPIs can be served by the DMA controller. 2.3.21 GPIOs (general-purpose inputs/outputs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high currentcapable. The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers. 20/121 DocID14610 Rev 9 STM32F101xC, STM32F101xD, STM32F101xE 2.3.22 Description ADC (analog to digital converter) A 12-bit analog-to-digital converter is embedded into STM32F101xC, STM32F101xD and STM32F101xE access line devices. It has up to 16 external channels, performing conversions in single-shot or scan modes. In scan mode, automatic conversion is performed on a selected group of analog inputs. The ADC can be served by the DMA controller. An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds. The events generated by the general-purpose timers (TIMx) can be internally connected to the ADC start trigger and injection trigger, respectively, to allow the application to synchronize A/D conversion and timers. 2.3.23 DAC (digital-to-analog converter) The two 12-bit buffered DAC channels can be used to convert two digital signals into two analog voltage signal outputs. The chosen design structure is composed of integrated resistor strings and an amplifier in inverting configuration. This dual digital Interface supports the following features: • two DAC converters: one for each output channel • 8-bit or 12-bit monotonic output • left or right data alignment in 12-bit mode • synchronized update capability • noise-wave generation • triangular-wave generation • dual DAC channel independent or simultaneous conversions • DMA capability for each channel • external triggers for conversion • input voltage reference VREF+ Seven DAC trigger inputs are used in the STM32F101xC, STM32F101xD and STM32F101xE access line family. The DAC channels are triggered through the timer update outputs that are also connected to different DMA channels. 2.3.24 Temperature sensor The temperature sensor has to generate a voltage that varies linearly with temperature. The conversion range is between 2 V < VDDA < 3.6 V. The temperature sensor is internally connected to the ADC_IN16 input channel which is used to convert the sensor output voltage into a digital value. 2.3.25 Serial wire JTAG debug port (SWJ-DP) The ARM® SWJ-DP Interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP. DocID14610 Rev 9 21/121 120 Description 2.3.26 STM32F101xC, STM32F101xD, STM32F101xE Embedded Trace Macrocell™ The ARM® Embedded Trace Macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the STM32F10xxx through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. The TPA is connected to a host computer using Ethernet, or any other high-speed channel. Real-time instruction and data flow activity can be recorded and then formatted for display on the host computer running debugger software. TPA hardware is commercially available from common development tool vendors. It operates with third party debugger software tools. 22/121 DocID14610 Rev 9 STM32F101xC, STM32F101xD, STM32F101xE 3 Pinouts and pin descriptions Pinouts and pin descriptions                                     6$$? 633? 0% 0% 0" 0" "//4 0" 0" 0" 0" 0" 0' 6$$? 633? 0' 0' 0' 0' 0' 0' 0$ 0$ 6$$? 633? 0$ 0$ 0$ 0$ 0$ 0$ 0# 0# 0# 0!  0!  Figure 3. LQFP144 pinout                                     ,1&0                                     6$$? 633? .# 0!  0!  0!  0!  0!  0!  0# 0# 0# 0# 6$$? 633? 0' 0' 0' 0' 0' 0' 0' 0$ 0$ 6$$? 633? 0$ 0$ 0$ 0$ 0$ 0$ 0" 0" 0" 0" 633? 6$$? 0& 0& 0& 0' 0' 0% 0% 0% 633? 6$$? 0% 0% 0% 0% 0% 0% 0" 0" 633? 6$$? 0!  633? 6$$? 0!  0!  0!  0!  0# 0# 0" 0" 0" 0& 0&                                     0% 0% 0% 0% 0% 6"!4 0# 4!-0%2 24# 0# /3#?). 0# /3#?/54 0& 0& 0& 0& 0& 0& 633? 6$$? 0& 0& 0& 0& 0& /3#?). /3#?/54 .234 0# 0# 0# 0# 633! 62%& 62%& 6$$! 0!  7+50 0!  0!  AI 1. The above figure shows the package top view. DocID14610 Rev 9 23/121 120 Pinouts and pin descriptions STM32F101xC, STM32F101xD, STM32F101xE                          6$$? 633? 0% 0% 0" 0" "//4 0" 0" 0" 0" 0" 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0# 0# 0# 0! 0! Figure 4. LQFP100 pinout                          ,1&0                          6$$? 633? .# 0! 0! 0! 0! 0! 0! 0# 0# 0# 0# 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0$ 0" 0" 0" 0" 0! 633? 6$$? 0! 0! 0! 0! 0# 0# 0" 0" 0" 0% 0% 0% 0% 0% 0% 0% 0% 0% 0" 0" 633? 6$$?                          0% 0% 0% 0% 0% 6"!4 0# 4!-0%2 24# 0# /3#?). 0# /3#?/54 633? 6$$? /3#?). /3#?/54 .234 0# 0# 0# 0# 633! 62%& 62%& 6$$! 0! 7+50 0! 0! AI 1. The above figure shows the package top view. 24/121 DocID14610 Rev 9 STM32F101xC, STM32F101xD, STM32F101xE Pinouts and pin descriptions sͺϯ s^^ͺϯ W ϵ W ϴ KK d Ϭ W ϳ W ϲ W ϱ W ϰ W ϯ WϮ WϭϮ Wϭϭ WϭϬ W ϭϱ W ϭϰ Figure 5. LQFP64 pinout ϲϰ ϲϯ ϲϮ ϲϭ ϲϬ ϱϵ ϱϴ ϱϳ ϱϲ ϱϱ ϱϰ ϱϯ ϱϮ ϱϭ ϱϬ ϰϵ ϰϴ ϭ ϰϳ Ϯ ϰϲ ϯ ϰϱ ϰ ϰϰ ϱ ϰϯ ϲ ϰϮ ϳ ϰϭ ϴ >Y&Wϲϰ ϰϬ ϵ ϯϵ ϭϬ ϯϴ ϭϭ ϯϳ ϭϮ ϯϲ ϭϯ ϯϱ ϭϰ ϯϰ ϭϱ ϯϯ ϭϲ ϭϳ ϭϴ ϭϵ ϮϬ Ϯϭ ϮϮ Ϯϯ Ϯϰ Ϯϱ Ϯϲ Ϯϳ Ϯϴ Ϯϵ ϯϬ ϯϭ ϯϮ sͺϮ s ^^ͺϮ W ϭϯ W ϭϮ W ϭϭ W ϭϬ W ϵ W ϴ Wϵ Wϴ Wϳ Wϲ W ϭϱ W ϭϰ W ϭϯ W ϭϮ W ϯ s ^^ͺϰ sͺϰ W ϰ W ϱ W ϲ W ϳ Wϰ Wϱ W Ϭ W ϭ W Ϯ Wϭ Ϭ Wϭ ϭ s ^^ͺϭ sͺϭ sd WϭϯͲdDWZͲZd W ϭϰͲK ^ ϯϮͺ/E W ϭϱͲK ^ ϯϮͺKh d W  ϬͲK^ ͺ/E W  ϭͲK^ ͺKhd EZ^d WϬ Wϭ WϮ Wϯ s^^ s W ϬͲt< hW W ϭ W Ϯ DL 1. The above figure shows the package top view. Table 5. STM32F101xC/STM32F101xD/STM32F101xE pin definitions Alternate functions(4) I / O Level(2) Remap LQFP100 Default LQFP64 Main function(3) (after reset) LQFP144 Type(1) Pins Pin name 1 - 1 PE2 I/O FT PE2 TRACECLK/ FSMC_A23 - 2 - 2 PE3 I/O FT PE3 TRACED0/FSMC_A19 - 3 - 3 PE4 I/O FT PE4 TRACED1/FSMC_A20 - 4 - 4 PE5 I/O FT PE5 TRACED2/FSMC_A21 - 5 - 5 PE6 I/O FT PE6 TRACED3/FSMC_A22 - 6 1 6 VBAT - VBAT - - 7 2 7 - PC13(6) TAMPER-RTC - - PC14(6) OSC32_IN - - PC15(6) OSC32_OUT - 8 3 S PC13-TAMPER-RTC(5) I/O 8 PC14-OSC32_IN(5) I/O 9 4 9 PC15-OSC32_OUT(5) 10 - - PF0 I/O FT PF0 FSMC_A0 - 11 - - PF1 I/O FT PF1 FSMC_A1 - I/O DocID14610 Rev 9 25/121 120 Pinouts and pin descriptions STM32F101xC, STM32F101xD, STM32F101xE Table 5. STM32F101xC/STM32F101xD/STM32F101xE pin definitions (continued) Alternate functions(4) I / O Level(2) Remap LQFP100 Default LQFP64 Main function(3) (after reset) LQFP144 Type(1) Pins Pin name 12 - - PF2 I/O FT PF2 FSMC_A2 - 13 - - PF3 I/O FT PF3 FSMC_A3 - 14 - - PF4 I/O FT PF4 FSMC_A4 - 15 - - PF5 I/O FT PF5 FSMC_A5 - 16 - 10 VSS_5 S - VSS_5 - - 17 - 11 VDD_5 S - VDD_5 - - 18 - - PF6 I/O - PF6 FSMC_NIORD - 19 - - PF7 I/O - PF7 FSMC_NREG - 20 - - PF8 I/O - PF8 FSMC_NIOWR - 21 - - PF9 I/O - PF9 FSMC_CD - 22 - - PF10 I/O - PF10 FSMC_INTR - 23 5 12 OSC_IN I - OSC_IN - PD0(7) 24 6 13 OSC_OUT O - OSC_OUT - PD1(7) 25 7 14 NRST I/O - NRST - - 26 8 15 PC0 I/O - PC0 ADC_IN10 - 27 9 16 PC1 I/O - PC1 ADC_IN11 - 28 10 17 PC2 I/O - PC2 ADC_IN12 - 29 11 18 PC3 I/O - PC3 ADC_IN13 - 30 12 19 VSSA S - VSSA - - 31 - 20 VREF- S - VREF- - - 32 - 21 VREF+ S - VREF+ - - 33 13 22 VDDA S - VDDA - - USART2_CTS(8)/ 34 14 23 PA0-WKUP I/O - PA0 WKUP/ ADC_IN0/TIM5_CH1/ TIM2_CH1_ETR(8) - 35 15 24 PA1 I/O - PA1 USART2_RTS(8)/ ADC_IN1/TIM5_CH2 TIM2_CH2(8) - 36 16 25 PA2 I/O - PA2 USART2_TX(8)/ TIM5_CH3/ADC_IN2/ TIM2_CH3(8) - 26/121 DocID14610 Rev 9 STM32F101xC, STM32F101xD, STM32F101xE Pinouts and pin descriptions Table 5. STM32F101xC/STM32F101xD/STM32F101xE pin definitions (continued) Alternate functions(4) I / O Level(2) Pin name Type(1) LQFP100 LQFP64 LQFP144 Pins Main function(3) (after reset) Default Remap - 37 17 26 PA3 I/O - PA3 USART2_RX(8)/ TIM5_CH4 / ADC_IN3/ TIM2_CH4(8) 38 18 27 VSS_4 S - VSS_4 - - 39 19 28 VDD_4 S - VDD_4 - - 40 20 29 PA4 I/O - PA4 SPI1_NSS/ DAC_OUT1 ADC_IN4 / USART2_CK(8) - 41 21 30 PA5 I/O - PA5 SPI1_SCK/ DAC_OUT2/ADC_IN5 - 42 22 31 PA6 I/O - PA6 SPI1_MISO / ADC_IN6 / TIM3_CH1(8) - 43 23 32 PA7 I/O - PA7 SPI1_MOSI / ADC_IN7/ TIM3_CH2(8) - 44 24 33 PC4 I/O - PC4 ADC_IN14 - 45 25 34 PC5 I/O - PC5 ADC_IN15 - 46 26 35 PB0 I/O - PB0 ADC_IN8 / TIM3_CH3(8) - PB1 ADC_IN9/TIM3_CH4(8) - 47 27 36 PB1 I/O 48 28 37 PB2 I/O FT PB2/BOOT1 - - 49 - - PF11 I/O FT PF11 FSMC_NIOS16 - 50 - - PF12 I/O FT PF12 FSMC_A6 - 51 - - VSS_6 S - VSS_6 - - 52 - - VDD_6 S - VDD_6 - - 53 - - PF13 I/O FT PF13 FSMC_A7 - 54 - - PF14 I/O FT PF14 FSMC_A8 - 55 - - PF15 I/O FT PF15 FSMC_A9 - 56 - - PG0 I/O FT PG0 FSMC_A10 - 57 - - PG1 I/O FT PG1 FSMC_A11 - 58 - 38 PE7 I/O FT PE7 FSMC_D4 - 59 - 39 PE8 I/O FT PE8 FSMC_D5 - 60 - 40 PE9 I/O FT PE9 FSMC_D6 - 61 - - VSS_7 VSS_7 - - S - - DocID14610 Rev 9 27/121 120 Pinouts and pin descriptions STM32F101xC, STM32F101xD, STM32F101xE Table 5. STM32F101xC/STM32F101xD/STM32F101xE pin definitions (continued) Alternate functions(4) I / O Level(2) - VDD_7 LQFP100 S LQFP64 Main function(3) (after reset) LQFP144 Type(1) Pins Pin name 62 - - VDD_7 63 - 41 PE10 I/O FT PE10 FSMC_D7 - 64 - 42 PE11 I/O FT PE11 FSMC_D8 - 65 - 43 PE12 I/O FT PE12 FSMC_D9 - 66 - 44 PE13 I/O FT PE13 FSMC_D10 - 67 - 45 PE14 I/O FT PE14 FSMC_D11 - 68 - 46 PE15 I/O FT PE15 FSMC_D12 - 69 29 47 PB10 I/O FT PB10 I2C2_SCL/ USART3_TX(8) TIM2_CH3 PB11 USART3_RX(8) TIM2_CH4 Remap - - 70 30 48 PB11 71 31 49 VSS_1 S - VSS_1 - - 72 32 50 VDD_1 S - VDD_1 - - 73 33 51 PB12 I/O FT PB12 SPI2_NSS(8)/ I2C2_SMBA USART3_CK(8) - 74 34 52 PB13 I/O FT PB13 SPI2_SCK(8)/ USART3_CTS(8) - 75 35 53 PB14 I/O FT PB14 SPI2_MISO(8)/ USART3_RTS(8) - 76 36 54 PB15 I/O FT PB15 SPI2_MOSI(8) - 77 - 55 PD8 I/O FT PD8 FSMC_D13 USART3_TX 78 - 56 PD9 I/O FT PD9 FSMC_D14 USART3_RX 79 - 57 PD10 I/O FT PD10 FSMC_D15 USART3_CK 80 - 58 PD11 I/O FT PD11 FSMC_A16 USART3_CTS 81 - 59 PD12 I/O FT PD12 FSMC_A17 TIM4_CH1 / USART3_RTS 82 - 60 PD13 I/O FT PD13 FSMC_A18 TIM4_CH2 83 - - VSS_8 S - VSS_8 - - 84 - - VDD_8 S - VDD_8 - - 85 - 61 PD14 I/O FT PD14 FSMC_D0 TIM4_CH3 86 - 62 PD15 I/O FT PD15 FSMC_D1 TIM4_CH4 87 - - PG2 I/O FT PG2 FSMC_A12 - 28/121 I/O FT Default DocID14610 Rev 9 I2C2_SDA/ STM32F101xC, STM32F101xD, STM32F101xE Pinouts and pin descriptions Table 5. STM32F101xC/STM32F101xD/STM32F101xE pin definitions (continued) Alternate functions(4) I / O Level(2) Remap LQFP100 Default LQFP64 Main function(3) (after reset) LQFP144 Type(1) Pins Pin name 88 - - PG3 I/O FT PG3 FSMC_A13 - 89 - - PG4 I/O FT PG4 FSMC_A14 - 90 - - PG5 I/O FT PG5 FSMC_A15 - 91 - - PG6 I/O FT PG6 FSMC_INT2 - 92 - - PG7 I/O FT PG7 FSMC_INT3 - 93 - - PG8 I/O FT PG8 - - 94 - - VSS_9 S - VSS_9 - - 95 - - VDD_9 S - VDD_9 - - 96 37 63 PC6 I/O FT PC6 - TIM3_CH1 97 38 64 PC7 I/O FT PC7 - TIM3_CH2 98 39 65 PC8 I/O FT PC8 - TIM3_CH3 99 40 66 PC9 I/O FT PC9 - TIM3_CH4 100 41 67 PA8 I/O FT PA8 USART1_CK/ MCO - PA9 USART1_TX(8) - 101 42 68 PA9 I/O FT 102 43 69 PA10 I/O FT PA10 USART1_RX(8) 103 44 70 PA11 I/O FT PA11 USART1_CTS - 104 45 71 PA12 I/O FT PA12 USART1_RTS - 105 46 72 PA13 I/O FT JTMS-SWDIO - PA13 106 - 73 107 47 74 VSS_2 S - VSS_2 - - 108 48 75 VDD_2 S - VDD_2 - - 109 49 76 PA14 I/O FT JTCK-SWCLK - PA14 110 50 77 PA15 I/O FT JTDI SPI3_NSS TIM2_CH1_ETR/ PA15 /SPI1_NSS 111 51 78 PC10 I/O FT PC10 UART4_TX USART3_TX 112 52 79 PC11 I/O FT PC11 UART4_RX USART3_RX 113 53 80 PC12 I/O FT PC12 UART5_TX USART3_CK 114 - 81 PD0 I/O FT OSC_IN(8) FSMC_D2(9) - (9) - 115 - 82 Not connected PD1 I/O FT (8) OSC_OUT DocID14610 Rev 9 FSMC_D3 29/121 120 Pinouts and pin descriptions STM32F101xC, STM32F101xD, STM32F101xE Table 5. STM32F101xC/STM32F101xD/STM32F101xE pin definitions (continued) Alternate functions(4) I / O Level(2) Remap LQFP100 Default LQFP64 Main function(3) (after reset) LQFP144 Type(1) Pins Pin name 116 54 83 PD2 I/O FT PD2 TIM3_ETR/UART5_RX - 117 - 84 PD3 I/O FT PD3 FSMC_CLK USART2_CTS 118 - 85 PD4 I/O FT PD4 FSMC_NOE USART2_RTS 119 - 86 PD5 I/O FT PD5 FSMC_NWE USART2_TX 120 - - VSS_10 S - VSS_10 - - 121 - - VDD_10 S - VDD_10 - - 122 - 87 PD6 I/O FT PD6 FSMC_NWAIT USART2_RX 123 - 88 PD7 I/O FT PD7 FSMC_NE1/ FSMC_NCE2 USART2_CK 124 - - PG9 I/O FT PG9 FSMC_NE2/ FSMC_NCE3 - 125 - - PG10 I/O FT PG10 FSMC_NE3/ FSMC_NCE4_1 - 126 - - PG11 I/O FT PG11 FSMC_NCE4_2 - 127 - - PG12 I/O FT PG12 FSMC_NE4 - 128 - - PG13 I/O FT PG13 FSMC_A24 - 129 - - PG14 I/O FT PG14 FSMC_A25 - 130 - - VSS_11 S - VSS_11 - - 131 - - VDD_11 S - VDD_11 - - 132 - - PG15 I/O FT PG15 - - 133 55 89 PB3 I/O FT JTDO SPI3_SCK TIM2_CH2 /PB3 TRACESWO SPI1_SCK 134 56 90 PB4 I/O FT NJTRST SPI3_MISO PB4 / TIM3_CH1 SPI1_MISO 135 57 91 PB5 I/O PB5 I2C1_SMBA/ SPI3_MOSI TIM3_CH2 / SPI1_MOSI 136 58 92 PB6 I/O FT PB6 I2C1_SCL/ TIM4_CH1(8) USART1_TX 137 59 93 PB7 I/O FT PB7 I2C1_SDA/FSMC_NADV TIM4_CH2(8) USART1_RX 138 60 94 BOOT0 BOOT0 - - 139 30/121 61 95 PB8 I - I/O FT PB8 DocID14610 Rev 9 TIM4_CH3 (8) I2C1_SCL STM32F101xC, STM32F101xD, STM32F101xE Pinouts and pin descriptions Table 5. STM32F101xC/STM32F101xD/STM32F101xE pin definitions (continued) Alternate functions(4) LQFP100 140 62 96 PB9 I / O Level(2) LQFP64 Pin name Type(1) LQFP144 Pins I/O FT Main function(3) (after reset) Default Remap PB9 TIM4_CH4 (8) I2C1_SDA TIM4_ETR(8) / FSMC_NBL0 - PE1 FSMC_NBL1 - - VSS_3 - - - VDD_3 - - 141 - 97 PE0 I/O FT PE0 142 - 98 PE1 I/O FT 143 63 99 VSS_3 S 144 64 100 VDD_3 S 1. I = input, O = output, S = supply. 2. FT = 5 V tolerant. 3. Function availability depends on the chosen device. 4. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register). 5. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output mode is limited: the speed should not exceed 2 MHz with a maximum load of 30 pF and these IOs must not be used as a current source (e.g. to drive an LED). 6. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the Battery backup domain and BKP register description sections in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com. 7. For the LQFP64 package, the pins number 5 and 6 are configured as OSC_IN/OSC_OUT after reset, however the functionality of PD0 and PD1 can be remapped by software on these pins. For the LQFP100 and LQFP144 packages, PD0 and PD1 are available by default, so there is no need for remapping. For more details, refer to Alternate function I/O and debug configuration section in the STM32F10xxx reference manual 8. This alternate function can be remapped by software to some other port pins (if available on the used package). For more details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com. 9. For devices delivered in LQFP64 packages, the FSMC function is not available. DocID14610 Rev 9 31/121 120 Pinouts and pin descriptions STM32F101xC, STM32F101xD, STM32F101xE Table 6. FSMC pin definition FSMC Pins 32/121 LQFP100(1) CF CF/IDE NOR/PSRAM/ SRAM PE2 - - A23 A23 - Yes PE3 - - A19 A19 - Yes PE4 - - A20 A20 - Yes PE5 - - A21 A21 - Yes PE6 - - A22 A22 - Yes PF0 A0 A0 A0 - - - PF1 A1 A1 A1 - - - PF2 A2 A2 A2 - - - PF3 A3 - A3 - - - PF4 A4 - A4 - - - PF5 A5 - A5 - - - PF6 NIORD NIORD - - - - PF7 NREG NREG - - - - PF8 NIOWR NIOWR - - - - PF9 CD CD - - - - PF10 INTR INTR - - - - PF11 NIOS16 NIOS16 - - - - PF12 A6 - A6 - - - PF13 A7 - A7 - - - PF14 A8 - A8 - - - PF15 A9 - A9 - - - PG0 A10 - A10 - - - PG1 - - A11 - - - PE7 D4 D4 D4 DA4 D4 Yes PE8 D5 D5 D5 DA5 D5 Yes PE9 D6 D6 D6 DA6 D6 Yes PE10 D7 D7 D7 DA7 D7 Yes PE11 D8 D8 D8 DA8 D8 Yes PE12 D9 D9 D9 DA9 D9 Yes PE13 D10 D10 D10 DA10 D10 Yes PE14 D11 D11 D11 DA11 D11 Yes PE15 D12 D12 D12 DA12 D12 Yes PD8 D13 D13 D13 DA13 D13 Yes DocID14610 Rev 9 NOR/PSRAM Mux NAND 16 bit STM32F101xC, STM32F101xD, STM32F101xE Pinouts and pin descriptions Table 6. FSMC pin definition (continued) FSMC Pins LQFP100(1) CF CF/IDE NOR/PSRAM/ SRAM NOR/PSRAM Mux NAND 16 bit PD9 D14 D14 D14 DA14 D14 Yes PD10 D15 D15 D15 DA15 D15 Yes PD11 - - A16 A16 CLE Yes PD12 - - A17 A17 ALE Yes PD13 - - A18 A18 PD14 D0 D0 D0 DA0 D0 Yes PD15 D1 D1 D1 DA1 D1 Yes PG2 - - A12 - - - PG3 - - A13 - - - PG4 - - A14 - - - PG5 - - A15 - - - PG6 - - - - INT2 - PG7 - - - - INT3 - PD0 D2 D2 D2 DA2 D2 Yes PD1 D3 D3 D3 DA3 D3 Yes PD3 - - CLK CLK - Yes PD4 NOE NOE NOE NOE NOE Yes PD5 NWE NWE NWE NWE NWE Yes PD6 NWAIT NWAIT NWAIT NWAIT NWAIT Yes PD7 - - NE1 NE1 NCE2 Yes PG9 - - NE2 NE2 NCE3 - PG10 NCE4_1 NCE4_1 NE3 NE3 - - PG11 NCE4_2 NCE4_2 - - - - PG12 - - NE4 NE4 - - PG13 - - A24 A24 - - PG14 - - A25 A25 - - PB7 - - NADV NADV - Yes PE0 - - NBL0 NBL0 - Yes PE1 - - NBL1 NBL1 - Yes Yes 1. Ports F and G are not available in devices delivered in 100-pin packages. DocID14610 Rev 9 33/121 120 Memory mapping 4 STM32F101xC, STM32F101xD, STM32F101xE Memory mapping The memory map is shown in Figure 6. 34/121 DocID14610 Rev 9 STM32F101xC, STM32F101xD, STM32F101xE Memory mapping Figure 6. Memory map 5HVHUYHG )60&UHJLVWHU [$[$))) )60&EDQN3&&$5' [[))))))) )60&EDQN1$1'1$1' [[))))))) )60&EDQN1$1'1$1' [[))))))) )60&EDQN125365$0 [&[))))))) )60&EDQN125365$0 [[%)))))) )60&EDQN125365$0 [[)))))) )60&EDQN125365$0 [[)))))) [[))))))) 5HVHUYHG &5& [)))))))) [( ['))))))) 0E\WH EORFN &RUWH[0 V LQWHUQDO SHULSKHUDOV 0E\WH EORFN 1RWXVHG 0E\WH EORFN )60&UHJLVWHU [ [))))))) [ [))))))) 0E\WH EORFN )60&EDQN EDQN 0E\WH EORFN )60&EDQN EDQN 0E\WH EORFN 3HULSKHUDOV [ [))))))) 0E\WH EORFN 65$0 [ [))))))) 0E\WH EORFN &RGH [ 5HVHUYHG 65$0.%DOLDVHG E\ELWEDQGLQJ 2SWLRQ%\WHV 6\VWHPPHPRU\ 5HVHUYHG )ODVK 5HVHUYHG $OLDVHGWR)ODVKRUV\VWHP PHPRU\GHSHQGLQJRQ %227SLQV [[)) 5HVHUYHG [[))) )ODVKLQWHUIDFH 5HVHUYHG [[))) [[)) 5&& [[)) 5HVHUYHG [[))) '0$ [[)) '0$ 5HVHUYHG 5HVHUYHG [[)) [[)))) [[)) 5HVHUYHG [&[))) [[%)) [[)) [[)) 86$57 5HVHUYHG 63, 5HVHUYHG [[))) $'& [[)) 3RUW* 3RUW) [[)) [&[))) [[%)) [[)) [[)) [&[))) [[%)) [[)) [[)) [[)))) 3RUW( 3RUW' 3RUW& 3RUW% 3RUW$ (;7, $),2 5HVHUYHG '$& 3:5 [& [%))))))) [$ [))))))) [$[%))))))) [[)) [[)) %.3 [&[))) 5HVHUYHG [&[%)) ,& ,& [[%)) [[)) 8$57 [[)) 8$57 [&[))) 86$57 86$57 [[%)) [[)) 5HVHUYHG [[)) 63, [&[))) 63, [[%)) 5HVHUYHG ,:'* [[)) ::'* [&[))) 57& [[%)) 5HVHUYHG [[)) 7,0 [[)) [[)) 7,0 [[)) 7,0 [&[))) 7,0 [[%)) 7,0 [[)) 7,0 [[)) [))))))) [& [%))) [ [))))[))))) [))))[)))))) [)))())) [ [)))) [ [)))))) [ [)))) [ DLF DocID14610 Rev 9 35/121 120 Electrical characteristics STM32F101xC, STM32F101xD, STM32F101xE 5 Electrical characteristics 5.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 5.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3Σ). 5.1.2 Typical values Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3.3 V (for the 2 V ≤ VDD ≤ 3.6 V voltage range). They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean±2Σ). 5.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 5.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 7. 36/121 DocID14610 Rev 9 STM32F101xC, STM32F101xD, STM32F101xE 5.1.5 Electrical characteristics Pin input voltage The input voltage measurement on a pin of the device is described in Figure 8. Figure 7. Pin loading conditions Figure 8. Pin input voltage 670)3,1 670)3,1 9,1 & S) DL DL 5.1.6 Power supply scheme Figure 9. Power supply scheme 9%$7  9 %DFNXSFLUFXLWU\ 26&.57& :DNHXSORJLF %DFNXSUHJLVWHUV 287 *3,2V ,1 /HYHOVKLIWHU 3R ZHUVZL WFK ,2 /RJLF .HUQHOORJLF &38 'LJLWDO 0HPRULHV 9'' 9'' 5HJXODWRU îQ) î—) 966 9'' 9''$ 95() Q) —) Q) —) 95() 95() $'& '$& $QDORJ 5&V3//  966$ DL Caution: In Figure 9, the 4.7 µF capacitor must be connected to VDD3. DocID14610 Rev 9 37/121 120 Electrical characteristics 5.1.7 STM32F101xC, STM32F101xD, STM32F101xE Current consumption measurement Figure 10. Current consumption measurement scheme )$$?6"!4 6"!4 )$$ 6$$ 6$$! AI 5.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 7: Voltage characteristics, Table 8: Current characteristics, and Table 9: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 7. Voltage characteristics Symbol VDD − VSS VIN (2) |ΔVDDx| |VSSX − VSS| VESD(HBM) Ratings Min Max –0.3 4.0 Input voltage on five volt tolerant pin VSS − 0.3 VDD + 4.0 Input voltage on any other pin VSS − 0.3 4.0 Variations between different VDD power pins - 50 Variations between all the different ground pins - 50 External main supply voltage (including VDDA and VDD)(1) Electrostatic discharge voltage (human body model) Unit V mV see Section 5.3.12: Absolute maximum ratings (electrical sensitivity) 1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. VIN maximum must always be respected. Refer to Table 8: Current characteristics for the maximum allowed injected current values. 38/121 DocID14610 Rev 9 STM32F101xC, STM32F101xD, STM32F101xE Electrical characteristics Table 8. Current characteristics Symbol ΣIVDD ΣIVSS IIO Ratings Max. Total current into VDD/VDDA power lines (source)(1) 150 (1) Total current out of VSS ground lines (sink) 150 Output current sunk by any I/O and control pin 25 − 25 Output current source by any I/Os and control pin (3) IINJ(PIN)(2) ΣIINJ(PIN) Injected current on five volt tolerant pins mA -5/+0 (4) ±5 Injected current on any other pin Total injected current (sum of all I/O and control pins) Unit (5) ± 25 1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. Negative injection disturbs the analog performance of the device. See note 3 below Table 58 on page 98. 3. Positive injection is not possible on these I/Os. A negative injection is induced by VINVDD while a negative injection is induced by VIN 8 MHz. Table 15. Maximum current consumption in Run mode, code with data processing running from RAM Max(1) Symbol Parameter Conditions External clock (2), all peripherals enabled IDD Supply current in Run mode External clock(2) all peripherals disabled fHCLK Unit TA = 85 °C 36 MHz 34 24 MHz 24 16 MHz 17 8 MHz 10 36 MHz 18 24 MHz 13 16 MHz 10 8 MHz 6 mA 1. Guaranteed by characterization results, tested in production at VDD max, fHCLK max. 2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz. DocID14610 Rev 9 43/121 120 Electrical characteristics STM32F101xC, STM32F101xD, STM32F101xE Figure 11. Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals enabled 35 30 8 MHz 16 MHz Consumption (mA) 25 24 MHz 36 MHz 20 15 10 5 0 -45 25 70 85 Temperature (°C) Figure 12. Typical current consumption in Run mode versus frequency (at 3.6 V) code with data processing running from RAM, peripherals disabled 18 16 Consumption (mA) 8 MHz 14 16 MHz 12 24 MHz 36 MHz 10 8 6 4 2 0 -45 25 70 Temperature (°C) 44/121 DocID14610 Rev 9 85 STM32F101xC, STM32F101xD, STM32F101xE Electrical characteristics Table 16. Maximum current consumption in Sleep mode, code running from Flash or RAM Max(1) Symbol Parameter Conditions fHCLK External clock(2) all peripherals enabled IDD Supply current in Sleep mode External clock(2), all peripherals disabled Unit TA = 85 °C 36 MHz 24 24 MHz 17 16 MHz 12.5 8 MHz 8 36 MHz 6 24 MHz 5 16 MHz 4.5 8 MHz 4 mA 1. Guaranteed by characterization results, tested in production at VDD max, fHCLK max with peripherals enabled. 2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz. Table 17. Typical and maximum current consumptions in Stop and Standby modes Typ(1) Symbol Parameter Supply current in Stop mode IDD Supply current in Standby mode IDD_VBAT Max VDD/ VBAT = 2.0 V VDD/ VBAT = 2.4 V VDD/VBA T TA = 85 °C Regulator in Run mode, Low-speed and high-speed internal RC oscillators and high-speed oscillator OFF (no independent watchdog) - 34.5 35 379 Regulator in Low-power mode, Low-speed and high-speed internal RC oscillators and high-speed oscillator OFF (no independent watchdog) - 24.5 25 365 Low-speed internal RC oscillator and independent watchdog ON - 3 3.8 - Low-speed internal RC oscillator ON, independent watchdog OFF - 2.8 3.6 - Low-speed internal RC oscillator and independent watchdog OFF, low-speed oscillator and RTC OFF - 1.9 2.1 5(2) 1.05 1.1 1.4 2(2) Conditions Backup domain Low-speed oscillator and RTC ON supply current = 3.3 V Unit µA 1. Typical values are measured at TA = 25 °C. 2. Guaranteed by characterization results, not tested in production. DocID14610 Rev 9 45/121 120 Electrical characteristics STM32F101xC, STM32F101xD, STM32F101xE Figure 13. Typical current consumption on VBAT with RTC on vs. temperature at different VBAT values  &RQVXPSWLRQ—$  9  9 9 9  9   ±    7HPSHUDWXUHƒ& DL Figure 14. Typical current consumption in Stop mode with regulator in run mode versus temperature at different VDD values 300 Consumption (µA) 250 200 150 100 2.4V 2.7V 3.0V 3.3V 3.6V 50 0 -45 25 70 Temperature (°C) 46/121 DocID14610 Rev 9 85 STM32F101xC, STM32F101xD, STM32F101xE Electrical characteristics Figure 15. Typical current consumption in Stop mode with regulator in low-power mode versus temperature at different VDD values 300 Consumption (µA) 250 200 150 100 2.4V 2.7V 3.0V 3.3V 3.6V 50 0 -45 25 70 85 Temperature (°C) Figure 16. Typical current consumption in Standby mode versus temperature at different VDD values 3.5 3 Consumption (µA) 2.5 2 1.5 1 2.4V 2.7V 3.0V 3.3V 3.6V 0.5 0 -45 25 70 85 Temperature (°C) DocID14610 Rev 9 47/121 120 Electrical characteristics STM32F101xC, STM32F101xD, STM32F101xE Typical current consumption The MCU is placed under the following conditions: • All I/O pins are in input mode with a static value at VDD or VSS (no load) • All peripherals are disabled except if it is explicitly mentioned • The Flash access time is adjusted to fHCLK frequency (0 wait state from 0 to 24 MHz, 1 wait state from 24 to 36 MHz) • Prefetch is on (reminder: this bit must be set before clock setting and bus prescaling) • When the peripherals are enabled fPCLK1 = fHCLK/4, fPCLK2 = fHCLK/2, fADCCLK = fPCLK2/4 • When the peripherals are enabled fPCLK1 = fHCLK, fPCLK2 = fHCLK, fADCCLK = fPCLK2/2 The parameters given in Table 18 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 10. Table 18. Typical current consumption in Run mode, code with data processing running from Flash Symbol Parameter Conditions External clock(3) IDD Supply current in Run mode Running on high speed internal RC (HSI), AHB prescaler used to reduce the frequency Typ(1) Typ(1) All peripherals enabled(2) All peripherals disabled 36 MHz 26.6 16.2 24 MHz 18.5 11.4 16 MHz 12.8 8.2 8 MHz 7.2 5 4 MHz 4.2 3.1 2 MHz 2.7 2.1 1 MHz 2 1.7 500 kHz 1.6 1.4 125 kHz 1.3 1.2 36 MHz 26 15.6 24 MHz 17.9 10.8 16 MHz 12.2 7.6 8 MHz 6.6 4.4 4 MHz 3.6 2.5 2 MHz 2.1 1.5 1 MHz 1.4 1.1 500 kHz 1 0.8 125 kHz 0.7 0.6 fHCLK 1. Typical values are measures at TA = 25 °C, VDD = 3.3 V. 2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register). 3. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz. 48/121 DocID14610 Rev 9 Unit mA STM32F101xC, STM32F101xD, STM32F101xE Electrical characteristics Table 19. Typical current consumption in Sleep mode, code running from Flash or RAM Typ(1) Symbol Parameter Conditions (3) External clock Supply current in Sleep mode IDD Running on High Speed Internal RC (HSI), AHB prescaler used to reduce the frequency fHCLK Typ(1) All peripherals All peripherals enabled(2) disabled 36 MHz 15.1 3.6 24 MHz 10.4 2.6 16 MHz 7.2 2 8 MHz 3.9 1.3 4 MHz 2.6 1.2 2 MHz 1.85 1.15 1 MHz 1.5 1.1 500 kHz 1.3 1.05 125 kHz 1.2 1.05 36 MHz 14.5 3 24 MHz 9.8 2 16 MHz 6.6 1.4 8 MHz 3.3 0.7 4 MHz 2 0.6 2 MHz 1.25 0.55 1 MHz 0.9 0.5 500 kHz 0.7 0.45 125 kHz 0.6 0.45 Unit mA 1. Typical values are measures at TA = 25 °C, VDD = 3.3 V. 2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register). 3. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz. On-chip peripheral current consumption The current consumption of the on-chip peripherals is given in Table 20. The MCU is placed under the following conditions: • all I/O pins are in input mode with a static value at VDD or VSS (no load) • all peripherals are disabled unless otherwise mentioned • the given value is calculated by measuring the current consumption • – with all peripherals clocked off – with only one peripheral clocked on ambient operating temperature and VDD supply voltage conditions summarized in Table 7. DocID14610 Rev 9 49/121 120 Electrical characteristics STM32F101xC, STM32F101xD, STM32F101xE Table 20. Peripheral current consumption(1) Peripherals µA/MHz AHB (up to36 MHz) DMA1 20.42 DMA2 19.03 FSMC 52.36 CRC 2.36 (2) 9.72 APB1-Bridge 7.78 TIM2 33.06 TIM3 31.94 TIM4 31.67 TIM5 31.94 TIM6 8.06 BusMatrix TIM7 APB1 (up to 18 MHz) 50/121 8.06 (3) SPI2/I2S2 8.33 SPI3/I2S3(3) 8.33 USART2 12.22 USART3 12.22 UART4 12.22 UART5 12.22 I2C1 10.28 I2C2 10.00 USB 18.06 DAC(4) 8.06 WWDG 3.89 PWR 1.11 BKP 1.11 IWDG 5.28 DocID14610 Rev 9 STM32F101xC, STM32F101xD, STM32F101xE Electrical characteristics Table 20. Peripheral current consumption(1) (continued) Peripherals µA/MHz APB2-Bridge 4.17 GPIOA 8.47 GPIOB 8.47 GPIOC 6.53 GPIOD 8.47 GPIOE 6.53 GPIOF 6.53 GPIOG 6.11 SPI1 4.72 USART1 12.50 TIM1 22.92 TIM8 22.92 APB2 (up to 36 MHz) (5)(6) 17.32 ADC1 1. fHCLK = 36 MHz, fAPB1 = fHCLK/2, fAPB2 = fHCLK, default prescaler value for each peripheral. 2. The BusMatrix is automatically active when at least one master peripheral is ON. 3. When the I2S is enabled, a current consumption of 0.02 mA must be added. 4. When DAC_OUT1 or DAC_OUT2 is enabled, a current consumption of 0.36 mA must be added. 5. Specific conditions for ADC: fHCLK = 28 MHz, fAPB1 = fHCLK/2, fAPB2 = fHCLK, fADCCLK = fAPB2/2. When ADON bit in the ADC_CR2 register is set to 1, the current consumption is equal to 0.54 mA. 6. When the ADC is enabled, a current consumption of 0.08 mA must be added. 5.3.6 External clock source characteristics High-speed external user clock generated from an external source The characteristics given in Table 21 result from tests performed using an high-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 10. Table 21. High-speed external user clock characteristics Symbol Parameter Conditions Min Typ Max Unit MHz fHSE_ext User external clock source frequency(1) 1 8 25 VHSEH OSC_IN input pin high level voltage 0.7VDD - VDD VHSEL OSC_IN input pin low level voltage VSS - 0.3VDD tw(HSE) tw(HSE) OSC_IN high or low time(1) 5 - - tr(HSE) tf(HSE) OSC_IN rise or fall time(1) - - 20 V - ns DocID14610 Rev 9 51/121 120 Electrical characteristics STM32F101xC, STM32F101xD, STM32F101xE Table 21. High-speed external user clock characteristics Symbol Cin(HSE) Parameter Conditions Min Typ Max Unit - - 5 - pF - 45 - 55 % VSS ≤ VIN ≤ VDD - - ±1 µA (1) OSC_IN input capacitance DuCy(HSE) Duty cycle IL OSC_IN Input leakage current 1. Guaranteed by design, not tested in production Low-speed external user clock generated from an external source The characteristics given in Table 22 result from tests performed using an low-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 10. Table 22. Low-speed user external clock characteristics Symbol Parameter Conditions Min Typ Max Unit kHz fLSE_ext User external clock source frequency(1) - - 32.768 1000 VLSEH OSC32_IN input pin high level voltage - 0.7VDD - VDD VLSEL OSC32_IN input pin low level voltage - VSS - 0.3VDD tw(LSE) tw(LSE) OSC32_IN high or low time(1) - 450 - - tr(LSE) tf(LSE) Cin(LSE) V ns OSC32_IN rise or fall time(1) - - - 50 - - 5 - pF - 30 - 70 % VSS ≤ VIN ≤ VDD - - ±1 µA OSC32_IN input capacitance(1) DuCy(LSE) Duty cycle IL OSC32_IN Input leakage current 1. Guaranteed by design, not tested in production. 52/121 DocID14610 Rev 9 STM32F101xC, STM32F101xD, STM32F101xE Electrical characteristics Figure 17. High-speed external clock source AC timing diagram 9+6(+   9+6(/ WU+6( W W:+6( W:+6( 7+6( ([WHUQDOFORFNVRXUFH I+6(BH[W ,/ 26&B,1 670)[[[ DLE Figure 18. Low-speed external clock source AC timing diagram 9/6(+   9/6(/ WU/6( WI/6( W:/6( 26&B,1 ,/ W:/6( W 7/6( ([WHUQDO FORFNVRXUFH I/6(BH[W 670)[[[ DLF DocID14610 Rev 9 53/121 120 Electrical characteristics STM32F101xC, STM32F101xD, STM32F101xE High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 4 to 16 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 23. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 23. HSE 4-16 MHz oscillator characteristics(1)(2) Symbol Conditions Min Typ Max Unit Oscillator frequency - 4 8 16 MHz RF Feedback resistor - - 200 - kΩ C Recommended load capacitance versus equivalent serial RS = 30 Ω resistance of the crystal (RS)(3) - 30 - pF i2 HSE driving current VDD = 3.3 V VIN = VSS with 30 pF load - - 1 mA gm Oscillator transconductance Startup 25 - - mA/V - 2 - ms fOSC_IN Parameter tSU(HSE)(4) Startup time VDD is stabilized 1. Resonator characteristics given by the crystal/ceramic resonator manufacturer. 2. Guaranteed by characterization results, not tested in production. 3. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a humid environment, due to the induced leakage and the bias condition change. However, it is recommended to take this point into account if the MCU is used in tough humidity conditions. 4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the 5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see Figure 19). CL1 and CL2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing CL1 and CL2. Refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com. 54/121 DocID14610 Rev 9 STM32F101xC, STM32F101xD, STM32F101xE Electrical characteristics Figure 19. Typical application with an 8 MHz crystal 5HVRQDWRUZLWK LQWHJUDWHGFDSDFLWRUV &/ 0+ ] UHVRQDWRU &/ I+6( 26&B,1 5(;7 5) %LDV FRQWUROOHG JDLQ 670)[[[ 26&B28 7 DLE 1. REXT value depends on the crystal characteristics. Low-speed external clock generated from a crystal/ceramic resonator The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 24. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 24. LSE oscillator characteristics (fLSE = 32.768 kHz)(1) (2) Symbol Parameter RF Feedback resistor C Conditions Min Typ Max Unit - - - 5 - MΩ Recommended load capacitance versus equivalent serial resistance of the crystal (RS) RS = 30 KΩ - - - 15 pF I2 LSE driving current VDD = 3.3 V VIN = VSS - - - 1.4 µA gm Oscillator transconductance - - 5 - - µA/V TA = 50 °C - 1.5 - TA = 25 °C - 2.5 - TA = 10 °C - 4 - TA = 0 °C - 6 - TA = -10 °C - 10 - TA = -20 °C - 17 - TA = -30 °C - 32 - TA = -40 °C - 60 - tSU(LSE)(3) Startup time VDD is stabilized s 1. Guaranteed by characterization results, not tested in production. 2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for ST microcontrollers”. 3. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer DocID14610 Rev 9 55/121 120 Electrical characteristics STM32F101xC, STM32F101xD, STM32F101xE Note: For CL1 and CL2, it is recommended to use high-quality ceramic capacitors in the 5 pF to 15 pF range selected to match the requirements of the crystal or resonator. CL1 and CL2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. Load capacitance CL has the following formula: CL = CL1 x CL2 / (CL1 + CL2) + Cstray where Cstray is the pin capacitance and board or trace PCB-related capacitance. Typically, it is between 2 pF and 7 pF. Caution: To avoid exceeding the maximum value of CL1 and CL2 (15 pF) it is strongly recommended to use a resonator with a load capacitance CL ≤ 7 pF. Never use a resonator with a load capacitance of 12.5 pF. Example: if you choose a resonator with a load capacitance of CL = 6 pF, and Cstray = 2 pF, then CL1 = CL2 = 8 pF. Figure 20. Typical application with a 32.768 kHz crystal 5HVRQDWRUZLWK LQWHJUDWHGFDSDFLWRUV &/ I/6( 26&B,1 .+ ] UHVRQDWRU 5) %LDV FRQWUROOHG JDLQ 670)[[[ 26&B28 7 &/ DLE 5.3.7 Internal clock source characteristics The parameters given in Table 25 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 10. High-speed internal (HSI) RC oscillator Table 25. HSI oscillator characteristics(1) Symbol Parameter Conditions Typ Max Unit Frequency - - 8 - MHz DuCy(HSI) Duty cycle - 45 - 55 % - - 1(3) % –2 - 2.5 % –1.5 - 2.2 % –1.3 - 2 % –1.1 - 1.8 % fHSI User-trimmed with the RCC_CR register(2) ACCHSI Accuracy of the HSI oscillator TA = –40 to 105 °C TA = –10 to 85 °C Factory(4) calibrated TA = 0 to 70 °C TA = 25 °C tsu(HSI)(4) HSI oscillator startup time - 1 - 2 µs IDD(HSI)(4) HSI oscillator power consumption - - 80 100 µA 1. VDD = 3.3 V, TA = –40 to 85 °C unless otherwise specified. 56/121 Min DocID14610 Rev 9 STM32F101xC, STM32F101xD, STM32F101xE Electrical characteristics 2. Refer to application note AN2868 “STM32F10xxx internal RC oscillator (HSI) calibration” available from the ST website www.st.com 3. Guaranteed by design, not tested in production. 4. Guaranteed by characterization results, not tested in production. Low-speed internal (LSI) RC oscillator Table 26. LSI oscillator characteristics (1) Symbol fLSI(2) tsu(LSI) (3) IDD(LSI)(3) Parameter Min Typ Max Unit 30 40 60 kHz LSI oscillator startup time - - 85 µs LSI oscillator power consumption - 0.65 1.2 µA Frequency 1. VDD = 3 V, TA = –40 to 85 °C unless otherwise specified. 2. Guaranteed by characterization results, not tested in production. 3. Guaranteed by design, not tested in production. Wakeup time from low-power mode The wakeup times given in Table 27 are measured on a wakeup phase with an 8-MHz HSI RC oscillator. The clock source used to wake up the device depends from the current operating mode: • Stop or Standby mode: the clock source is the RC oscillator • Sleep mode: the clock source is the clock that was set before entering Sleep mode. All timings are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 10. Table 27. Low-power mode wakeup timings Symbol tWUSLEEP(1) tWUSTOP(1) tWUSTDBY(1) Parameter Typ Unit Wakeup from Sleep mode 1.8 µs Wakeup from Stop mode (regulator in run mode) 3.6 Wakeup from Stop mode (regulator in low-power mode) 5.4 Wakeup from Standby mode 50 µs µs 1. The wakeup times are measured from the wakeup event to the point at which the user application code reads the first instruction. DocID14610 Rev 9 57/121 120 Electrical characteristics 5.3.8 STM32F101xC, STM32F101xD, STM32F101xE PLL characteristics The parameters given in Table 28 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 10. Table 28. PLL characteristics Value Symbol Parameter Unit Min(1) Typ Max(1) PLL input clock(2) 1 8.0 25 MHz PLL input clock duty cycle 40 - 60 % fPLL_OUT PLL multiplier output clock 16 - 36 MHz tLOCK PLL lock time - - 200 µs Jitter Cycle-to-cycle jitter - - 300 ps fPLL_IN 1. Guaranteed by characterization results, not tested in production. 2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with the range defined by fPLL_OUT. 5.3.9 Memory characteristics Flash memory The characteristics are given at TA = –40 to 85 °C unless otherwise specified. Table 29. Flash memory characteristics Symbol Parameter Conditions Min Typ Max(1) Unit tprog 16-bit programming time TA = –40 to +85 °C 40 52.5 70 µs tERASE Page (2 KB) erase time TA = –40 to +85 °C 20 - 40 ms Mass erase time TA = –40 to +85 °C 20 - 40 ms Read mode fHCLK = 36 MHz with 1 wait state, VDD = 3.3 V - - 28 mA Write mode fHCLK = 36 MHz, VDD = 3.3 V - - 7 mA Erase mode fHCLK = 36 MHz, VDD = 3.3 V - - 5 mA Power-down mode / Halt, VDD = 3.0 to 3.6 V - - 50 µA 2 - 3.6 V tME IDD Vprog Supply current Programming voltage 1. Guaranteed by design, not tested in production. 58/121 DocID14610 Rev 9 STM32F101xC, STM32F101xD, STM32F101xE Electrical characteristics Table 30. Flash memory endurance and data retention Value Symbol NEND Parameter Endurance Conditions TA = –40 °C to 85 °C (2) tRET Data retention Min(1) 10 TA = 85 °C, 1 kcycle 30 TA = 55 °C, 10 kcycle(2) 20 Unit kcycles Years 1. Guaranteed by characterization results, not tested in production. 2. Cycling performed over the whole temperature range. 5.3.10 FSMC characteristics Asynchronous waveforms and timings Figure 21 through Figure 24 represent asynchronous waveforms and Table 31 through Table 34 provide the corresponding timings. The results shown in these tables are obtained with the following FSMC configuration: • AddressSetupTime = 0 • AddressHoldTime = 1 • DataSetupTime = 1 DocID14610 Rev 9 59/121 120 Electrical characteristics STM32F101xC, STM32F101xD, STM32F101xE Figure 21. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms WZ1( )60&B1( W Y12(B1( W Z12( W K1(B12( )60&B12( )60&B1:( WY$B1( )60&B$>@ W K$B12( $GGUHVV WY%/B1( W K%/B12( )60&B1%/>@ W K'DWDB1( W VX'DWDB12( WK'DWDB12( W VX'DWDB1( 'DWD )60&B'>@ W Y1$'9B1( WZ1$'9 )60&B1$'9 069 1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used. Note: FSMC_BusTurnAroundDuration = 0. Table 31. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1) (2) Symbol Parameter Max Unit 5tHCLK – 1.5 5tHCLK + 2 ns 0.5 1.5 ns 5tHCLK – 1.5 5tHCLK + 1.5 ns –1.5 - ns - 7 ns 0.1 - ns tw(NE) FSMC_NE low time tv(NOE_NE) FSMC_NEx low to FSMC_NOE low tw(NOE) FSMC_NOE low time th(NE_NOE) FSMC_NOE high to FSMC_NE high hold time tv(A_NE) FSMC_NEx low to FSMC_A valid th(A_NOE) Address hold time after FSMC_NOE high tv(BL_NE) FSMC_NEx low to FSMC_BL valid - 0 ns th(BL_NOE) FSMC_BL hold time after FSMC_NOE high 0 - ns tsu(Data_NE) Data to FSMC_NEx high setup time 2tHCLK + 25 - ns 2tHCLK + 25 - ns 0 - ns tsu(Data_NOE) Data to FSMC_NOEx high setup time th(Data_NOE) 60/121 Min Data hold time after FSMC_NOE high DocID14610 Rev 9 STM32F101xC, STM32F101xD, STM32F101xE Electrical characteristics Table 31. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1) (2) Symbol Parameter Min Max Unit th(Data_NE) Data hold time after FSMC_NEx high 0 - ns tv(NADV_NE) FSMC_NEx low to FSMC_NADV low - 5 ns tw(NADV) FSMC_NADV low time - tHCLK + 1.5 ns 1. CL = 15 pF. 2. Guaranteed by characterization results, not tested in production. Figure 22. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms WZ1( )60&B1([ )60&B12( WY1:(B1( WZ1:( W K1(B1:( )60&B1:( WK$B1:( WY$B1( )60&B$>@ $GGUHVV WY%/B1( )60&B1%/>@ WK%/B1:( 1%/ WY'DWDB1( WK'DWDB1:( 'DWD )60&B'>@ W Y1$'9B1( WZ1$'9 )60&B1$'9 DL 1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used. Table 32. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)(2) Symbol Parameter Min Max Unit tw(NE) FSMC_NE low time 3tHCLK – 1 3tHCLK + 2 ns tv(NWE_NE) FSMC_NEx low to FSMC_NWE low tHCLK – 0.5 tHCLK + 1.5 ns tw(NWE) FSMC_NWE low time tHCLK – 0.5 tHCLK + 1.5 ns th(NE_NWE) FSMC_NWE high to FSMC_NE high hold time tHCLK - ns tv(A_NE) FSMC_NEx low to FSMC_A valid - 7.5 ns th(A_NWE) Address hold time after FSMC_NWE high tHCLK - ns tv(BL_NE) FSMC_NEx low to FSMC_BL valid - 1.5 ns th(BL_NWE) FSMC_BL hold time after FSMC_NWE high tHCLK – 0.5 - ns tv(Data_NE) FSMC_NEx low to Data valid - tHCLK + 7 ns DocID14610 Rev 9 61/121 120 Electrical characteristics STM32F101xC, STM32F101xD, STM32F101xE Table 32. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)(2) Symbol Parameter Min Max Unit th(Data_NWE) Data hold time after FSMC_NWE high tHCLK - ns tv(NADV_NE) FSMC_NEx low to FSMC_NADV low - 5.5 ns tw(NADV) FSMC_NADV low time - tHCLK + 1.5 ns 1. CL = 15 pF. 2. Guaranteed by characterization results, not tested in production. Figure 23. Asynchronous multiplexed NOR/PSRAM read waveforms TW.% &3-#?.% TV./%?.% T H.%?./% &3-#?./% T W./% &3-#?.7% TV!?.% &3-#?!;= T H!?./% !DDRESS TV",?.% TH",?./% &3-#?.",;= .", TH$ATA?.% TSU$ATA?.% T V!?.% &3-#? !$;= TSU$ATA?./% !DDRESS T V.!$6?.% TH$ATA?./% $ATA TH!$?.!$6 TW.!$6 &3-#?.!$6 AIB Table 33. Asynchronous multiplexed NOR/PSRAM read timings(1)(2) Symbol 62/121 Parameter Min Max Unit 7tHCLK – 2 7tHCLK + 2 ns 3tHCLK – 0.5 3tHCLK + 1.5 ns 4tHCLK – 1 4tHCLK + 2 ns –1 - ns tw(NE) FSMC_NE low time tv(NOE_NE) FSMC_NEx low to FSMC_NOE low tw(NOE) FSMC_NOE low time th(NE_NOE) FSMC_NOE high to FSMC_NE high hold time tv(A_NE) FSMC_NEx low to FSMC_A valid - 0 ns tv(NADV_NE) FSMC_NEx low to FSMC_NADV low 3 5 ns tw(NADV) FSMC_NADV low time tHCLK –1.5 tHCLK + 1.5 ns th(AD_NADV) FSMC_AD (address) valid hold time after FSMC_NADV high tHCLK - ns DocID14610 Rev 9 STM32F101xC, STM32F101xD, STM32F101xE Electrical characteristics Table 33. Asynchronous multiplexed NOR/PSRAM read timings(1)(2) (continued) Symbol Parameter Min Max Unit tHCLK - ns th(A_NOE) Address hold time after FSMC_NOE high th(BL_NOE) FSMC_BL hold time after FSMC_NOE high 0 - ns tv(BL_NE) FSMC_NEx low to FSMC_BL valid - 0 ns tsu(Data_NE) Data to FSMC_NEx high setup time 2tHCLK + 24 - ns tsu(Data_NOE) Data to FSMC_NOE high setup time 2tHCLK + 25 - ns th(Data_NE) Data hold time after FSMC_NEx high 0 - ns th(Data_NOE) Data hold time after FSMC_NOE high 0 - ns 1. CL = 15 pF. 2. Guaranteed by characterization results, not tested in production. DocID14610 Rev 9 63/121 120 Electrical characteristics STM32F101xC, STM32F101xD, STM32F101xE Figure 24. Asynchronous multiplexed NOR/PSRAM write waveforms WZ1( )60&B1([ )60&B12( WY1:(B1( WZ1:( W K1(B1:( )60&B1:( WK$B1:( WY$B1( )60&B$>@ $GGUHVV WY%/B1( WK%/B1:( )60&B1%/>@ 1%/ W Y$B1( )60&B$'>@ W Y'DWDB1$'9 $GGUHVV W Y1$'9B1( WK'DWDB1:( 'DWD WK$'B1$'9 WZ1$'9 )60&B1$'9 DL% Table 34. Asynchronous multiplexed NOR/PSRAM write timings(1)(2) Symbol Parameter Max Unit 5tHCLK – 1 5tHCLK + 2 ns 1tHCLK 1tHCLK + 1 ns tw(NE) FSMC_NE low time tv(NWE_NE) FSMC_NEx low to FSMC_NWE low tw(NWE) FSMC_NWE low time 3tHCLK – 1 2 ns th(NE_NWE) FSMC_NWE high to FSMC_NE high hold time tHCLK – 1 - ns tv(A_NE) FSMC_NEx low to FSMC_A valid - 7 ns tv(NADV_NE) FSMC_NEx low to FSMC_NADV low 3 5 ns tw(NADV) FSMC_NADV low time tHCLK – 1 tHCLK + 1 ns th(AD_NADV) FSMC_AD (address) valid hold time after FSMC_NADV high tHCLK – 3 - ns th(A_NWE) Address hold time after FSMC_NWE high 1tHCLK - ns tv(BL_NE) FSMC_NEx low to FSMC_BL valid - 1.6 ns th(BL_NWE) FSMC_BL hold time after FSMC_NWE high tHCLK – 1.5 - ns - tHCLK + 1.5 ns tHCLK – 5 - ns tv(Data_NADV) FSMC_NADV high to Data valid th(Data_NWE) Data hold time after FSMC_NWE high 1. CL = 15 pF. 2. Guaranteed by characterization results, not tested in production.. 64/121 Min DocID14610 Rev 9 STM32F101xC, STM32F101xD, STM32F101xE Electrical characteristics Synchronous waveforms and timings Figure 25 through Figure 28 represent synchronous waveforms and Table 36 through Table 38 provide the corresponding timings. The results shown in these tables are obtained with the following FSMC configuration: • BurstAccessMode = FSMC_BurstAccessMode_Enable; • MemoryType = FSMC_MemoryType_CRAM; • WriteBurst = FSMC_WriteBurst_Enable; • CLKDivision = 1; (0 is not supported, see the STM32F10xxx reference manual) • DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM Figure 25. Synchronous multiplexed NOR/PSRAM read timings %867851  WZ&/. WZ&/. )60&B&/. 'DWDODWHQF\  WG&/./1([/ W G&/./1([+ )60&B1([ WG&/./1$'9/ WG&/./1$'9+ )60&B1$'9 WG&/./$,9 WG&/./$9 )60&B$>@ WG&/.+12(/ WG&/./12(+ )60&B12( WG&/./$'9 WG&/./$',9 WVX$'9&/.+ )60&B$'>@ $'>@ WK&/.+$'9 WVX$'9&/.+ ' WVX1:$,79&/.+ WK&/.+$'9 ' WK&/.+1:$,79 )60&B1:$,7 :$,7&)* E:$,732/E WVX1:$,79&/.+ WK&/.+1:$,79 )60&B1:$,7 :$,7&)* E:$,732/E WVX1:$,79&/.+ WK&/.+1:$,79 DLK DocID14610 Rev 9 65/121 120 Electrical characteristics STM32F101xC, STM32F101xD, STM32F101xE Table 35. Synchronous multiplexed NOR/PSRAM read timings(1)(2) Symbol Parameter Max Unit 55.5 - ns tw(CLK) FSMC_CLK period td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x = 0...2) - 1.5 ns td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x = 0...2) 2 - ns td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low - 4 ns td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high 5 - ns td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x = 16...25) - 0 ns td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x = 16...25) 2 - ns td(CLKH-NOEL) FSMC_CLK high to FSMC_NOE low - 1 ns td(CLKL-NOEH) FSMC_CLK low to FSMC_NOE high 0.5 - ns td(CLKL-ADV) FSMC_CLK low to FSMC_AD[15:0] valid - 12 ns td(CLKL-ADIV) FSMC_CLK low to FSMC_AD[15:0] invalid 0 - ns tsu(ADV-CLKH) FSMC_A/D[15:0] valid data before FSMC_CLK high 6 - ns th(CLKH-ADV) FSMC_A/D[15:0] valid data after FSMC_CLK high 0 - ns 8 - ns 2 - ns tsu(NWAITV-CLKH) FSMC_NWAIT valid before FSMC_CLK high th(CLKH-NWAITV) FSMC_NWAIT valid after FSMC_CLK high 1. CL = 15 pF. 2. Guaranteed by characterization results, not tested in production.. 66/121 Min DocID14610 Rev 9 STM32F101xC, STM32F101xD, STM32F101xE Electrical characteristics Figure 26. Synchronous multiplexed PSRAM write timings "53452. TW#,+ TW#,+ &3-#?#,+ $ATALATENCY TD#,+, .%X, TD#,+, .%X( &3-#?.%X TD#,+, .!$6, TD#,+, .!$6( &3-#?.!$6 TD#,+, !6 TD#,+, !)6 &3-#?!;= TD#,+, .7%, TD#,+, .7%( &3-#?.7% TD#,+, !$)6 TD#,+, !$6 &3-#?!$;= TD#,+, $ATA TD#,+, $ATA !$;= $ $ &3-#?.7!)4 7!)4#&'B7!)40/,B TSU.7!)46 #,+( TH#,+( .7!)46 TD#,+, .",( &3-#?.", AIG DocID14610 Rev 9 67/121 120 Electrical characteristics STM32F101xC, STM32F101xD, STM32F101xE Table 36. Synchronous multiplexed PSRAM write timings(1)(2) Symbol Parameter Max Unit 55.5 - ns tw(CLK) FSMC_CLK period td(CLKL-NExL) FSMC_CLK low to FSMC_Nex low (x = 0...2) - 2 ns td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x = 0...2) 2 - ns td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low - 4 ns td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high 5 - ns td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x = 16...25) - 0 ns td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x = 16...25) 2 - ns td(CLKL-NWEL) FSMC_CLK low to FSMC_NWE low - 1 ns td(CLKL-NWEH) FSMC_CLK low to FSMC_NWE high 1 - ns td(CLKL-ADV) FSMC_CLK low to FSMC_AD[15:0] valid - 12 ns td(CLKL-ADIV) FSMC_CLK low to FSMC_AD[15:0] invalid 3 - ns td(CLKL-Data) FSMC_A/D[15:0] valid after FSMC_CLK low - 6 ns tsu(NWAITV-CLKH) FSMC_NWAIT valid before FSMC_CLK high 7 - ns th(CLKH-NWAITV) FSMC_NWAIT valid after FSMC_CLK high 2 - ns td(CLKL-NBLH) FSMC_CLK low to FSMC_NBL high 1 - ns 1. CL = 15 pF. 2. Guaranteed by characterization results, not tested in production. 68/121 Min DocID14610 Rev 9 STM32F101xC, STM32F101xD, STM32F101xE Electrical characteristics Figure 27. Synchronous non-multiplexed NOR/PSRAM read timings "53452. TW#,+ TW#,+ &3-#?#,+ TD#,+, .%X, TD#,+, .%X( $ATALATENCY &3-#?.%X TD#,+, .!$6, TD#,+, .!$6( &3-#?.!$6 TD#,+, !)6 TD#,+, !6 &3-#?!;= TD#,+( ./%, TD#,+, ./%( &3-#?./% TSU$6 #,+( TH#,+( $6 TSU$6 #,+( &3-#?$;= $ TSU.7!)46 #,+( TH#,+( $6 $ $ TH#,+( .7!)46 &3-#?.7!)4 7!)4#&'B7!)40/,B TSU.7!)46 #,+( T H#,+( .7!)46 &3-#?.7!)4 7!)4#&'B7!)40/,B TSU.7!)46 #,+( TH#,+( .7!)46 AIG Table 37. Synchronous non-multiplexed NOR/PSRAM read timings(1)(2) Symbol Parameter Min Max Unit 55.5 - ns tw(CLK) FSMC_CLK period td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x = 0...2) - 1.5 ns td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x = 0...2) 2 - ns td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low - 4 ns td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high 5 - ns td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x = 0...25) - 0 ns td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x = 0...25) 4 - ns td(CLKH-NOEL) FSMC_CLK high to FSMC_NOE low - 1.5 ns td(CLKL-NOEH) FSMC_CLK low to FSMC_NOE high 1.5 - ns tsu(DV-CLKH) FSMC_D[15:0] valid data before FSMC_CLK high 6.5 - ns th(CLKH-DV) FSMC_D[15:0] valid data after FSMC_CLK high 7 - ns tsu(NWAITV-CLKH) FSMC_NWAIT valid before FSMC_SMCLK high 7 - ns th(CLKH-NWAITV) 2 - ns FSMC_NWAIT valid after FSMC_CLK high 1. CL = 15 pF. DocID14610 Rev 9 69/121 120 Electrical characteristics STM32F101xC, STM32F101xD, STM32F101xE 2. Guaranteed by characterization results, not tested in production. Figure 28. Synchronous non-multiplexed PSRAM write timings %867851  WZ&/. WZ&/. )60&B&/. 'DWDODWHQF\  WG&/./1([/ W G&/./1([+ )60&B1([ WG&/./1$'9/ WG&/./1$'9+ )60&B1$'9 WG&/./$,9 WG&/./$9 )60&B$>@ WG&/.+12(/ WG&/./12(+ )60&B12( WG&/./$'9 WG&/./$',9 WVX$'9&/.+ )60&B$'>@ $'>@ WK&/.+$'9 WVX$'9&/.+ ' WVX1:$,79&/.+ WK&/.+$'9 ' WK&/.+1:$,79 )60&B1:$,7 :$,7&)* E:$,732/E WVX1:$,79&/.+ WK&/.+1:$,79 )60&B1:$,7 :$,7&)* E:$,732/E WVX1:$,79&/.+ WK&/.+1:$,79 DLK Table 38. Synchronous non-multiplexed PSRAM write timings(1)(2) Symbol 70/121 Parameter Min Max Unit 55.5 - ns tw(CLK) FSMC_CLK period td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x = 0...2) - 2 ns td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x = 0...2) 2 - ns td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low - 4 ns td(CLKL-NADVH) FSMC_CLK low to FSMC_NADV high 5 - ns td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x = 16...25) - 0 ns td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x = 16...25) 2 - ns td(CLKL-NWEL) FSMC_CLK low to FSMC_NWE low - 1 ns td(CLKL-NWEH) FSMC_CLK low to FSMC_NWE high 1 - ns td(CLKL-Data) FSMC_D[15:0] valid data after FSMC_CLK low - 6 ns tsu(NWAITV-CLKH) FSMC_NWAIT valid before FSMC_CLK high 7 - ns DocID14610 Rev 9 STM32F101xC, STM32F101xD, STM32F101xE Electrical characteristics Table 38. Synchronous non-multiplexed PSRAM write timings(1)(2) (continued) Symbol Parameter Min Max Unit th(CLKH-NWAITV) FSMC_NWAIT valid after FSMC_CLK high 2 - ns td(CLKL-NBLH) FSMC_CLK low to FSMC_NBL high 1 - ns 1. CL = 15 pF. 2. Guaranteed by characterization results, not tested in production. PC Card/CompactFlash controller waveforms and timings Figure 29 through Figure 34 represent synchronous waveforms and Table 39 provides the corresponding timings. The results shown in this table are obtained with the following FSMC configuration: • COM.FSMC_SetupTime = 0x04; • COM.FSMC_WaitSetupTime = 0x07; • COM.FSMC_HoldSetupTime = 0x04; • COM.FSMC_HiZSetupTime = 0x00; • ATT.FSMC_SetupTime = 0x04; • ATT.FSMC_WaitSetupTime = 0x07; • ATT.FSMC_HoldSetupTime = 0x04; • ATT.FSMC_HiZSetupTime = 0x00; • IO.FSMC_SetupTime = 0x04; • IO.FSMC_WaitSetupTime = 0x07; • IO.FSMC_HoldSetupTime = 0x04; • IO.FSMC_HiZSetupTime = 0x00; • TCLRSetupTime = 0; • TARSetupTime = 0; DocID14610 Rev 9 71/121 120 Electrical characteristics STM32F101xC, STM32F101xD, STM32F101xE Figure 29. PC Card/CompactFlash controller waveforms for common memory read access )60&B1&(B )60&B1&(B WK1&([$, WY1&([$ )60&B$>@ WK1&([15(* WK1&([1,25' WK1&([1,2:5 WG15(*1&([ WG1,25'1&([ )60&B15(* )60&B1,2:5 )60&B1,25' )60&B1:( WG1&(B12( )60&B12( WZ12( WVX'12( WK12(' )60&B'>@ DLE 1. FSMC_NCE4_2 remains high (inactive during 8-bit access. Figure 30. PC Card/CompactFlash controller waveforms for common memory write access )60&B1&(B )60&B1&(B +LJK WY1&(B$ WK1&(B$, )60&B$>@ WK1&(B15(* WK1&(B1,25' WK1&(B1,2:5 WG15(*1&(B WG1,25'1&(B )60&B15(* )60&B1,2:5 )60&B1,25' WG1&(B1:( WZ1:( WG1:(1&(B )60&B1:( )60&B12( 0(0[+,=  WG'1:( WY1:(' WK1:(' )60&B'>@ DLE 72/121 DocID14610 Rev 9 STM32F101xC, STM32F101xD, STM32F101xE Electrical characteristics Figure 31. PC Card/CompactFlash controller waveforms for attribute memory read access )60&B1&(B WY1&(B$ WK1&(B$, )60&B1&(B +LJK )60&B$>@ )60&B1,2:5 )60&B1,25' WG15(*1&(B WK1&(B15(* )60&B15(* )60&B1:( WG1&(B12( WZ12( WG12(1&(B )60&B12( WVX'12( WK12(' )60&B'>@ DLE 1. Only data bits 0...7 are read (bits 8...15 are disregarded). DocID14610 Rev 9 73/121 120 Electrical characteristics STM32F101xC, STM32F101xD, STM32F101xE Figure 32. PC Card/CompactFlash controller waveforms for attribute memory write access )60&B1&(B )60&B1&(B +LJK WY1&(B$ WK1&(B$, )60&B$>@ )60&B1,2:5 )60&B1,25' WG15(*1&(B WK1&(B15(* )60&B15(* WG1&(B1:( WZ1:( )60&B1:( WG1:(1&(B )60&B12( WY1:(' )60&B'>@ DLE 1. Only data bits 0...7 are driven (bits 8...15 remains HiZ). Figure 33. PC Card/CompactFlash controller waveforms for I/O space read access )60&B1&(B )60&B1&(B WK1&(B$, WY1&([$ )60&B$>@ )60&B15(* )60&B1:( )60&B12( )60&B1,2:5 WZ1,25' WG1,25'1&(B )60&B1,25' WVX'1,25' WG1,25'' )60&B'>@ DL% 74/121 DocID14610 Rev 9 STM32F101xC, STM32F101xD, STM32F101xE Electrical characteristics Figure 34. PC Card/CompactFlash controller waveforms for I/O space write access )60&B1,2:5 WY1&([$ WK1&(B$, )60&B$>@ )60&B15(* )60&B1:( )60&B12( )60&B1,25' WG1&(B1,2:5 WZ1,2:5 )60&B1,2:5 $77[+,=  WY1,2:5' WK1,2:5' )60&B'>@ DLE Table 39. Switching characteristics for PC Card/CF read and write cycles(1)(2) Symbol Parameter Min Max Unit tv(NCEx-A) tv(NCE4_1-A) FSMC_NCEx low (x = 4_1/4_2) to FSMC_Ay valid (y = 0...10) FSMC_NCE4_1 low (x = 4_1/4_2) to FSMC_Ay valid (y = 0...10) - 0 ns th(NCEx-AI) th(NCE4_1-AI) FSMC_NCEx high (x = 4_1/4_2) to FSMC_Ax invalid (x = 0...10) FSMC_NCE4_1 high (x = 4_1/4_2) to FSMC_Ax invalid (x = 0...10) 2.5 - ns td(NREG-NCEx) td(NREG-NCE4_1) FSMC_NCEx low to FSMC_NREG valid FSMC_NCE4_1 low to FSMC_NREG valid - 5 ns th(NCEx-NREG) th(NCE4_1-NREG) FSMC_NCEx high to FSMC_NREG invalid FSMC_NCE4_1 high to FSMC_NREG invalid tHCLK + 3 - ns td(NCE4_1-NOE) FSMC_NCE4_1 low to FSMC_NOE low - 5tHCLK + 2 ns tw(NOE) FSMC_NOE low width 8tHCLK –1.5 8tHCLK + 1 ns td(NOE-NCE4_1 FSMC_NOE high to FSMC_NCE4_1 high 5tHCLK + 2 - ns tsu(D-NOE) FSMC_D[15:0] valid data before FSMC_NOE high 25 - ns th(NOE-D) FSMC_D[15:0] valid data after FSMC_NOE high 15 - ns tw(NWE) FSMC_NWE low width 8tHCLK – 1 8tHCLK + 2 ns td(NWE-NCE4_1) FSMC_NWE high to FSMC_NCE4_1 high 5tHCLK + 2 - ns td(NCE4_1-NWE) FSMC_NCE4_1 low to FSMC_NWE low - 5tHCLK + 1.5 ns tv(NWE-D) FSMC_NWE low to FSMC_D[15:0] valid - 0 ns th(NWE-D) FSMC_NWE high to FSMC_D[15:0] invalid 11tHCLK - ns DocID14610 Rev 9 75/121 120 Electrical characteristics STM32F101xC, STM32F101xD, STM32F101xE Table 39. Switching characteristics for PC Card/CF read and write cycles(1)(2) (continued) Symbol Parameter td(D-NWE) FSMC_D[15:0] valid before FSMC_NWE high tw(NIOWR) FSMC_NIOWR low width tv(NIOWR-D) FSMC_NIOWR low to FSMC_D[15:0] valid th(NIOWR-D) FSMC_NIOWR high to FSMC_D[15:0] invalid td(NCE4_1-NIOWR) FSMC_NCE4_1 low to FSMC_NIOWR valid FSMC_NCEx high to FSMC_NIOWR invalid th(NCEx-NIOWR) th(NCE4_1-NIOWR) FSMC_NCE4_1 high to FSMC_NIOWR invalid td(NIORD-NCEx) FSMC_NCEx low to FSMC_NIORD valid td(NIORD-NCE4_1) FSMC_NCE4_1 low to FSMC_NIORD valid th(NCEx-NIORD) FSMC_NCEx high to FSMC_NIORD invalid th(NCE4_1-NIORD) FSMC_NCE4_1 high to FSMC_NIORD invalid tsu(D-NIORD) FSMC_D[15:0] valid before FSMC_NIORD high td(NIORD-D) FSMC_D[15:0] valid after FSMC_NIORD high tw(NIORD) FSMC_NIORD low width Min Max Unit 13tHCLK - ns 8tHCLK + 3 - ns - 5tHCLK +1 ns 11tHCLK - ns - 5tHCLK+3ns ns 5tHCLK – 5 - ns - 5tHCLK + 2.5 ns 5tHCLK – 5 - ns 4.5 - ns 9 - ns 8tHCLK + 2 - ns 1. CL = 15 pF. 2. Guaranteed by characterization results, not tested in production. NAND controller waveforms and timings Figure 35 through Figure 38 represent synchronous waveforms and Table 40 provides the corresponding timings. The results shown in this table are obtained with the following FSMC configuration: 76/121 • COM.FSMC_SetupTime = 0x01; • COM.FSMC_WaitSetupTime = 0x03; • COM.FSMC_HoldSetupTime = 0x02; • COM.FSMC_HiZSetupTime = 0x01; • ATT.FSMC_SetupTime = 0x01; • ATT.FSMC_WaitSetupTime = 0x03; • ATT.FSMC_HoldSetupTime = 0x02; • ATT.FSMC_HiZSetupTime = 0x01; • Bank = FSMC_Bank_NAND; • MemoryDataWidth = FSMC_MemoryDataWidth_16b; • ECC = FSMC_ECC_Enable; • ECCPageSize = FSMC_ECCPageSize_512Bytes; • TCLRSetupTime = 0; • TARSetupTime = 0; DocID14610 Rev 9 STM32F101xC, STM32F101xD, STM32F101xE Electrical characteristics Figure 35. NAND controller waveforms for read access )60&B1&([ /RZ $/()60&B$ &/()60&B$ )60&B1:( WK12($/( WG$/(12( )60&B12(15( WVX'12( WK12(' )60&B'>@ DLE Figure 36. NAND controller waveforms for write access )60&B1&([ /RZ $/()60&B$ &/()60&B$ WG$/(1:( WK1:($/( )60&B1:( )60&B12(15( WY1:(' WK1:(' )60&B'>@ DLE Figure 37. NAND controller waveforms for common memory read access )60&B1&([ /RZ $/()60&B$ &/()60&B$ WG$/(12( WK12($/( )60&B1:( WZ12( )60&B12( WVX'12( WK12(' )60&B'>@ DLE DocID14610 Rev 9 77/121 120 Electrical characteristics STM32F101xC, STM32F101xD, STM32F101xE Figure 38. NAND controller waveforms for common memory write access )60&B1&([ /RZ $/()60&B$ &/()60&B$ WG$/(1:( WZ1:( WK1:($/( )60&B1:( )60&B12( WG'1:( WY1:(' WK1:(' )60&B'>@ DLE Table 40. Switching characteristics for NAND Flash read and write cycles(1) Symbol Parameter td(D-NWE)(2) tw(NOE) (2) Min Max FSMC_D[15:0] valid before FSMC_NWE high 5tHCLK + 12 - ns FSMC_NOE low width 4tHCLK – 1.5 4tHCLK + 1.5 ns tsu(D-NOE)(2) FSMC_D[15:0] valid data before FSMC_NOE high 25 - ns th(NOE-D)(2) FSMC_D[15:0] valid data after FSMC_NOE high 7 - ns 4tHCLK – 1 4tHCLK + 2.5 ns - 0 ns tw(NWE) (2) FSMC_NWE low width tv(NWE-D)(2) th(NWE-D) (2) td(ALE-NWE) FSMC_NWE low to FSMC_D[15:0] valid FSMC_NWE high to FSMC_D[15:0] invalid 2tHCLK + 4ns - ns (3) FSMC_ALE valid before FSMC_NWE low - 3tHCLK + 1.5 ns (3) FSMC_NWE high to FSMC_ALE invalid 3tHCLK + 4.5 - ns - 3tHCLK + 2 ns 3tHCLK + 4.5 - ns th(NWE-ALE) td(ALE-NOE)(3) FSMC_ALE valid before FSMC_NOE low th(NOE-ALE) (3) FSMC_NWE high to FSMC_ALE invalid 1. CL = 15 pF. 2. Guaranteed by characterization results, not tested in production. 3. Guaranteed by design, not tested in production. 5.3.11 EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. 78/121 Unit DocID14610 Rev 9 STM32F101xC, STM32F101xD, STM32F101xE Electrical characteristics Functional EMS (Electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports), the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs: • Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard. • FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard. A device reset allows normal operations to be resumed. The test results are given in Table 41. They are based on the EMS levels and classes defined in application note AN1709. Table 41. EMS characteristics Symbol Parameter Conditions Level/Class VFESD VDD = 3.3 V, LQFP144, Voltage limits to be applied on any I/O pin to TA = +25 °C, fHCLK= 36 MHz induce a functional disturbance conforms to IEC 61000-4-2 2B VEFTB Fast transient voltage burst limits to be applied through 100 pF on VDD and VSS pins to induce a functional disturbance VDD = 3.3 V, LQFP144, TA = +25 °C, fHCLK = 36 MHz conforms to IEC 61000-4-4 4A Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and pre qualification tests in relation with the EMC level requested for his application. Software recommendations The software flowchart must include the management of runaway conditions such as: • Corrupted program counter • Unexpected reset • Critical Data corruption (control registers...) Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). DocID14610 Rev 9 79/121 120 Electrical characteristics STM32F101xC, STM32F101xD, STM32F101xE Electromagnetic Interference (EMI) The electromagnetic field emitted by the device is monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with IEC 61967-2 standard which specifies the test board and the pin loading. Table 42. EMI characteristics Symbol Parameter SEMI 5.3.12 Peak level Conditions Max vs. [fHSE/fHCLK] Monitored frequency band Unit 8/36 MHz 0.1 MHz to 30 MHz VDD = 3.3 V, TA = 25 °C, 30 MHz to 130 MHz LQFP144 package compliant with 130 MHz to 1 GHz IEC 61967-2 SAE EMI Level 8 27 dBµV 26 4 - Absolute maximum ratings (electrical sensitivity) Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the JESD22-A114/JESD22-C101 standard. Table 43. ESD absolute maximum ratings Class Maximum value(1) Electrostatic discharge TA = +25 °C, conforming voltage (human body model) to JESD22-A114 2 2000 Electrostatic discharge TA = +25 °C, conforming VESD(CDM) voltage (charge device model) to JESD22-C101 III Symbol VESD(HBM) Ratings Conditions Unit V 500 1. Guaranteed by characterization results, not tested in production. Static latch-up Two complementary static tests are required on six parts to assess the latch-up performance: • A supply overvoltage is applied to each power supply pin • A current injection is applied to each input, output and configurable I/O pin These tests are compliant with EIA/JESD 78 IC latch-up standard. Table 44. Electrical sensitivities Symbol LU 80/121 Parameter Static latch-up class Conditions TA = +85 °C conforming to JESD78A DocID14610 Rev 9 Class II level A STM32F101xC, STM32F101xD, STM32F101xE 5.3.13 Electrical characteristics I/O current injection characteristics As a general rule, current injection to the I/O pins, due to external voltage below VSS or above VDD (for standard, 3 V-capable I/O pins) should be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization. Functional susceptibilty to I/O current injection While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures. The failure is indicated by an out of range parameter: ADC error above a certain limit (>5 LSB TUE), out of spec current injection on adjacent pins or other functional failure (for example reset, oscillator frequency deviation). The test results are given in Table 45 Table 45. I/O current injection susceptibility Functional susceptibility Symbol IINJ Description Negative injection Positive injection Injected current on OSC_IN32, OSC_OUT32, PA4, PA5, PC13 -0 +0 Injected current on all FT pins -5 +0 Injected current on any other pin -5 +5 DocID14610 Rev 9 Unit mA 81/121 120 Electrical characteristics 5.3.14 STM32F101xC, STM32F101xD, STM32F101xE I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 46 are derived from tests performed under the conditions summarized in Table 10. All I/Os are CMOS and TTL compliant. Table 46. I/O static characteristics Symbol VIL Parameter Standard IO input low level voltage IO FT(1) input low level voltage Conditions Vhys IO FT(1) input high level voltage Standard IO Schmitt trigger voltage hysteresis(2) VDD > 2 V Input leakage current (4) Max Unit –0.3 0.28*(VDD-2 V)+0.8 V V –0.3 0.32*(VDD-2V)+0.75 V V 0.41*(VDD-2 V)+1.3 V VDD+0.3 V 5.5 0.42*(VDD-2 V)+1 V VDD ≤ 2 V 5.2 V 200 - mV 5% VDD(3) - mV VSS ≤ VIN ≤ VDD Standard I/Os - ±1 VIN = 5 V I/O FT - - IO FT Schmitt trigger voltage hysteresis(2) Ilkg Typ - Standard IO input high level voltage VIH Min µA 3 RPU Weak pull-up equivalent resistor(5) VIN = VSS 30 40 50 kΩ RPD Weak pull-down equivalent resistor(5) VIN = VDD 30 40 50 kΩ CIO I/O pin capacitance - - 5 - pF 1. FT = Five-volt tolerant. In order to sustain a voltage higher than VDD+0.3 the internal pull-up/pull-down resistors must be disabled. 2. Hysteresis voltage between Schmitt trigger switching levels. Guaranteed by characterization results, not tested in production. 3. With a minimum of 100 mV. 4. Leakage could be higher than maximum value if negative current is injected on adjacent pins. 5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This PMOS/NMOS contribution to the series resistance is minimum (~10% order). All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. The coverage of these requirements is shown in Figure 39 and Figure 40 for standard I/Os, and in Figure 41 and Figure 42 for 5 V tolerant I/Os. 82/121 DocID14610 Rev 9 STM32F101xC, STM32F101xD, STM32F101xE Electrical characteristics Figure 39. Standard I/O input characteristics - CMOS port 6)(6),6  6   6 )( $$ 6 $$ ENT6 )( QUIREM NDARDRE -/3STA # 7)(MIN    7),MAX    6   6), $$ 6 MENT6 ), $$ RDREQUIRE #-/3STANDA  )NPUTRANGE NOTGUARANTEED           6$$6  AIB Figure 40. Standard I/O input characteristics - TTL port 6)(6),6 7)(MIN 44,REQUIREMENTS 6)( 6   6   6 )( $$ )NPUTRANGE NOTGUARANTEED   7),MAX    6 ),6 $$  44,REQUIREMENTS 6),6    6$$6 AI DocID14610 Rev 9 83/121 120 Electrical characteristics STM32F101xC, STM32F101xD, STM32F101xE Figure 41. 5 V tolerant I/O input characteristics - CMOS port 6)(6),6 6 $$ TS6 )( UIREMEN REQ TANDARD #-/3S             )NPUTRANGE NOTGUARANTEED    6 ),6 $$ T6 ),6 $$ REQUIRMEN /3STANDARD #-    6 )(6 $$   6$$6  6$$ AIB Figure 42. 5 V tolerant I/O input characteristics - TTL port 6)(6),6 44,REQUIREMENT6 )(6    6   6 )( $$ 7)(MIN 7),MAX  )NPUTRANGE NOTGUARANTEED   6 ), 6 $$   44,REQUIREMENTS6 ),6    6$$6 AI Output driving current The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or source up to ± 20 mA (with a relaxedVOL/VOH) except PC13, PC14 and PC15 which can sink or source up to ±3 mA. When using the GPIOs PC13 to PC15 in output mode, the speed should not exceed 2 MHz with a maximum load of 30 pF. In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 5.2: 84/121 • The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating IVDD (see Table 8). • The sum of the currents sunk by all the I/Os on VSS plus the maximum Run consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating IVSS (see Table 8). DocID14610 Rev 9 STM32F101xC, STM32F101xD, STM32F101xE Electrical characteristics Output voltage levels Unless otherwise specified, the parameters given in Table 47 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 10. All I/Os are CMOS and TTL compliant. Table 47. Output voltage characteristics Symbol VOL(1) VOH (3) VOL(1) VOH (3) VOL(1) VOH (3) VOL(1) VOH (3) Parameter Output Low level voltage for an I/O pin when 8 pins are sunk at the same time Output High level voltage for an I/O pin when 8 pins are sourced at the same time Output low level voltage for an I/O pin when 8 pins are sunk at the same time Output high level voltage for an I/O pin when 8 pins are sourced at the same time Output low level voltage for an I/O pin when 8 pins are sunk at the same time Output high level voltage for an I/O pin when 8 pins are sourced at the same time Output low level voltage for an I/O pin when 8 pins are sunk at the same time Output high level voltage for an I/O pin when 8 pins are sourced at the same time Conditions Min Max CMOS port(2), IIO = +8 mA, 2.7 V < VDD < 3.6 V - 0.4 TTL port(2) IIO = +8 mA 2.7 V < VDD < 3.6 V IIO = +20 mA(4) 2.7 V < VDD < 3.6 V IIO = +6 mA(4) 2 V < VDD < 2.7 V Unit V VDD–0.4 - - 0.4 V 2.4 - - 1.3 V VDD–1.3 - - 0.4 V VDD–0.4 - 1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 8 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52. 3. The IIO current sourced by the device must always respect the absolute maximum rating specified in Table 8 and the sum of IIO (I/O ports and control pins) must not exceed IVDD. 4. Guaranteed by characterization results, not tested in production. DocID14610 Rev 9 85/121 120 Electrical characteristics STM32F101xC, STM32F101xD, STM32F101xE Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure 43 and Table 48, respectively. Unless otherwise specified, the parameters given in Table 48 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 10. Table 48. I/O AC characteristics(1) MODEx [1:0] bit value(1) Symbol Parameter fmax(IO)out Maximum frequency(2) 10 tf(IO)out Output high to low level fall time tr(IO)out Output low to high level rise time fmax(IO)out Maximum frequency(2) 01 tf(IO)out Output high to low level fall time tr(IO)out Output low to high level rise time Fmax(IO)out Maximum 11 tf(IO)out tr(IO)out Frequency(2) Output high to low level fall time Conditions CL = 50 pF, VDD = 2 V to 3.6 V tEXTIpw 2 MHz CL = 50 pF, VDD = 2 V to 3.6 V ns (3) 125 CL= 50 pF, VDD = 2 V to 3.6 V 10 MHz 25(3) CL= 50 pF, VDD = 2 V to 3.6 V ns 25(3) CL= 30 pF, VDD = 2.7 V to 3.6 V 50 MHz CL = 50 pF, VDD = 2.7 V to 3.6 V 30 MHz CL = 50 pF, VDD = 2 V to 2.7 V 20 MHz CL = 30 pF, VDD = 2.7 V to 3.6 V 5(3) CL = 50 pF, VDD = 2.7 V to 3.6 V 8(3) CL = 50 pF, VDD = 2 V to 2.7 V 12(3) CL = 30 pF, VDD = 2.7 V to 3.6 V 5(3) Output low to high level rise CL = 50 pF, VDD = 2.7 V to 3.6 V time Pulse width of external signals detected by the EXTI controller Unit 125(3) CL = 50 pF, VDD = 2 V to 2.7 V - Max - ns 8(3) 12(3) 10 ns 1. The I/O speed is configured using the MODEx[1:0] bits. Refer to the STM32F10xxx reference manual for a description of GPIO Port configuration register. 2. The maximum frequency is defined in Figure 43. 3. Guaranteed by design, not tested in production. 86/121 DocID14610 Rev 9 STM32F101xC, STM32F101xD, STM32F101xE Electrical characteristics Figure 43. I/O AC characteristics definition       (;7(51$/ 287387 21&/ WU,2RXW WI,2RXW 7 0D[LPXPIUHTXHQF\LVDFKLHYHGLIWUWI”7DQGLIWKHGXW\F\FOHLV ZKHQORDGHGE\&/VSHFLILHGLQWKHWDEOH³,2$&FKDUDFWHULVWLFV´  5.3.15 DLG NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 46). Unless otherwise specified, the parameters given in Table 49 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 10. Table 49. NRST pin characteristics Symbol Parameter Conditions Min Typ Max Unit VIL(NRST)(1) NRST Input low level voltage - –0.5 - 0.8 VIH(NRST)(1) NRST Input high level voltage - 2 - VDD+0.5 Vhys(NRST) NRST Schmitt trigger voltage hysteresis - - 200 - mV VIN = VSS 30 40 50 kΩ - - - 100 ns - 300 - - ns RPU VF(NRST)(1) Weak pull-up equivalent resistor(2) NRST Input filtered pulse VNF(NRST)(1) NRST Input not filtered pulse V 1. Guaranteed by design, not tested in production. 2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance must be minimum (~10% order). DocID14610 Rev 9 87/121 120 Electrical characteristics STM32F101xC, STM32F101xD, STM32F101xE Figure 44. Recommended NRST pin protection 9'' ([WHUQDO UHVHWFLUFXLW  1567  538 ,QWHUQDO5HVHW )LOWHU —) 670) DLF 1. The reset network protects the device against parasitic resets. 2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 49. Otherwise the reset will not be taken into account by the device. 88/121 DocID14610 Rev 9 STM32F101xC, STM32F101xD, STM32F101xE 5.3.16 Electrical characteristics TIM timer characteristics The parameters given in Table 50 are guaranteed by design. Refer to Section 5.3.13: I/O current injection characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 50. TIMx(1) characteristics Symbol tres(TIM) fEXT ResTIM tCOUNTER Parameter Conditions Min Max Unit 1 - tTIMxCLK 27.8 - ns - 0 fTIMxCLK/2 MHz fTIMxCLK = 36 MHz 0 18 MHz Timer resolution - - 16 bit 16-bit counter clock period when internal clock is selected - 1 65536 tTIMxCLK 1820 µs Timer resolution time Timer external clock frequency on CH1 to CH4 tMAX_COUNT Maximum possible count fTIMxCLK = 36 MHz fTIMxCLK = 36 MHz 0.0278 - - 65536 × 65536 tTIMxCLK fTIMxCLK = 36 MHz - 119.2 s 1. TIMx is used as a general term to refer to the TIM1, TIM2, TIM3 and TIM4 timers. 5.3.17 Communications interfaces I2C interface characteristics The STM32F101xC, STM32F101xD and STM32F101xE access line I2C interface meets the requirements of the standard I2C communication protocol with the following restrictions: the I/O pins SDA and SCL are mapped to are not “true” open-drain. When configured as opendrain, the PMOS connected between the I/O pin and VDD is disabled, but is still present. The I2C characteristics are described in Table 51. Refer also to Section 5.3.13: I/O current injection characteristics for more details on the input/output alternate function characteristics (SDA and SCL). DocID14610 Rev 9 89/121 120 Electrical characteristics STM32F101xC, STM32F101xD, STM32F101xE Table 51. I2C characteristics Symbol Parameter Standard mode I2C(1)(2) Fast mode I2C(1)(2) Unit Min Max Min Max tw(SCLL) SCL clock low time 4.7 - 1.3 - tw(SCLH) SCL clock high time 4.0 - 0.6 - tsu(SDA) SDA setup time 250 - 100 - th(SDA) SDA data hold time - 3450(3) - 900(3) tr(SDA) tr(SCL) SDA and SCL rise time - 1000 - 300 tf(SDA) tf(SCL) SDA and SCL fall time - 300 - 300 th(STA) Start condition hold time 4.0 - 0.6 - tsu(STA) Repeated Start condition setup time 4.7 - 0.6 - tsu(STO) Stop condition setup time 4.0 - 0.6 - µs tw(STO:STA) Stop to Start condition time (bus free) 4.7 - 1.3 - µs Cb Capacitive load for each bus line - 400 - 400 pF tSP Pulse width of the spikes that are suppressed by the analog filter for standard and fast mode 0 50(4) 0 50(4) μs 1. Guaranteed by design, not tested in production. 2. fPCLK1 must be at least 2 MHz to achieve standard mode I2C frequencies. It must be at least 4 MHz to achieve the fast mode I2C frequencies and it must be a multiple of 10 MHz in order to reach the I2C fast mode maximum clock speed of 400 kHz. 3. The maximum data hold time has only to be met if the interface does not stretch the low period of SCL signal. 4. The minimum width of the spikes filtered by the analog filter is above tSP(max). 90/121 DocID14610 Rev 9 µs ns µs STM32F101xC, STM32F101xD, STM32F101xE Electrical characteristics Figure 45. I2C bus AC waveforms and measurement circuit(1) s ͺ/Ϯ s ͺ/Ϯ ZW ZW ^dDϯϮ Z^ ^ /ϸďƵƐ Z^ ^> ^ d Z dZWd ^ d Z d ^ d Z d ƚƐƵ;^dͿ ^  ƚĨ;^Ϳ ƚƌ;^Ϳ ƚŚ;^dͿ ƚƐƵ;^Ϳ ƚŚ;^Ϳ ƚǁ;^>>Ϳ ƚǁ;^dK͗^dͿ ^ dKW ^> ƚƌ;^>Ϳ ƚǁ;^>,Ϳ ƚĨ;^>Ϳ ƚƐƵ;^dKͿ ĂŝϭϰϵϳϵĚ 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. 1. RS = series protection resistor. 2. RP = external pull-up resistor. 3. VDD_I2C is the I2C bus power supply. Table 52. SCL frequency (fPCLK1= 36 MHz, VDD = VDD_I2C = 3.3 V)(1)(2) fSCL I2C_CCR value (kHz) RP = 4.7 kΩ 400 0x801E 300 0x8028 200 0x803C 100 0x00B4 50 0x0168 20 0x0384 1. RP = External pull-up resistance, fSCL = I2C speed. 2. For speeds around 200 kHz, the tolerance on the achieved speed is of ±5%. For other speed ranges, the tolerance on the achieved speed ±2%. These variations depend on the accuracy of the external components used to design the application. DocID14610 Rev 9 91/121 120 Electrical characteristics STM32F101xC, STM32F101xD, STM32F101xE SPI interface characteristics Unless otherwise specified, the parameters given in Table 53Table 54 are derived from tests performed under ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 10. Refer to Section 5.3.13: I/O current injection characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO). Table 53. STM32F10xxx SPI characteristics Symbol Parameter fSCK 1/tc(SCK) SPI clock frequency Min Max Master mode - 10 Slave mode - 10 SPI clock rise and fall time Capacitive load: C = 30 pF - 8 tsu(NSS)(1) NSS setup time Slave mode 4tPCLK - th(NSS)(1) NSS hold time Slave mode 73 - Master mode, fPCLK = 36 MHz, presc = 4 50 60 Master mode - SPI1 3 - Master mode - SPI2 5 - Slave mode 4 - Master mode - SPI1 4 - Data input hold time Master mode - SPI2 6 - Slave mode 5 - Slave mode, fPCLK = 36 MHz, presc = 4 0 55 Slave mode, fPCLK = 20 MHz - 4tPCLK Data output disable time Slave mode 10 - tv(SO) (1) Data output valid time Slave mode (after enable edge) - 25 tv(MO)(1) Data output valid time Master mode (after enable edge) - 6 Slave mode (after enable edge) 25 - Master mode (after enable edge) 6 - tr(SCK) tf(SCK) (1) tw(SCKH) SCK high and low tw(SCKL)(1) time tsu(MI) (1) tsu(SI)(1) th(MI) (1) th(SI) ta(SO) Data input setup time (1) (1)(2) tdis(SO)(1)(3) th(SO)(1) th(MO) (1) Data output access time Data output hold time Conditions Unit MHz ns 1. Guaranteed by characterization results, not tested in production. 2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. 3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z 92/121 DocID14610 Rev 9 STM32F101xC, STM32F101xD, STM32F101xE Electrical characteristics Table 54. SPI characteristics Symbol fSCK 1/tc(SCK) Parameter SPI clock frequency Conditions Min Max Master mode - 18 Slave mode - 18 - 8 ns % tr(SCK) tf(SCK) SPI clock rise and fall time Capacitive load: C = 30 pF DuCy(SCK) SPI slave input clock duty cycle Slave mode 30 70 NSS setup time Slave mode 4tPCLK - NSS hold time Slave mode 2tPCLK - SCK high and low time Master mode, fPCLK = 36 MHz, presc = 4 50 60 Master mode 5 - Slave mode 5 - Master mode 5 - Slave mode 4 - tsu(NSS)(1) th(NSS) (1) tw(SCKH)(1) tw(SCKL)(1) tsu(MI) (1) tsu(SI)(1) th(MI) Data input setup time (1) th(SI)(1) Data input hold time ta(SO)(1)(2) Data output access time Slave mode, fPCLK = 20 MHz 0 3tPCLK tdis(SO)(1)(3) Data output disable time Slave mode 2 10 (1)(1) Data output valid time Slave mode (after enable edge) - 25 tv(MO)(1)(1) Data output valid time Master mode (after enable edge) - 5 Slave mode (after enable edge) 15 - Master mode (after enable edge) 2 - tv(SO) th(SO)(1) th(MO)(1) Data output hold time Unit MHz ns 1. Guaranteed by characterization results not tested in production. 2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. 3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z DocID14610 Rev 9 93/121 120 Electrical characteristics STM32F101xC, STM32F101xD, STM32F101xE Figure 46. SPI timing diagram - slave mode and CPHA=0 E^^ŝŶƉƵƚ ƚĐ;^/6%,'($/    (*   ([DPSOHRIDQDFWX DOWUDQVIH UFXUYH 7KHLGHDOWUDQVIHUFX UYH (QGSRLQWFRUUHODWLRQOLQH  (7 7RWDOXQDGMXVWHG(UURUPD[LPXPGHYLDWLRQ EHWZHHQWKHDFWXDODQGWKHLGHDOWUDQVIHUFXUYHV (2 2IIVHW(UURUGHYLDWLRQEHWZHHQWKHILUVWDFWXDO WUDQVLWLRQDQGWKHODVWDFWXDORQH (* *DLQ(UURUGHYLDWLRQEHWZHHQWKHODVWLGHDO WUDQVLWLRQDQGWKHODVWDFWXDORQH (' 'LIIHUHQWLDO/LQHDULW\(UURUPD[LPXPGHYLDWLRQ EHWZHHQDFWXDOVWHSVDQGWKHLGHDORQH (/ ,QWHJUDO/LQHDULW\(UURUPD[LPXPGHYLDWLRQ EHWZHHQDQ\DFWXDOWUDQVLWLRQDQGWKHHQGSRLQW FRUUHODWLRQOLQH  (7      (2  (/  ('  /6%,'($/   966$            9''$ DLH 98/121 DocID14610 Rev 9 STM32F101xC, STM32F101xD, STM32F101xE Electrical characteristics Figure 50. Typical connection diagram using the ADC 670)[[[ 9'' 5$,1 9$,1 6DPSOHDQGKROG$'& FRQYHUWHU 97 9 5$'& $,1[ 97 9 &SDUDVLWLF ,/“—$ ELW FRQYHUWHU &$'& DLG 1. Refer to Table 55 for the values of RAIN, RADC and CADC. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy this, fADC should be reduced. General PCB design guidelines Power supply decoupling should be performed as shown in Figure 51 or Figure 52, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip. Figure 51. Power supply and reference decoupling (VREF+ not connected to VDDA) 670)[[[ 9 5() 6HHQRWH —)Q) 9 ''$ —)Q) 9 66$9 5() 6HHQRWH DLF 1. VREF+ and VREF- inputs are available only on 100-pin packages. DocID14610 Rev 9 99/121 120 Electrical characteristics STM32F101xC, STM32F101xD, STM32F101xE Figure 52. Power supply and reference decoupling (VREF+ connected to VDDA) 34-&XXX 62%&6$$! 3EENOTE —&N& 62%&n633! 3EENOTE AIC 1. VREF+ and VREF- inputs are available only on 100-pin packages. 5.3.19 DAC electrical specifications Table 59. DAC characteristics Symbol Parameter Min Typ Max(1) Unit Comments VDDA Analog supply voltage 2.4 - 3.6 V VREF+ Reference supply voltage 2.4 - 3.6 V VSSA Ground 0 - 0 V RLOAD(2) Resistive load with buffer ON 5 - - kΩ RO(2) Impedance output with buffer OFF - - 15 When the buffer is OFF, the minimum resistive load between kΩ DAC_OUT and VSS to have a 1% accuracy is 1.5 MΩ CLOAD(2) Capacitive load - - 50 pF DAC_OUT min(2) Lower DAC_OUT voltage with buffer ON 0.2 - - V DAC_OUT max(2) Higher DAC_OUT voltage with buffer ON - - VDDA – 0.2 V DAC_OUT min(2) Lower DAC_OUT voltage with buffer OFF - 0.5 - mV DAC_OUT max(2) Higher DAC_OUT voltage with buffer OFF VREF+ – 1LSB V 100/121 - DocID14610 Rev 9 VREF+ must always be below VDDA Maximum capacitive load at DAC_OUT pin (when the buffer is ON). It gives the maximum output excursion of the DAC. It corresponds to 12-bit input code (0x0E0) to (0xF1C) at VREF+ = 3.6 V and (0x155) and (0xEAB) at VREF+ = 2.4 V. It gives the maximum output excursion of the DAC. STM32F101xC, STM32F101xD, STM32F101xE Electrical characteristics Table 59. DAC characteristics (continued) Min Typ Max(1) - - 220 With no load, worst code (0xF1C) µA at VREF+ = 3.6 V in terms of DC consumption on the inputs. - - 380 µA - - 480 With no load, worst code (0xF1C) µA at VREF+ = 3.6 V in terms of DC consumption on the inputs. - - ±0.5 LSB Given for the DAC in 10-bit configuration. - - ±2 LSB Given for the DAC in 12-bit configuration. - - ±1 LSB Given for the DAC in 10-bit configuration. - - ±4 LSB Given for the DAC in 12-bit configuration. - - ±10 mV - - ±3 LSB Given for the DAC in 10-bit at VREF+ = 3.6 V. - - ±12 LSB Given for the DAC in 12-bit at VREF+ = 3.6 V. - - ±0.5 % Given for the DAC in 12bit configuration. Settling time (full scale: for a 10-bit input code transition between the lowest and the highest input codes when DAC_OUT reaches final value ±1LSB - 3 4 µs CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ Update rate Max frequency for a correct change when small variation in the input code (from code i to i+1LSB) - - 1 tWAKEUP(1) Wakeup time from off state (Setting the ENx bit in the DAC Control register) - 6.5 10 µs PSRR+ (2) Power supply rejection ratio (to VDDA) (static DC measurement - –67 –40 dB No RLOAD, CLOAD = 50 pF Symbol Parameter DAC DC current consumption in quiescent mode (Standby mode) IDDVREF+ DAC DC current consumption in quiescent mode(3) IDDA Differential non linearity Difference between two consecutive code-1LSB) DNL(1) Integral non linearity (difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 1023) INL(1) Offset error (difference between measured value at Code (0x800) and the ideal value = VREF+/2) Offset(1) Gain error(1) Gain error tSETTLINGv (1) DAC_OUT Unit Comments With no load, middle code (0x800) on the inputs. MS/s CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ input code between lowest and highest possible ones. 1. Guaranteed by characterization results, not tested in production. 2. Guaranteed by design, not tested in production. 3. Quiescent mode refers to the state of the DAC when a steady value is kept on the output so that no dynamic consumption is involved. DocID14610 Rev 9 101/121 120 Electrical characteristics STM32F101xC, STM32F101xD, STM32F101xE Figure 53. 12-bit buffered /non-buffered DAC %XIIHU 5/ '$&B287[ ELW GLJLWDOWR DQDORJ FRQYHUWHU &/ AI6 1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register. 5.3.20 Temperature sensor characteristics Table 60. TS characteristics Symbol TL(1) Parameter VSENSE linearity with temperature (1) Min Typ Max Unit - ±1 ±2 °C Avg_Slope Average slope 4.0 4.3 4.6 mV/°C V25(1) Voltage at 25°C 1.34 1.43 1.52 V Startup time 4 - 10 µs ADC sampling time when reading the temperature - - 17.1 µs tSTART (2) TS_temp(3)(2) 1. Guaranteed by characterization, not tested in production. 2. Guaranteed by design, not tested in production. 3. Shortest sampling time can be determined in the application by multiple iterations. 102/121 DocID14610 Rev 9 STM32F101xC, STM32F101xD, STM32F101xE 6 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. LQFP144 package information Figure 54. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package outline C ! ! 3%!4).' 0,!.% # ! MM CCC # $ , $ + ! '!5'%0,!.% , $     % % % B 6.1    0). )$%.4)&)#!4)/.  E !?-%?6 1. Drawing is not to scale. DocID14610 Rev 9 103/121 120 Package information STM32F101xC, STM32F101xD, STM32F101xE Table 61. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package mechanical data Symbol inches(1) millimeters Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 21.800 22.000 22.200 0.8583 0.8661 0.874 D1 19.800 20.000 20.200 0.7795 0.7874 0.7953 D3 - 17.500 - - 0.689 - E 21.800 22.000 22.200 0.8583 0.8661 0.874 E1 19.800 20.000 20.200 0.7795 0.7874 0.7953 E3 - 17.500 - 0.689 e - 0.500 - 0.0197 L 0.450 0.600 0.750 L1 - 1.000 - k 0° 3.5° 7° 0° 3.5° 7° ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. 104/121 DocID14610 Rev 9 0.0177 0.0236 0.0295 0.0394 STM32F101xC, STM32F101xD, STM32F101xE Package information Figure 55. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package footprint                 DLH 1. Dimensions are expressed in millimeters. DocID14610 Rev 9 105/121 120 Package information STM32F101xC, STM32F101xD, STM32F101xE Device marking for LQFP144 The following figure gives an example of topside marking and pin 1 position identifier location. Figure 56. LQFP144 marking (package top view) 5HYLVLRQFRGH 3URGXFWLGHQWLILFDWLRQ 5 670)=&7 'DWHFRGH < :: 3LQ LGHQWLILHU 06Y9 1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity. 106/121 DocID14610 Rev 9 STM32F101xC, STM32F101xD, STM32F101xE 6.2 Package information LQFP100 package information Figure 57. LQFP100 – 14 x 14 mm, 100-pin low-profile quad flat package outline C ! MM ! ! 3%!4).'0,!.% # '!5'%0,!.% $ , $ ! + CCC # , $     % % % B   0).  )$%.4)&)#!4)/.  E ,?-%?6 1. Drawing is not to scale. Table 62. LQPF100 – 14 x 14 mm, 100-pin low-profile quad flat package mechanical data Symbol inches(1) millimeters Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 15.800 16.000 16.200 0.622 0.6299 0.6378 D1 13.800 14.000 14.200 0.5433 0.5512 0.5591 D3 - 12.000 - - 0.4724 - E 15.800 16.000 16.200 0.622 0.6299 0.6378 E1 13.800 14.000 14.200 0.5433 0.5512 0.5591 DocID14610 Rev 9 107/121 120 Package information STM32F101xC, STM32F101xD, STM32F101xE Table 62. LQPF100 – 14 x 14 mm, 100-pin low-profile quad flat package mechanical data (continued) Symbol inches(1) millimeters Min Typ Max Min Typ Max E3 - 12.000 - - 0.4724 - e - 0.500 - - 0.0197 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0° 3.5° 7° 0° 3.5° 7° ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 58. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat recommended footprint                AIC 1. Dimensions are in millimeters. 108/121 DocID14610 Rev 9 STM32F101xC, STM32F101xD, STM32F101xE Package information Device marking for LQFP100 The following figure gives an example of topside marking and pin 1 position identifier location. Figure 59. LQFP100 marking (package top view) 3URGXFWLGHQWLILFDWLRQ 670) 9&75 5HYLVLRQFRGH 'DWHFRGH < :: 3LQ LQGHQWLILHU 06Y9 1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity. DocID14610 Rev 9 109/121 120 Package information 6.3 STM32F101xC, STM32F101xD, STM32F101xE LQFP64 information Figure 60. LQFP64 – 10 x 10 mm, 64 pin low-profile quad flat package outline PP *$8*(3/$1( F $ $ $ 6($7,1*3/$1( & $ FFF & ' ' ' . / /      ( ( ( E  3,1 ,'(17,),&$7,21   H :B0(B9 1. Drawing is not to scale. Table 63. LQFP64 – 10 x 10 mm, 64 pin low-profile quad flat package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D - 12.000 - - 0.4724 - D1 - 10.000 - - 0.3937 - D3 - 7.500 - - 0.2953 - E - 12.000 - - 0.4724 - E1 - 10.000 - - 0.3937 - E3 - 7.500 - - 0.2953 - 110/121 DocID14610 Rev 9 STM32F101xC, STM32F101xD, STM32F101xE Package information Table 63. LQFP64 – 10 x 10 mm, 64 pin low-profile quad flat package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max e - 0.500 - - 0.0197 - θ 0° 3.5° 7° 0° 3.5° 7° L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 61. Recommended footprint                 AIC 1. Dimensions are in millimeters. DocID14610 Rev 9 111/121 120 Package information STM32F101xC, STM32F101xD, STM32F101xE Device marking for LQFP64 The following figure gives an example of topside marking and pin 1 position identifier location. Figure 62. LQFP64 marking (package top view) 5HYLVLRQFRGH 5 3URGXFWLGHQWLILFDWLRQ 670) 5&7 'DWHFRGH < :: 3LQ LQGHQWLILHU 06Y9 1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity. 112/121 DocID14610 Rev 9 STM32F101xC, STM32F101xD, STM32F101xE 6.4 Package information Thermal characteristics The maximum chip junction temperature (TJmax) must never exceed the values given in Table 10: General operating conditions on page 40. The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated using the following equation: TJ max = TA max + (PD max × ΘJA) Where: • TA max is the maximum ambient temperature in °C, • ΘJA is the package junction-to-ambient thermal resistance, in °C/W, • PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax), • PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power. PI/O max represents the maximum power dissipation on output pins where: PI/O max = Σ (VOL × IOL) + Σ((VDD – VOH) × IOH), taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the application. Table 64. Package thermal characteristics Symbol ΘJA 6.4.1 Parameter Value Thermal resistance junction-ambient LQFP144 - 20 x 20 mm / 0.5 mm pitch 30 Thermal resistance junction-ambient LQFP100 - 14 x 14 mm / 0.5 mm pitch 46 Thermal resistance junction-ambient LQFP64 - 10 x 10 mm / 0.5 mm pitch 45 Unit °C/W Reference document JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air), available from www.jedec.org. DocID14610 Rev 9 113/121 120 Package information 6.4.2 STM32F101xC, STM32F101xD, STM32F101xE Evaluating the maximum junction temperature for an application When ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in Table 65: Ordering information scheme. Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a specific maximum junction temperature. Here, only temperature range 6 is available (–40 to 85 °C). The following example shows how to calculate the temperature range needed for a given application, making it possible to check whether the required temperature range is compatible with the STM32F10xxx junction temperature range. Example: High-performance application Assuming the following application conditions: Maximum ambient temperature TAmax = 82 °C (measured according to JESD51-2), IDDmax = 50 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low level with IOL = 8 mA, VOL= 0.4 V and maximum 8 I/Os used at the same time in output mode at low level with IOL = 20 mA, VOL= 1.3 V PINTmax = 50 mA × 3.5 V= 175 mW PIOmax = 20 × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW This gives: PINTmax = 175 mW and PIOmax = 272 mW PDmax = 175 + 272 = 447 mW Thus: PDmax = 447 mW Using the values obtained in Table 65 TJmax is calculated as follows: – For LQFP64, 45 °C/W TJmax = 82 °C + (45 °C/W × 447 mW) = 82 °C + 20.1 °C = 102.1 °C This is within the junction temperature range of the STM32F10xxx (–40 < TJ < 105 °C). Figure 63. LQFP64 PD max vs. TA 700 PD (mW) 600 500 400 Suffix 6 300 200 100 0 65 75 85 95 TA (°C) 114/121 DocID14610 Rev 9 105 115 STM32F101xC, STM32F101xD, STM32F101xE 7 Part numbering Part numbering Table 65. Ordering information scheme Example: STM32 F 101 R C T 6 xxx Device family STM32 = ARM®-based 32-bit microcontroller Product type F = general-purpose Device subfamily 101 = access line Pin count R = 64 pins V = 100 pins Z = 144 pins Flash memory size C = 256 Kbytes of Flash memory D = 384 Kbytes of Flash memory E = 512 Kbytes of Flash memory Package T = LQFP Temperature range 6 = Industrial temperature range, –40 to 85 °C. Options xxx = programmed parts TR = tape and real For a list of available options (speed, package, etc..) or for further information on any aspect of this device, please contact your nearest ST sales office. DocID14610 Rev 9 115/121 120 Revision history 8 STM32F101xC, STM32F101xD, STM32F101xE Revision history Table 66. Document revision history Date Revision 07-Apr-2008 1 Initial release. 2 Document status promoted from Target Specification to Preliminary Data. Section 1: Introduction and Section 2.2: Full compatibility throughout the family modified. Small text changes. Note 1 added in Table 2: STM32F101xC, STM32F101xD and STM32F101xE features and peripheral counts on page 11. LQPF100/BGA100 column added to Table 6: FSMC pin definition on page 32. Values added to Maximum current consumption on page 42 (see Table 14, Table 15, Table 16 and Table 17). Values added to Typical current consumption on page 48 (see Table 18, Table 19 and Table 20 and see Figure 11, Figure 12, Figure 14, Figure 15 and Figure 16), Table 19: Typical current consumption in Standby mode removed. Figure 55: LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package footprint on page 105 corrected. Equation 1 corrected. Section 6.4.2: Evaluating the maximum junction temperature for an application on page 114 added. 22-May-2008 116/121 Changes DocID14610 Rev 9 STM32F101xC, STM32F101xD, STM32F101xE Table 66. Revision history Document revision history (continued) Date 21-Jul-2008 12-Dec-2008 Revision Changes 3 Document status promoted from Preliminary Data to full datasheet. FSMC (flexible static memory controller) on page 15 modified. Power supply supervisor on page 17 modified and VDDA added to Table 10: General operating conditions on page 40. Table notes revised in Section 5: Electrical characteristics. Capacitance modified in Figure 9: Power supply scheme on page 37. Table 52: SCL frequency (fPCLK1= 36 MHz, VDD = VDD_I2C = 3.3 V) updated. Table 54: SPI characteristics modified, th(NSS) modified in Figure 46: SPI timing diagram - slave mode and CPHA=0 on page 94. Minimum SDA and SCL fall time value for Fast mode removed from Table 51: I2C characteristics on page 90, note 1 modified. IDD_VBAT values added to Table 17: Typical and maximum current consumptions in Stop and Standby modes on page 45. Table 30: Flash memory endurance and data retention on page 59 updated. fHCLK corrected in Table 41: EMS characteristics. tsu(NSS) modified in Table 54: SPI characteristics. EO corrected in Table 58: ADC accuracy on page 98, fPCLK2 corrected in Table 57: ADC accuracy - limited test conditions and Table 58: ADC accuracy. Figure 50: Typical connection diagram using the ADC on page 99 and note below corrected. Typical TS_temp value removed from Table 60: TS characteristics on page 102. Section 6.1: LQFP144 package information on page 103 updated, Small text changes. 4 General-purpose timers (TIMx) on page 19 updated, Table 3: STM32F101xx family updated to show the low-density family, Table 4: Timer feature comparison added Figure 1: STM32F101xC, STM32F101xD and STM32F101xE access line block diagram updated. Note 9 added, main function after reset and Note 5 updated in Table 5: STM32F101xC/STM32F101xD/STM32F101xE pin definitions. Note 2 modified below Table 7: Voltage characteristics on page 38, |ΔVDDx| min and |ΔVDDx| min removed. Measurement conditions specified in Section 5.3.5: Supply current characteristics on page 42. General input/output characteristics on page 82 modified. Max values at TA = 85 °C updated in Table 17: Typical and maximum current consumptions in Stop and Standby modes on page 45. Section 5.3.10: FSMC characteristics on page 59 revised. Values added to Table 42: EMI characteristics on page 80. IVREF added to Table 55: ADC characteristics on page 96. Table 64: Package thermal characteristics on page 113 updated, Small text changes. DocID14610 Rev 9 117/121 120 Revision history STM32F101xC, STM32F101xD, STM32F101xE Table 66. Document revision history (continued) Date 30-Mar-2009 118/121 Revision Changes 5 I/O information clarified on cover page, Number of ADC peripherals corrected in Table 2: STM32F101xC, STM32F101xD and STM32F101xE features and peripheral counts. In Table 5: STM32F101xC/STM32F101xD/STM32F101xE pin definitions: – I/O level of pins PF11, PF12, PF13, PF14, PF15, G0, G1 and G15 updated – PB4, PB13, PB14, PB15, PB3/TRACESWO moved from Default column to Remap column. PG14 pin description modified in Table 6: FSMC pin definition, Figure 6: Memory map on page 35 modified. Note modified in Table 14: Maximum current consumption in Run mode, code with data processing running from Flash and Table 16: Maximum current consumption in Sleep mode, code running from Flash or RAM. Figure 14, Figure 15 and Figure 16 show typical curves (titles changed). Table 21: High-speed external user clock characteristics and Table 22: Low-speed user external clock characteristics modified. ACCHSI max values modified in Table 25: HSI oscillator characteristics FSMC configuration modified for Asynchronous waveforms and timings. Notes modified below Figure 21: Asynchronous nonmultiplexed SRAM/PSRAM/NOR read waveforms and Figure 22: Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms. tw(NADV) values modified in Table 31: Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings and Table 34: Asynchronous multiplexed NOR/PSRAM write timings. th(Data_NWE) modified in Table 32: Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings. In Table 36: Synchronous multiplexed PSRAM write timings and Table 38: Synchronous non-multiplexed PSRAM write timings: – tv(Data-CLK) renamed as td(CLKL-Data) – td(CLKL-Data) min value removed and max value added – th(CLKL-DV) / th(CLKL-ADV) removed Figure 25: Synchronous multiplexed NOR/PSRAM read timings. Figure 26: Synchronous multiplexed PSRAM write timings and Figure 28: Synchronous non-multiplexed PSRAM write timings modified, Small text changes. DocID14610 Rev 9 STM32F101xC, STM32F101xD, STM32F101xE Table 66. Revision history Document revision history (continued) Date 21-Jul-2009 24-Sep-2009 Revision Changes 6 Figure 1: STM32F101xC, STM32F101xD and STM32F101xE access line block diagram modified. Note 5 updated and Note 4 added in Table 5: STM32F101xC/STM32F101xD/STM32F101xE pin definitions. VRERINT and TCoeff added to Table 13: Embedded internal reference voltage. fHSE_ext min modified in Table 21: High-speed external user clock characteristics. Table 23: HSE 4-16 MHz oscillator characteristics modified. Note 1 modified below Figure 19: Typical application with an 8 MHz crystal. Figure 44: Recommended NRST pin protection modified. CL1 and CL2 replaced by C in Table 23: HSE 4-16 MHz oscillator characteristics and Table 24: LSE oscillator characteristics (fLSE = 32.768 kHz), notes modified and moved below the tables. Table 25: HSI oscillator characteristics modified. Conditions removed from Table 27: Low-power mode wakeup timings. Jitter added to Table 28: PLL characteristics. In Table 31: Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings: th(BL_NOE) and th(A_NOE) modified. In Table 32: Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings: th(A_NWE) and th(Data_NWE) modified. In Table 33: Asynchronous multiplexed NOR/PSRAM read timings: th(AD_NADV) and th(A_NOE) modified. In Table 34: Asynchronous multiplexed NOR/PSRAM write timings: th(A_NWE) modified. In Table 35: Synchronous multiplexed NOR/PSRAM read timings: th(CLKH-NWAITV) modified. In Table 40: Switching characteristics for NAND Flash read and write cycles: th(NOE-D) modified. Table 54: SPI characteristics modified. CADC and RAIN parameters modified in Table 55: ADC characteristics. RAIN max values modified in Table 56: RAIN max for fADC = 14 MHz. Table 59: DAC characteristics modified. Figure 53: 12-bit buffered /nonbuffered DAC added. 7 Number of DACs corrected in Table 3: STM32F101xx family. IDD_VBAT updated in Table 17: Typical and maximum current consumptions in Stop and Standby modes. Figure 13: Typical current consumption on VBAT with RTC on vs. temperature at different VBAT values added. IEC 1000 standard updated to IEC 61000 and SAE J1752/3 updated to IEC 61967-2 in Section : on page 78. Table 59: DAC characteristics modified. Small text changes. DocID14610 Rev 9 119/121 120 Revision history STM32F101xC, STM32F101xD, STM32F101xE Table 66. Document revision history (continued) Date 19-Apr-2011 15-May-2015 120/121 Revision Changes 8 Updated footnotes below Table 7: Voltage characteristics on page 38 and Table 8: Current characteristics on page 39 Updated tw min in Table 21: High-speed external user clock characteristics on page 51 Updated startup time in Table 24: LSE oscillator characteristics (fLSE = 32.768 kHz) on page 55 Updated Table 31: Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings on page 60 Updated FSMC sync data latency in Figure 25 thru Figure 28 Updated Figure 38: NAND controller waveforms for common memory write access and Table 40: Switching characteristics for NAND Flash read and write cycles on page 78 Updated Figure 44: Recommended NRST pin protection Added Section 5.3.13: I/O current injection characteristics Updated Section 5.3.13: I/O current injection characteristics Updated note 2 in Table 51: I2C characteristics on page 90 Updated Figure 45: I2C bus AC waveforms and measurement circuit(1) 9 Added OSC_IN/OSC_OUT remap functions and updated PD0/PD1 in Table 5: STM32F101xC/STM32F101xD/STM32F101xE pin definitions. Modified Section 2.3.21: GPIOs (general-purpose inputs/outputs) on page 20. Updated notes related to parameters not tested in production in the whole document. Updated Table 20: Peripheral current consumption on page 50. Updated CDM standard and values in Section : Electrostatic discharge (ESD). Modified Section : Output driving current on page 84. Updated Figure 43: I/O AC characteristics definition. Updated conditions related to Section : I2C interface characteristics. Modified Table 51: I2C characteristics on page 90, updated Figure 45: I2C bus AC waveforms and measurement circuit(1) and VDD/VDD_I2C conditions in Table 52: SCL frequency (fPCLK1= 36 MHz, VDD = VDD_I2C = 3.3 V) on page 91. Modified Figure 48: SPI timing diagram - master mode(1) on page 95. Modified note 3 in Table 58: ADC accuracy on page 98. Updated IDDA definition in Table 59: DAC characteristics on page 100 and removed comment related to the offset parameter for ±10 mV. Corrected “CLKL-NOEL” in Section 5.3.10: FSMC characteristics on page 59. Updated Section 6.1: LQFP144 package information on page 103 and added Section : Device marking for LQFP144 on page 106. Updated Section 6.2: LQFP100 package information on page 107 and added Section : Device marking for LQFP100 on page 109. Updated Section 6.3: LQFP64 information on page 110 and added Section : Device marking for LQFP64 on page 112. DocID14610 Rev 9 STM32F101xC, STM32F101xD, STM32F101xE IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2015 STMicroelectronics – All rights reserved DocID14610 Rev 9 121/121 121