STM6513
Reset
TM
Dual push-button Smart
with dual reset outputs and user-selectable setup delay
Features
■
Dual Smart Reset push-button inputs with
user-selectable extended reset setup delay (by
three-state input logic): tSRC = 2, 6, 10 s (min.)
■
Capacitor-adjustable reset pulse duration
(tREC1)
■
Power-on reset
■
Dual reset output (RST1 is active-high, pushpull type, RST2 is active-low, open-drain)
■
Factory-programmable thresholds to monitor
VCC in the range of 1.575 to 4.625 V typ.
■
Operating voltage 1.0 V (active-low output
valid) to 5.5 V
■
Low supply current 3 µA
■
Operating temperature: industrial grade –40 °C
to +85 °C
■
Mobile phones, smartphones
■
e-books
■
TDFN8 package: 2 mm x 2 mm x 0.75 mm
■
MP3 players
■
RoHS compliant
■
Games
■
Portable navigation devices
■
Any application that requires delayed reset
push-button(s) response for improved system
stability.
June 2010
TDFN8 (DG)
2 mm x 2 mm
Applications
Doc ID 16490 Rev 2
1/29
www.st.com
1
Contents
STM6513
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3
Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1
Power supply (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2
Ground (VSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.3
Smart Reset inputs (SR0, SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.4
User-programmable Smart Reset delay (TSR pin) . . . . . . . . . . . . . . . . . . 8
3.5
Reset outputs (RST1, RST2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.6
Adjustable output reset timeout period input pin (TRECADJ) . . . . . . . . . . . 8
4
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5
Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
8
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
9
Package footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
10
Tape and reel information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
11
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
12
Package marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
13
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2/29
Doc ID 16490 Rev 2
STM6513
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
tREC1 programmed by an ideal external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Operating and measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
DC and AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Possible VCC voltage thresholds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
TDFN – 8-lead 2 x 2 x 0.75 mm, 0.5 mm package mechanical data . . . . . . . . . . . . . . . . . 21
Parameter for landing pattern - TDFN – 8-lead 2 x 2 mm package . . . . . . . . . . . . . . . . . . 22
Carrier tape dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Reel dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Package marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Doc ID 16490 Rev 2
3/29
List of figures
STM6513
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
4/29
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Timing waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Smart Reset delay tSRC vs. temperature and supply voltage VCC,
TSR = VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Output reset timeout period tREC2 vs. temperature and supply voltage VCC
(tREC option E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Supply current ICC vs. temperature and supply voltage VCC . . . . . . . . . . . . . . . . . . . . . . . 13
Reset voltage VRST (falling) vs. temperature
(threshold option S, 2.925 V typ.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Input leakage current, TSR pin, logic low vs. temperature and supply voltage VCC . . . . . . 14
Input leakage current, TSR pin, logic high vs. temperature and supply voltage VCC . . . . . 15
AC testing input/output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
TDFN - 8-lead, 2 x 2 x 0.75 mm, 0.5 mm pitch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Landing pattern - TDFN – 8-lead 2 x 2 mm without thermal pad . . . . . . . . . . . . . . . . . . . . 22
Carrier tape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Reel dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Tape trailer/leader. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Pin 1 orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Package marking area, top view. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Doc ID 16490 Rev 2
STM6513
1
Description
Description
The STM6513 has two separate delayed Smart Reset inputs (SR0, SR1) which when taken
low simultaneously provide three user-selectable delayed Smart Reset setup time (tSRC)
options of 2 s, 6 s and 10 s. These are selected through a three-state TSR input pin: when
connected to ground, tSRC = 2 s; when left open, tSRC = 6 s; when connected to VCC,
tSRC = 10 s (all the times are minimum). There are two reset outputs, both going active
simultaneously after both the Smart Reset inputs were held active for the selected tSRC
delay time. The first reset output, RST1, is active-high, push-pull; the second reset output,
RST2, is active-low, open-drain requiring an external pull-up resistor. The duration of the
output reset pulses is independently programmable: tREC1 is user-programmable (by
external capacitor CtREC), tREC2 is factory-programmed to 210 ms (typ.), with the option of
360 ms typ. Additionally, the VCC is monitored and if it drops below the selected VRST
threshold, both the reset outputs go active and remain so while VCC is below the VRST
threshold, plus the defined duration of the reset pulse tREC on each output.
Smart Reset devices
The Smart Reset device family STM65xx provides a useful feature that ensures inadvertent
short reset push-button closures do not cause system resets. This is done by implementing
extended Smart Reset input delay (tSRC). Once the valid Smart Reset input levels and setup
delay are met, the device generates an output reset pulse with user-programmable timeout
period (tREC).
The Smart Reset inputs can be also connected to the applications interrupt to allow the
control of both the interrupt pin and the hard reset functions. If the push-buttons are closed
for a short time, the processor is only interrupted. If the system still does not respond
properly, holding the push-buttons for the extended setup time (tSRC) causes hard reset of
the processor through the reset outputs. The Smart Reset feature helps significantly
increase system stability.
The STM65xx family of Smart Reset devices consists of low current microprocessor reset
circuits targeted at applications such as MP3 players, navigation, smartphones or mobile
phones; generally any application that requires delayed reset push-button(s) response for
improved system stability. The STM65xx devices feature single or dual Smart Reset inputs
(SR). The delayed Smart Reset setup time (tSRC) options of 2 s, 6 s and 10 s
(all min.) are adjustable by an external capacitor on the SRC pin or selectable by three-state
logic. The delayed setup period ignores switch closures shorter than tSRC, thus preventing
unwanted resets.
The STM65xx devices have active-low (optionally active-high) open-drain reset (RST)
output(s) with or without internal pull-up resistor or push-pull as output options, with factoryprogrammed or capacitor-adjustable or push-buttons defined output reset pulse duration,
with or without power-on reset function.
Some devices also have an undervoltage monitoring feature: the reset output is also
asserted when the monitored supply voltage VCC drops below the specified threshold. The
reset output remains asserted for the reset timeout period (tREC) after the monitored supply
voltage goes above the specified threshold.
Doc ID 16490 Rev 2
5/29
Description
STM6513
Figure 1.
Logic diagram
VCC
SR1
TRECADJ
STM6513
RST1
RST2
SR0
TSR
VSS
Figure 2.
AM00372
Pin connections
RST1
1
8
VCC
VSS
2
7
SR0
SR1
3
6
TRECADJ
RST2
4
5
TSR
STM
6513
AM00373
6/29
Doc ID 16490 Rev 2
STM6513
2
Device overview
Device overview
Table 1.
Signal names
Symbol
Input/output
Description
RST1
Output
First reset output, active-high, push-pull.
RST2
Output
Second reset output, active-low, open-drain.
SR0
Input
Primary push-button Smart Reset input. Active-low.
SR1
Input
Secondary push-button Smart Reset input. Active-low.
TSR
Input
A Three-state Smart Reset input delay setup control. When connected
to ground, tSRC = 2 s; when left open, tSRC = 6 s; when connected to
VCC, tSRC = 10 s (all times are minimum). TSR is a DC-type input,
intended to be either permanently grounded, permanently connected
to VCC or permanently left open. If left open, for improved system glitch
immunity it is strongly recommended to connect a 0.1 µF decoupling
ceramic capacitor between the TSR and VSS pins.
TRECADJ
Input
Input pin for tREC1 reset pulse duration adjustment. Connect an
external capacitor CtREC to this pin to determine tREC1; tREC2 is factoryprogrammed.
VCC
Supply
Positive supply voltage input. Power supply for the device and an input
for the monitored supply voltage. A 0.1 µF decoupling ceramic
capacitor is recommended to be connected between VCC and VSS
pins.
VSS
Supply
Ground
Doc ID 16490 Rev 2
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Pin descriptions
3
Pin descriptions
3.1
Power supply (VCC)
STM6513
This pin is used to provide the power to the Smart Reset device and to monitor the power
supply. A 0.1 µF decoupling ceramic capacitor is recommended to be connected between
VCC and VSS pins.
3.2
Ground (VSS)
This is the ground for the device and all supplies.
3.3
Smart Reset inputs (SR0, SR1)
Push-button Smart Reset inputs. Both inputs need to be held active at the same time for at
least tSRC to activate the reset outputs. When only one Smart Reset input is used, connect
the unused one permanently to VSS.
3.4
User-programmable Smart Reset delay (TSR pin)
Used to allow the user to program the setup time before the push-buttons action is validated
by reset output. Controlled by different voltage levels on the TSR pin: when connected to
ground, tSRC = 2 s; when left open, tSRC = 6 s; when connected to VCC, tSRC = 10 s
(all times are minimum). TSR is a DC-type input, intended to be either permanently
grounded, permanently connected to VCC or permanently left open. If left open, for improved
system glitch immunity it is strongly recommended to connect a 0.1 µF decoupling ceramic
capacitor between the TSR and VSS pins.
3.5
Reset outputs (RST1, RST2)
Reset outputs, RST1 active-high, push-pull type, RST2 active-low, open-drain.
3.6
Adjustable output reset timeout period input pin (TRECADJ)
The output reset timeout period (tREC1) on RST1 is adjustable by connecting an external
capacitor CtREC to the TRECADJ pin. Calculated tREC and CtREC examples are given in
Table 2. Refer also to Table 5.
8/29
Doc ID 16490 Rev 2
STM6513
Pin descriptions
Table 2.
tREC1 programmed by an ideal external capacitor
tREC1 (ms)(1)(2)
Closest common
CtREC value (µF)
Min.
Typ.
Max.
CtREC value (µF)
0.001
10
15
20
0.001
0.002
20
30
40
0.0022
0.01
100
150
200
0.01
0.014
140
210
280
0.015
0.028
280
420
560
0.027
0.056
560
840
1120
0.056
0.112
1120
1680
2240
0.12
1. At 25 ° C. Example calculations based on an ideal capacitor. During application design and component
selection it should be considered that the current flowing into the external tREC programming capacitor
(CtREC) is on the order of 100 nA, therefore a low-leakage capacitor (ceramic or film capacitor) should be
used and placed as close as possible to the TRECADJ pin. Also an adequate low-leakage PCB
environment should be ensured to prevent tREC accuracy from being affected. A recommended minimum
value of C tREC is 0.001 µF.
2. In case of repeated activations of the internal tREC timer, an interval of 10 ms min. is needed between tREC
intervals to fully discharge CtREC, so that the next tREC1 is as specified.
Doc ID 16490 Rev 2
9/29
Block diagram
STM6513
4
Block diagram
Figure 3.
Block diagram
VCC
tREC2
RST2
tREC1
RST1
+
–
VREF
IREF
TRECADJ
SR1
tSRC
SR logic
SR0
TSR
Three-state
selector
Oscillator
AM00374V2
10/29
Doc ID 16490 Rev 2
STM6513
Block diagram
STM6513 hookup with RST1 and RST2, bridging the PS_hold reset pulse during the
microprocessor reset initiated by the STM6513 Smart Reset device:
Figure 4.
Typical application diagram
VCC
PMU
VREG
LD00
...
LD07
MCU
Seq.
logic
(PU resistor)
RST_n
RST
PWR
SW
POWER
KEY
PS_hold
PS_hold
100 kΩ
VREG
GPIO1
RST1 (PP)
RST2 (OD)
TSR
TRECADJ
STM6513
SR0
GPIOn
Forces PS_hold
high during
reset period
SR1
KEYn
CtREC
KEY1
AM00375a
Figure 5.
Timing waveforms
POR initiated
Smart Reset™ initiated
tSRC
SR0, SR1
RST2 (OD)
Factory programmed
RST1 (PP)
by CtREC
tREC2 (210 ms)
tREC1(~1 s)
tREC2 (210 ms)
tREC1 (~1 s)
AM00376V2
Doc ID 16490 Rev 2
11/29
Typical operating characteristics
5
STM6513
Typical operating characteristics
Figure 6.
Smart Reset delay tSRC vs. temperature and supply voltage VCC,
TSR = VSS
3
2.9
2.8
2.7
2.6
2.5
tSRC [s]
2.4
2.3
2.2
2.1
2
–60
–40
–20
0
20
40
60
80
100
120
140
Temperature [˚C]
5.5 V
3.3 V
AM00632
12/29
Doc ID 16490 Rev 2
STM6513
Typical operating characteristics
Figure 7.
Output reset timeout period tREC2 vs. temperature and supply voltage
VCC (tREC option E)
280
260
240
220
tREC2 [ms]
200
180
160
140
–60
–40
–20
0
20
40
60
80
100
120
140
Temperature [˚C]
5.5 V
3.3 V
AM00633
Supply current ICC vs. temperature and supply voltage VCC
Figure 8.
6
5
4
3
ICC [µA]
2
1
0
–60
–40
–20
0
20
40
60
80
100
120
140
Temperature [˚C]
5.5 V
3.3 V
AM00634
Doc ID 16490 Rev 2
13/29
Typical operating characteristics
Figure 9.
STM6513
Reset voltage VRST (falling) vs. temperature
(threshold option S, 2.925 V typ.)
2.96
2.95
2.94
2.93
VRST, falling [V]
2.92
2.91
2.9
2.89
–60
–40
–20
0
20
40
60
80
100
120
140
Temperature [˚C]
AM00635
Figure 10. Input leakage current, TSR pin, logic low vs. temperature and supply
voltage VCC
10
8
6
4
2
ILI(TSR) , LO [µA]
–60
–40
–20
0
0
20
40
60
80
100
120
140
–2
–4
–6
–8
–10
Temperature [˚C]
5.5 V
3.3 V
2V
AM00636
14/29
Doc ID 16490 Rev 2
STM6513
Typical operating characteristics
Figure 11. Input leakage current, TSR pin, logic high vs. temperature and supply
voltage VCC
10
8
6
4
2
ILI(TSR), HI [µA]
0
–60
–40
–20
0
20
40
60
80
100
120
140
–2
–4
–6
–8
–10
Temperature [˚C]
5.5 V
3.3 V
2V
AM00637
Doc ID 16490 Rev 2
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Maximum rating
6
STM6513
Maximum rating
Stressing the device above the rating listed in the Table 3: Absolute maximum ratings may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Table 3.
Absolute maximum ratings
Symbol
TSTG
Parameter
Storage temperature (VCC off)
TSLD(1)
Lead solder temperature for 10 seconds
θ JA
Thermal resistance (junction to ambient)
VIO
Input or output voltage
VCC
Supply voltage
TDFN8
Value
Unit
–55 to +150
°C
260
°C
149.0
°C/W
–0.3 to 5.5(2)
V
–0.3 to 7
V
1. Reflow at peak temperature of 260 °C. The time above 255 °C must not exceed 30 s.
2. For RST1 –0.3 to V CC +0.3 V only.
16/29
Doc ID 16490 Rev 2
STM6513
7
DC and AC parameters
DC and AC parameters
This section summarizes the operating measurement conditions, and the DC and AC
characteristics of the device. The parameters in the Table 5: DC and AC characteristics that
follow, are derived from tests performed under the Measurement Conditions summarized in
Table 4.: Operating and measurement conditions. Designers should check that the
operating conditions in their circuit match the operating conditions when relying on the
quoted parameters.
Table 4.
Operating and measurement conditions
Parameter
Value
Unit
VCC supply voltage
1.0 to 5.5
V
Ambient operating temperature (TA)
–40 to +85
°C
≤5
ns
Input pulse voltages
0.2 to 0.8 VCC
V
Input and output timing ref. voltages
0.3 to 0.7 VCC
V
Input rise and fall times
Figure 12. AC testing input/output waveforms
0.8 VCC
0.2 VCC
Doc ID 16490 Rev 2
0.7 VCC
0.3 VCC
AM00478
17/29
DC and AC parameters
Table 5.
STM6513
DC and AC characteristics
Symbol
Parameter
VCC
Supply voltage range
Test conditions(1)
Min.
5.5
V
Reset output valid - active-high
1.2
5.5
V
3
5
µA
4
6
µA
0.3
V
0.3
V
0.3
V
VCC = 3.0 V, TSR left open
(3)
VOL
VCC ≥ 4.5 V, sinking 3.2 mA
Reset output voltage
VCC ≥ 3.3 V, sinking 2.5 mA
low
VCC ≥ 1.0 V, sinking 0.1 mA
VCC = 5.0 V, TSR left open
VCC ≥ 4.5 V, ISOURCE = 0.8 mA
Reset output voltage
VCC ≥ 2.7 V, ISOURCE = 0.5 mA
high, RST1
VCC ≥ 1.2 V, ISOURCE = 0.05 mA
VRST
VHYST
Hysteresis of VRST
0.8 VCC
V
0.8 VCC
V
0.8 VCC
V
–40 to +85 °C
VRST –2.5%
VRST
VRST +2.5%
V
25 °C
VRST –2.0%
VRST
VRST +2.0%
V
L, M
VCC to reset delay(4)
0.5%
T, S, R, Z, Y, W, V
1%
VCC falling from (VRST + 100 mV)
to (VRST - 100 mV) at 10 mV/µs
20
tREC2
Output reset timeout Option E
period on RST2,
factory-programmed Option F
tREC1
User-adjustable
output reset timeout
period on RST1
Refer to Table 2.
18/29
Units
1.0
Supply current (VCC)
Fixed voltage trip
point for VCC
monitoring (refer to
Table 6)
Max.
Reset output valid - active-low
ICC
VOH
Typ.(2)
Doc ID 16490 Rev 2
µs
140
210
280
ms
240
360
480
ms
10 000 x
C tREC (µF)
15 000 x
CtREC (µF)
20 000 x
CtREC (µF)
ms
STM6513
DC and AC parameters
Table 5.
DC and AC characteristics (continued)
Symbol
Test conditions(1)
Min.
Typ.(2)
Max.
Units
TSR = VSS
2
2.5
3
s
TSR = floating
6
7.5
9
s
TSR = VCC
10
12.5
15
s
Parameter
Smart Reset inputs (SRx)
tSRC
Smart Reset delay
VIL
SR0, SR1 input
voltage low
VSS –0.3
0.3 VCC
V
VIH
SR0, SR1 input
voltage high
0.7 VCC
5.5
V
Input glitch
immunity(5)
Corresponds to the actual tSRC
tSRC
s
ILI(SR)
Input leakage
current (SR0, SR1
pins)
–1
1
µA
ILI(TSR)
Input leakage
current (TSR pin)
–5
7
µA
1. Valid for ambient operating temperature: TA = –40 to +85 °C; VCC = 1.0 V to 5.5 V (except where noted).
2. Typical value is at 25 °C and VCC = 3.3 V unless otherwise noted.
3. For devices with VRST < 3.0 V.
4. Guaranteed by design.
5. Input glitch immunity is equal to tSRC (when both SR inputs are low), otherwise infinite.
Table 6.
Possible VCC voltage thresholds
VCC monitoring
threshold VRST
±2.5% (–40 °C to +85 °C)
±2.0% (25 °C)
Typ.
Unit
Min.
Max.
Min.
Max.
L (falling)
4.625
4.509
4.741
4.533
4.718
V
M (falling)
4.375
4.266
4.484
4.288
4.463
V
T (falling)
3.075
2.998
3.152
3.014
3.137
V
S (falling)
2.925
2.852
2.998
2.867
2.984
V
R (falling)
2.625
2.559
2.691
2.573
2.678
V
Z (falling)
2.313
2.255
2.371
2.267
2.359
V
Y (falling)
2.188
2.133
2.243
2.144
2.232
V
W (falling)
1.665
1.623
1.707
1.632
1.698
V
V (falling)
1.575
1.536
1.614
1.544
1.607
V
Doc ID 16490 Rev 2
19/29
Package mechanical data
8
STM6513
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Figure 13. TDFN - 8-lead, 2 x 2 x 0.75 mm, 0.5 mm pitch
D
A
B
PIN 1 INDEX AREA
E
0.10 C 2x
0.10 C 2x
TOP VIEW
0.10 C
C
A1
A
SEATING
PLANE
SIDE VIEW
0.08 C
e
b
PIN 1 INDEX AREA
1
4
0.10
C A B
Pin#1 ID
L
5
8
BOTTOM VIEW
TDFN-8L
20/29
Doc ID 16490 Rev 2
STM6513
Package mechanical data
Table 7.
TDFN – 8-lead 2 x 2 x 0.75 mm, 0.5 mm package mechanical data
Dimension (mm)
Dimension (inches)
Symbol
Min.
Nom.
Max.
Min.
Nom.
Max.
A
0.70
0.75
0.80
0.028
0.030
0.031
A1
0.00
0.02
0.05
0.000
0.001
0.002
b
0.15
0.20
0.25
0.006
0.008
0.010
D
BSC
1.9
2.00
2.1
0.075
0.079
0.083
E
BSC
1.9
2.00
2.1
0.075
0.079
0.083
e
L
0.50
0.45
0.55
0.020
0.65
Doc ID 16490 Rev 2
0.018
0.022
0.026
21/29
Package footprint
9
STM6513
Package footprint
Figure 14. Landing pattern - TDFN – 8-lead 2 x 2 mm without thermal pad
D
P
E
E1
L
b
Table 8.
AM00441
Parameter for landing pattern - TDFN – 8-lead 2 x 2 mm package
Dimension (mm)
Parameter
22/29
Description
Min.
Nom.
Max.
L
Contact length
1.05
—
1.15
b
Contact width
0.25
—
0.30
E
Max. land pattern Y-direction
—
2.85
—
E1
Contact gap spacing
—
0.65
—
D
Max. land pattern X-direction
—
1.75
—
P
Contact pitch
—
0.5
—
Doc ID 16490 Rev 2
STM6513
10
Tape and reel information
Tape and reel information
Figure 15. Carrier tape
P0
D
P2
T
E
A0
F
Top cover
tape
W
B0
Center lines
of cavity
K0
P1
User direction of feed
AM03073v2
Table 9.
Carrier tape dimensions
Package
W
D
TDFN8
8.00
+0.30
–0.10
1.50
+0.10/
–0.00
E
P0
P2
F
1.75
4.00
2.00
3.50
±0.10 ±0.10 ±0.10 ±0.05
A0
B0
K0
P1
T
2.30
±0.05
2.30
±0.05
1.00
±0.05
4.00
±0.10
0.250
±0.05
Doc ID 16490 Rev 2
Unit
Bulk
qty.
mm 3000
23/29
Tape and reel information
STM6513
Figure 16. Reel dimensions
T
40 mm min.
acces hole
at slot location
B
D
C
N
A
Full radius
Tape slot
in core for
tape start
25 mm min width
G measured
at hub
AM00443
Table 10.
24/29
Reel dimensions
Tape sizes
A max.
B min.
C
D min.
N min.
G
T max.
8 mm
180 (7 inches)
1.50
13.0 +/– 0.20
20.20
60
8.4 +2/–0
14.40
Doc ID 16490 Rev 2
STM6513
Tape and reel information
Figure 17. Tape trailer/leader
End
Top
cover
tape
Start
No components
Components
100 mm min.
T RA IL ER
No components
L EA D ER
160 mm min.
400 mm min.
Sealed with cover tape
User direction of feed
AM00444
Figure 18. Pin 1 orientation
User direction of feed
Note:
1
Drawings are not to scale.
2
All dimensions are in mm, unless otherwise noted.
Doc ID 16490 Rev 2
AM00442
25/29
Part numbering
STM6513
11
Part numbering
Table 11.
Ordering information scheme
Example:
STM6513
V
E
I
E
DG
6
Device type
STM6513
Reset (VCC monitoring threshold) voltage VRST
L = 4.625 V (typ., falling)
M = 4.375 V
T = 3.075 V
S = 2.925 V
R = 2.625 V
Z = 2.313 V
Y = 2.188 V
W = 1.665 V
V = 1.575 V
Smart Reset setup delay (tSRC);
presence of internal input pull-up on all Smart Reset inputs (SR0, SR1)
E = 2 or 6 or 10 s min., user-programmed (three-state); no input pull-up
Outputs type
I = RST1 active-high, push-pull, RST2 active-low, open-drain, no pull-up
Reset timeout period (tREC)
E = tREC1 user-programmable (external capacitor), tREC2 factory-programmed (210 ms typ.)
F = tREC1 user-programmable (external capacitor), tREC2 factory-programmed (360 ms typ.)
Package
DG = TDFN8 - 2 x 2 x 0.75 mm, 0.5 mm pitch
Temperature range
6 = –40 °C to +85 °C
Shipping method
F = ECOPACK® package, tape and reel
For other options, voltage threshold values etc. or for more information on any aspect of this device,
please contact the ST sales office nearest you.
26/29
Doc ID 16490 Rev 2
F
STM6513
Package marking information
12
Package marking information
Table 12.
Package marking
Smart
RST1
tREC1
Reset
VRST output
programming
inputs type
type
Full part number
tSRC
delay
control
STM6513VEIEDG6F
TSR
AL, NPU
V
AH, PP
CtREC
AL, OD, NPU
E
9AH
STM6513SEIEDG6F
TSR
AL, NPU
S
AH, PP
CtREC
AL, OD, NPU
E
9SH
STM6513REIEDG6F
TSR
AL, NPU
R
AH, PP
CtREC
AL, OD, NPU
E
9RH
Note:
RST2 output
type
tREC2
Topmark
option
AL = active-low, AH = active-high; PP = push-pull, OD = open-drain, PU = internal pull-up
resistor, NPU = no internal pull-up resistor.
Figure 19. Package marking area, top view
A
B
C
D
E
Topmark
A = dot (pin 1 reference)
B = assembly plant (P)
C = assembly year (Y, 0-9): 9 = 2009 etc.
D = assembly work week (WW, 01 to 52): 20 = WW20 etc.
E = marking area (topmark)
AM00479
Doc ID 16490 Rev 2
27/29
Revision history
13
STM6513
Revision history
Table 13.
Document revision history
Date
Revision
22-Oct-2009
1
Initial release.
2
Updated title, Features, Applications, replaced “smart reset” by
“Smart Reset™” and “Smart Reset”, updated Section 1, Table 1,
Section 3, Table 2, Figure 3, Figure 5, Figure 6, Table 3, Table 5 to
Table 8, Table 11 and Table 12.
21-Jun-2010
28/29
Changes
Doc ID 16490 Rev 2
STM6513
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Doc ID 16490 Rev 2
29/29
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