STM818LM6F

STM690A, STM692A, STM703 STM704, STM802, STM805, STM817/8/9 5 V supervisor with battery switchover Features ■ 5 V operating voltage ■ NVRAM supervisor for external LPSRAM ■ Chip-enable gating (STM818 only) for external LPSRAM (7 ns max prop delay) ■ RST and RST outputs ■ 200 ms (typ) trec ■ Watchdog timer - 1.6 sec (typ) ■ Automatic battery switchover ■ Low battery supply current - 0.4 µA (typ) ■ Power-fail comparator (PFI/PFO) ■ Low supply current - 40 µA (typ) ■ Guaranteed RST (RST) assertion down to VCC = 1.0 V ■ Operating temperature: –40 °C to +85 °C (industrial grade) ■ RoHS compliance – Lead-free components are compliant with the RoHS directive Table 1. 8 1 SO8 (M) TSSOP8 3 x 3 (DS)(1) 1. Contact local ST sales office for availability. Device summary Part number Watchdog Active-low Activehigh RST input RST(1) Manual reset input(1) Battery Power-fail switchcomparator over STM690A ✓ ✓ ✓ ✓ STM692A ✓ ✓ ✓ ✓ STM703 ✓ ✓ ✓ ✓ STM704 ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ STM802L/M ✓ STM805L ✓ STM817L/M ✓ ✓ ✓ STM818L/M ✓ ✓ ✓ STM819L/M ✓ ✓ ✓ ✓ ✓ Chipenable gating ✓ ✓ ✓ Battery freshness seal ✓ ✓ 1. All RST and RST outputs are push-pull. August 2010 Doc ID 10522 Rev 10 1/43 www.st.com 1 Contents STM690A/692A/703/704/802/805/817/818/819 Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 2 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1.1 MR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1.2 WDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1.3 RST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1.4 RST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1.5 1.1.6 VOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 VBAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.1.7 E .......................................................9 1.1.8 1.1.9 ECON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 PFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.1.10 PFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1 Reset output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2 Push-button reset input (STM703/704/819) . . . . . . . . . . . . . . . . . . . . . . . 13 2.3 Watchdog input (NOT available on STM703/704/819) . . . . . . . . . . . . . . . 13 2.4 Backup battery switchover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.5 Chip-enable gating (STM818 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.6 Chip-enable input (STM818 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.7 Chip-enable output (STM818 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.8 Power-fail input/output (NOT available on STM818) . . . . . . . . . . . . . . . . 16 2.9 Applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.10 Using a SuperCap™ as a backup power source . . . . . . . . . . . . . . . . . . . 17 2.11 Negative-going VCC transients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.12 Battery freshness seal (STM817/818/819) . . . . . . . . . . . . . . . . . . . . . . . . 19 3 Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2/43 Doc ID 10522 Rev 10 STM690A/692A/703/704/802/805/817/818/819 Contents 6 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Doc ID 10522 Rev 10 3/43 List of tables STM690A/692A/703/704/802/805/817/818/819 List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. 4/43 Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 I/O status in battery backup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 DC and AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 SO8 - 8-lead plastic small outline, 150 mils body width, package mechanical data . . . . . . 38 TSSOP8 - 8-lead, thin shrink small outline, 3 x 3 mm body size, mechanical data . . . . . . 39 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Marking description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Doc ID 10522 Rev 10 STM690A/692A/703/704/802/805/817/818/819 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Logic diagram (STM690A/692/802/805/817) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Logic diagram (STM703/704/819) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Logic diagram (STM818) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 STM690A/692A/802/805/817 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 STM703/704/819 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 STM818 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Block diagram (STM690A/692A/802/805/817) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Block diagram (STM703/704/819) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Block diagram (STM818) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Chip-enable gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Chip-enable waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Power-fail comparator waveform (STM817/818/819) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Power-fail comparator waveform (STM690A/692A/703/704/802/805) . . . . . . . . . . . . . . . . 17 Using a SuperCap™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Freshness seal enable waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 VCC to VOUT on-resistance vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 VBAT to VOUT on-resistance vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Supply current vs. temperature (no load) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Battery current vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 VPFI threshold vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Reset comparator propagation delay vs. temperature (other than STM817/818/819) . . . . 22 Reset comparator propagation delay vs. temperature (VBAT = 3.0 V; STM817/818/819) . 23 Power-up tREC vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Normalized reset threshold vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Watchdog time-out period vs. temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 E to ECON on-resistance vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 PFI to PFO propagation delay vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Output voltage vs. load current (VCC = 5 V; VBAT = 2.8 V; TA = 25 °C) . . . . . . . . . . . . . . . 26 Output voltage vs. load current (VCC = 0 V; VBAT = 2.8 V; TA = 25 °C) . . . . . . . . . . . . . . . 26 RST output voltage vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 RST output voltage vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 RST response time (assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 RST response time (assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Power-fail comparator response time (assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Power-fail comparator response time (de-assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Maximum transient duration vs. reset threshold overdrive . . . . . . . . . . . . . . . . . . . . . . . . . 30 E to ECON propagation delay vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 E to ECON propagation delay test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 AC testing input/output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 MR timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Watchdog timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 SO8 - 8-lead plastic small outline, 150 mils body width, package mechanical drawing . . . 38 TSSOP8 - 8-lead, thin shrink small outline, 3 x 3 mm body size, outline . . . . . . . . . . . . . . 39 Doc ID 10522 Rev 10 5/43 Description 1 STM690A/692A/703/704/802/805/817/818/819 Description The STM690A/692A/703/704/802/805/817/818/819 supervisors are self-contained devices which provide microprocessor supervisory functions with the ability to non-volatize and write-protect external LPSRAM. A precision voltage reference and comparator monitors the VCC input for an out-of-tolerance condition. When an invalid VCC condition occurs, the reset output (RST) is forced low (or high in the case of RST). These devices also offer a watchdog timer (except for STM703/704/819) as well as a power-fail comparator (except for STM818) to provide the system with an early warning of impending power failure. These devices are available in a standard 8-pin SOIC package or a space-saving 8-pin TSSOP package. Figure 1. Logic diagram (STM690A/692/802/805/817) VCC VBAT VOUT WDI PFI STM690A/ 692A/802/ 805/817 RST(RST)(1) PFO VSS AI07894 1. For STM805, reset output is active-high. Figure 2. Logic diagram (STM703/704/819) VCC VBAT VOUT MR PFI STM703/ 704/819 RST PFO VSS 6/43 Doc ID 10522 Rev 10 AI07895 STM690A/692A/703/704/802/805/817/818/819 Figure 3. Description Logic diagram (STM818) VCC VBAT VOUT WDI RST STM818 E ECON VSS Table 2. AI07896 Signal names MR Push-button reset input WDI Watchdog input RST Active-low reset output RST Active-high reset outpu E(1) Chip-enable input ECON (1) Conditioned chip-enable output VOUT Supply voltage output VCC Supply voltage VBAT Backup supply voltage PFI Power-fail input PFO Power-fail output VSS Ground 1. STM818 Figure 4. STM690A/692A/802/805/817 connections SO8/TSSOP8 VOUT VCC VSS PFI 1 2 3 4 8 7 6 5 VBAT RST(RST)(1) WDI PFO AI07889 1. For STM805, reset output is active-high. Doc ID 10522 Rev 10 7/43 Description STM690A/692A/703/704/802/805/817/818/819 Figure 5. STM703/704/819 connections SO8/TSSOP8 VOUT VCC VSS PFI 1 2 3 4 8 7 6 5 VBAT RST MR PFO AI07890 Figure 6. STM818 connections SO8/TSSOP8 VOUT VCC VSS E 1 2 3 4 8 7 6 5 VBAT RST WDI ECON AI07892 1.1 Pin descriptions 1.1.1 MR A logic low on MR asserts the reset output. Reset remains asserted as long as MR is low and for trec after MR returns high. This active-low input has an internal pull-up. It can be driven from a TTL or CMOS logic line, or shorted to ground with a switch. Leave open if unused. 1.1.2 WDI If WDI remains high or low for 1.6 sec, the internal watchdog timer runs out and reset is triggered. The internal watchdog timer clears while reset is asserted or when WDI sees a rising or falling edge. The watchdog function can be disabled by allowing the WDI pin to float. 1.1.3 RST Pulses low for trec when triggered, and stays low whenever VCC is below the reset threshold or when MR is a logic low. It remains low for trec after either VCC rises above the reset threshold, the watchdog triggers a reset, or MR goes from low to high. 1.1.4 RST Pulses high for trec when triggered, and stays high whenever VCC is above the reset threshold or when MR is a logic high. It remains high for trec after either VCC falls below the reset threshold, the watchdog triggers a reset, or MR goes from high to low. 8/43 Doc ID 10522 Rev 10 STM690A/692A/703/704/802/805/817/818/819 1.1.5 Description VOUT When VCC is above the switchover voltage (VSO), VOUT is connected to VCC through a Pchannel MOSFET switch. When VCC falls below VSO, VBAT connects to VOUT. 1.1.6 VBAT When VCC falls below VSO, VOUT switches from VCC to VBAT. When VCC rises above VSO + hysteresis, VOUT reconnects to VCC. VBAT may exceed VCC. Connect to VCC if no battery is used. 1.1.7 E The input to the chip-enable gating circuit. Connect to ground if unused. 1.1.8 ECON ECON goes low only when E is low and reset is not asserted. If ECON is low when reset is asserted, ECON will remain low for 15 µs or until E goes high, whichever occurs first. In the disabled mode, ECON is pulled up to VOUT. 1.1.9 PFI When PFI is less than VPFI or when VCC falls below 2.4 V (or VSO), PFO goes low; otherwise, PFO remains high. Connect to ground if unused. 1.1.10 PFO When PFI is less than VPFI, or VCC falls below 2.4 V (or VSO), PFO goes low; otherwise, PFO remains high. Leave open if unused. Output type is push-pull. Doc ID 10522 Rev 10 9/43 Description Table 3. STM690A/692A/703/704/802/805/817/818/819 Pin description Pin STM690A STM692A STM818 STM802 STM817 STM703 STM704 Name Function STM805 STM819 - - 6 - MR Push-button reset input 6 6 - 6 WDI Watchdog input 7 7 7 - RST Active-low reset output - - - 7 RST Active-high reset output 1 1 1 1 VOUT Supply output for external LPSRAM 2 2 2 2 VCC Supply voltage 8 8 8 8 VBAT Backup battery input 4 - - - E 5 - - - ECON - 4 4 4 PFI Power-fail input - 5 5 5 PFO Power-fail output (push-pull) 3 3 3 3 VSS Ground Figure 7. Chip-enable input Conditioned chip-enable output Block diagram (STM690A/692A/802/805/817) VCC VOUT VBAT VSO COMPARE VRST COMPARE WATCHDOG TIMER WDI PFI VPFI COMPARE trec Generator (1) RST(RST) PFO AI07897 1. For STM805, reset output is active-high. 10/43 Doc ID 10522 Rev 10 STM690A/692A/703/704/802/805/817/818/819 Figure 8. Description Block diagram (STM703/704/819) VCC VOUT VBAT VSO COMPARE VRST COMPARE trec Generator MR PFI VPFI COMPARE RST PFO AI07898 Figure 9. Block diagram (STM818) VCC VOUT VBAT WDI VSO COMPARE VRST COMPARE WATCHDOG TIMER trec Generator RST ECON OUTPUT CONTROL E ECON AI07899a Doc ID 10522 Rev 10 11/43 Description STM690A/692A/703/704/802/805/817/818/819 Figure 10. Hardware hookup Regulator Unregulated Voltage VIN VCC VCC VCC VOUT VCC STM690A/692A/ 703/704/802/805/ 817/818/819 0.1 F LPSRAM E E 0.1 F WDI(1) From Microprocessor E(2) ECON(2) R1 PFI(3) PFO(3) MR(4) RST To Microprocessor NMI R2 Push-Button (5) To Microprocessor Reset VBAT AI07893 1. For STM690A/692A/802/805/817/818. 2. For STM818 only. 3. Not available on STM818. 4. For STM703/704/819. 5. Active high on STM805. 12/43 Doc ID 10522 Rev 10 STM690A/692A/703/704/802/805/817/818/819 2 Operation 2.1 Reset output Operation The STM690A/692A/703/704/802/805/817/818/819 Supervisor asserts a reset signal to the MCU whenever VCC goes below the reset threshold (VRST), a watchdog time-out occurs, or when the Push-button Reset Input (MR) is taken low. RST is guaranteed to be a logic low (logic high for STM805) for 0V < VCC < VRST if VBAT is greater than 1 V. Without a backup battery, RST is guaranteed valid down to VCC =1 V. During power-up, once VCC exceeds the reset threshold an internal timer keeps RST low for the reset time-out period, trec. After this interval RST returns high. If VCC drops below the reset threshold, RST goes low. Each time RST is asserted, it stays low for at least the reset time-out period (trec). Any time VCC goes below the reset threshold the internal timer clears. The reset timer starts when VCC returns above the reset threshold. 2.2 Push-button reset input (STM703/704/819) A logic low on MR asserts reset. Reset remains asserted while MR is low, and for trec (see Figure 41) after it returns high. The MR input has an internal 40 kΩ pull-up resistor, allowing it to be left open if not used. This input can be driven with TTL/CMOS-logic levels or with open-drain/collector outputs. Connect a normally open momentary switch from MR to GND to create a manual reset function; external debounce circuitry is not required. If MR is driven from long cables or the device is used in a noisy environment, connect a 0.1 µF capacitor from MR to GND to provide additional noise immunity. MR may float, or be tied to VCC when not used. 2.3 Watchdog input (NOT available on STM703/704/819) The watchdog timer can be used to detect an out-of-control MCU. If the MCU does not toggle the Watchdog Input (WDI) within tWD(1.6 sec typ), the reset is asserted. The internal watchdog timer is cleared by either: 1. a reset pulse, or 2. by toggling WDI (high-to-low or low-to-high), which can detect pulses as short as 50ns. If WDI is tied high or low, a reset pulse is triggered every 1.8 sec (tWD + trec). The timer remains cleared and does not count for as long as reset is asserted. As soon as reset is released, the timer starts counting (see Figure 42). Note: 1 The watchdog function may be disabled by floating WDI or tri-stating the driver connected to WDI. When tri-stated or disconnected, the maximum allowable leakage current is 10 µA and the maximum allowable load capacitance is 200 pF. 2 Input pulses less than 20 ns will be ignored. Doc ID 10522 Rev 10 13/43 Operation 2.4 STM690A/692A/703/704/802/805/817/818/819 Backup battery switchover In the event of a power failure, it may be necessary to preserve the contents of external SRAM through VOUT. With a backup battery installed with voltage VBAT, the devices automatically switch the SRAM to the backup supply when VCC falls. Note: When the battery is first connected without VCC power applied, the device does not immediately provide backup battery voltage on VOUT. Only after VCC exceeds VRST will the switchover operate as described below. This mode allows a battery to be attached during manufacturing but not used until after the system has been activated for the first time. As a result, no battery power is consumed by the device during storage and shipment. For the STM81x devices, the battery freshness seal can be initiated again by following the procedure outlined in Section 2.12. If the backup battery is not used, connect both VBAT and VOUT to VCC . Whenever VCC falls below the switchover voltage, VSO, VOUT is connected to VBAT through a 100 Ω switch. VSO is the lesser of VBAT and VRST. Choosing the lesser allows the device to be powered by VCC for as long as possible before switching over thereby maximizing the battery life. Assuming VBAT > 2.0 V, switchover at VSO ensures that battery backup mode is entered before VOUT gets too close to the 2.0 V minimum required to reliably retain data in most external SRAMs. When VCC recovers, hysteresis is used to avoid oscillation around the VSO point. VOUT is connected to VCC through a 3 Ω PMOS power switch. Note: The backup battery may be removed while VCC is valid, assuming VBAT is adequately decoupled (0.1 µF typ), without danger of triggering a reset. Table 4. I/O status in battery backup VOUT Connected to VBAT through internal switch VCC Disconnected from VOUT PFI Disabled PFO Logic low E 14/43 High impedance ECON Logic high WDI Watchdog timer is disabled MR Disabled RST Logic low RST Logic high VBAT Connected to VOUT Doc ID 10522 Rev 10 STM690A/692A/703/704/802/805/817/818/819 2.5 Operation Chip-enable gating (STM818 only) Internal gating of the chip-enable (E) signal prevents erroneous data from corrupting the external CMOS RAM in the event of an undervoltage condition. The STM818 uses a series transmission gate from E to ECON (see Figure 11). During normal operation (reset not asserted), the E transmission gate is enabled and passes all E transitions. When reset is asserted, this path becomes disabled, preventing erroneous data from corrupting the CMOS RAM. The short propagation delay from E to ECON enables the STM818 to be used with most µPs. If E is low when reset asserts, ECON remains low for typically 15 µs (or until E goes high) to permit the current WRITE cycle to complete. Connect E to VSS if unused. 2.6 Chip-enable input (STM818 only) The chip-enable transmission gate is disabled and E is high impedance (disabled mode) while reset is asserted. During a power-down sequence when VCC passes the reset threshold, the chip-enable transmission gate disables and E immediately becomes high impedance if the voltage at E is high. If E is low when reset asserts, the chip-enable transmission gate will disable 15 µs after reset asserts (see Figure 12). This permits the current WRITE cycle to complete during power-down. Any time a reset is generated, the chip-enable transmission gate remains disabled and E remains high impedance (regardless of E activity) for the reset time-out period. When the chip-enable transmission gate is enabled, the impedance of E appears as a 40 Ω resistor in series with the load at ECON. The propagation delay through the chip-enable transmission gate depends on VCC, the source impedance of the drive connected to E, and the loading on ECON. The chip-enable propagation delay is production tested from the 50% point on E to the 50% point on ECON using a 50 Ω driver and a 50 pF load capacitance (see Figure 39). For minimum propagation delay, minimize the capacitive load at ECON and use a low-output impedance driver. 2.7 Chip-enable output (STM818 only) When the chip-enable transmission gate is enabled, the impedance of ECON is equivalent to a 40 Ω resistor in series with the source driving E. In the disabled mode, the transmission gate is off and an active pull-up connects ECON to VOUT (see Figure 11). This pull-up turns off when the transmission gate is enabled. Figure 11. Chip-enable gating VCC VRST COMPARE trec Generator RST VOUT ECON OUTPUT CONTROL E ECON AI08802 Doc ID 10522 Rev 10 15/43 Operation STM690A/692A/703/704/802/805/817/818/819 Figure 12. Chip-enable waveform VCC ECON RST E VRST VBAT trec 15µs XX trec XX AI08803b 2.8 Power-fail input/output (NOT available on STM818) The Power-fail Input (PFI) is compared to an internal reference voltage (independent from the VRST comparator). If PFI is less than the power-fail threshold (VPFI), the Power-Fail Output (PFO) will go low. This function is intended for use as an undervoltage detector to signal a failing power supply. Typically PFI is connected through an external voltage divider (see Figure 12) to either the unregulated DC input (if it is available) or the regulated output of the VCC regulator. The voltage divider can be set up such that the voltage at PFI falls below VPFI several milliseconds before the regulated VCC input to the STM690A/692A/703/704/802/805/817/818/819 Supervisor or before the microprocessor drops below the minimum operating voltage. This provides several milliseconds of advanced warning that power is about to fail. During battery backup, the power-fail comparator turns off and PFO goes (or remains) low (see Figure 13 below and Figure 14). This occurs after VCC drops below 2.4 V (or VSO). When power returns, PFO is forced high (STM817/819 only), irrespective of VPFI for the WRITE protect time (trec). At the end of this time, the power-fail comparator is enabled and PFO follows PFI. If the comparator is unused, PFI should be connected to VSS and PFO left unconnected. PFO may be connected to MR on the STM703/704/818 so that a low voltage on PFI will generate a reset output. 2.9 Applications information These supervisor circuits are not short-circuit protected. Shorting VOUT to ground excluding power-up transients such as charging a decoupling capacitor - destroys the device. Decouple both VCC and VBAT pins to ground by placing 0.1 µF capacitors as close to the device as possible. 16/43 Doc ID 10522 Rev 10 STM690A/692A/703/704/802/805/817/818/819 Operation Figure 13. Power-fail comparator waveform (STM817/818/819) VCC VRST VSO (or 2.4V) trec PFO (STM817/819) PFO follows PFI PFO follows PFI RST to ECON Delay (STM818) RST ECON (STM818) AI08804a Figure 14. Power-fail comparator waveform (STM690A/692A/703/704/802/805) VCC VRST 2.4V (or VSO) trec PFO PFO follows PFI PFO follows PFI RST AI08832a 2.10 Using a SuperCap™ as a backup power source SuperCaps™ are capacitors with extremely high capacitance values (e.g., 0.47 F) for their size. Figure 15 shows how to use a SuperCap as a backup power source. The SuperCap may be connected through a diode to the 5 V supply. Since VBAT can exceed VCC while VCC is above the reset threshold, there are no special precautions for using these supervisors with a SuperCap. Doc ID 10522 Rev 10 17/43 Operation 2.11 STM690A/692A/703/704/802/805/817/818/819 Negative-going VCC transients The STM690A/692A/703/704/802/805/817/818/819 Supervisors are relatively immune to negative-going VCC transients (glitches). Figure 37 shows typical transient duration versus reset comparator overdrive (for which the STM690A/692A/703/704/802/805/817/818/819 will NOT generate a reset pulse). The graph was generated using a negative pulse applied to VCC, starting at VRST + 0.3 V and ending below the reset threshold by the magnitude indicated (comparator overdrive). The graph indicates the maximum pulse width a negative VCC transient can have without causing a reset pulse. As the magnitude of the transient increases (further below the threshold), the maximum allowable pulse width decreases. Any combination of duration and overdrive which lies under the curve will NOT generate a reset signal. Typically, a VCC transient that goes 100 mV below the reset threshold and lasts 40 µs or less will not cause a reset pulse. A 0.1 µF bypass capacitor mounted as close as possible to the VCC pin provides additional transient immunity. 18/43 Doc ID 10522 Rev 10 STM690A/692A/703/704/802/805/817/818/819 2.12 Operation Battery freshness seal (STM817/818/819) The battery freshness seal disconnects the backup battery from internal circuitry and VOUT until it is needed. This allows an OEM to ensure that the backup battery connected to VBAT will be fresh when the final product is put to use. To enable the freshness seal: 1. Connect a battery to VBAT 2. Ground PFO 3. Bring VCC above the reset threshold and hold it there until reset is deasserted following the reset timeout period and 4. Bring VCC down again (Figure 16) Use the same procedure for the STM818, but ground ECON instead of PFO. Once the battery freshness seal is enabled (disconnecting the backup battery from internal circuitry and anything connected to VOUT), it remains enabled until VCC is brought above VRST. Figure 15. Using a SuperCap™ 5V VCC VOUT To external SRAM STMXXX VBAT RST To µP GND AI08805 Figure 16. Freshness seal enable waveform VRST VCC trec RST ECON (Externally held at 0V) (STM818) PFO (Externally held at 0V) ECON out state latched at 1/2 trec, Freshness Seal enabled PFO out state latched at 1/2 trec, Freshness Seal Enabled (STM817/819) Doc ID 10522 Rev 10 AI08806 19/43 Typical operating characteristics STM690A/692A/703/704/802/805/817/818/819 3 Typical operating characteristics Note: Typical values are at TA = 25 °C. Figure 17. VCC to VOUT on-resistance vs. temperature VCC to V OUT on-resistance ( ) 5.0 VCC = 3.0V 4.0 VCC = 4.5V VCC = 5.5V 3.0 2.0 1.0 0.0 –40 –20 0 20 40 60 80 100 120 Temperature (°C) AI10498 Figure 18. VBAT to VOUT on-resistance vs. temperature VBAT to VOUT on-resistance ( ) 160 140 120 100 80 60 VBAT = 2.0V 40 VBAT = 3.0V VBAT = 3.3V 20 VBAT = 3.6V 0 –40 –20 0 20 40 60 Temperature (°C) 20/43 Doc ID 10522 Rev 10 80 100 120 AI09140b STM690A/692A/703/704/802/805/817/818/819 Typical operating characteristics Figure 19. Supply current vs. temperature (no load) 30 Supply Current (µA) 25 20 15 VCC = 2.7V VCC = 3.0V VCC = 3.6V VCC = 4.5V VCC = 5.5V 10 5 0 –40 –20 0 20 40 60 80 100 120 Temperature (°C) AI09141b Figure 20. Battery current vs. temperature Battery Supply Current (nA) 1000 100 VBAT = 2.0V VBAT = 3.0V VBAT = 3.6V 10 1 0.1 –40 –20 0 20 40 60 80 100 120 Temperature (°C) AI10499 Doc ID 10522 Rev 10 21/43 Typical operating characteristics STM690A/692A/703/704/802/805/817/818/819 Figure 21. VPFI threshold vs. temperature 1.270 1.265 VCC = 3.0V VCC = 4.5V VCC = 4.75V VCC = 5.5V VPFI Threshold (V) 1.260 1.255 1.250 1.245 1.240 1.235 1.230 1.225 –40 –20 0 20 40 60 80 100 120 Temperature (°C) AI09142c Figure 22. Reset comparator propagation delay vs. temperature (other than STM817/818/819) 30 28 Propagation Delay (µs) 26 24 22 20 18 16 14 12 10 –40 –20 0 20 40 60 Temperature (°C) 22/43 Doc ID 10522 Rev 10 80 100 120 AI09143b STM690A/692A/703/704/802/805/817/818/819 Typical operating characteristics Figure 23. Reset comparator propagation delay vs. temperature (VBAT = 3.0 V; STM817/818/819) 350 1v/ms Propagation Delay (µs) 300 10V/ms 250 200 150 100 50 0 –40 –20 0 20 40 60 80 100 120 Temperature (°C) AI11100 Figure 24. Power-up tREC vs. temperature 240 235 trec (ms) 230 VCC = 3.0V 225 VCC = 4.5V VCC = 5.5V 220 215 210 –40 –20 0 20 40 60 80 Temperature (°C) Doc ID 10522 Rev 10 100 120 AI09144b 23/43 Typical operating characteristics STM690A/692A/703/704/802/805/817/818/819 Figure 25. Normalized reset threshold vs. temperature Normalized Reset Threshold 1.004 1.002 1.000 0.998 0.996 –40 –20 0 20 40 60 80 100 120 Temperature (°C) AI09145b Figure 26. Watchdog time-out period vs. temperature Watchdog Time-out Period (sec) 1.90 1.85 1.80 1.75 VCC = 3.0V VCC = 4.5V VCC = 5.5V 1.70 1.65 1.60 –40 –20 0 20 40 60 Temperature (°C) 24/43 Doc ID 10522 Rev 10 80 100 120 AI09146b STM690A/692A/703/704/802/805/817/818/819 Typical operating characteristics Figure 27. E to ECON on-resistance vs. temperature 60 E to ECON On-Resistance ( ) 50 40 30 VCC = 3.0V VCC = 4.5V VCC = 5.5V 20 10 0 –40 –20 0 20 40 60 80 100 120 Temperature (°C) AI09147b Figure 28. PFI to PFO propagation delay vs. temperature PFI to PFO Propagation Delay (µs) 4.0 VCC = 3.0V VCC = 3.6V 3.0 VCC = 4.5V VCC = 5.5V 2.0 1.0 0.0 –40 –20 0 20 40 60 80 100 120 Temperature (°C) AI09148b Doc ID 10522 Rev 10 25/43 Typical operating characteristics STM690A/692A/703/704/802/805/817/818/819 Figure 29. Output voltage vs. load current (VCC = 5 V; VBAT = 2.8 V; TA = 25 °C) 5.00 VOUT (V) 4.98 4.96 4.94 0 10 20 30 40 50 IOUT (mA) AI10496 Figure 30. Output voltage vs. load current (VCC = 0 V; VBAT = 2.8 V; TA = 25 °C) 2.80 2.78 VOUT (V) 2.76 2.74 2.72 2.70 2.68 2.66 0.0 0.2 0.4 0.6 IOUT (mA) 26/43 Doc ID 10522 Rev 10 0.8 1.0 AI10497 STM690A/692A/703/704/802/805/817/818/819 Typical operating characteristics Figure 31. RST output voltage vs. supply voltage VRST (V) VRST VCC 4 4 3 3 2 2 1 1 0 0 VCC (V) 5 5 500ms/div AI09149b Figure 32. RST output voltage vs. supply voltage 5 VRST VCC VRST (V) 4 4 3 3 2 2 1 1 VCC (V) 5 0 0 500ms/div Doc ID 10522 Rev 10 AI09150b 27/43 Typical operating characteristics STM690A/692A/703/704/802/805/817/818/819 Figure 33. RST response time (assertion) 5V 1V/div VCC 4V 5V 4V RST 1V/div 0V AI09151b 5µs/div Figure 34. RST response time (assertion) 5V VCC 4V 1V/div 4V RST 1V/div 0V 5µs/div 28/43 Doc ID 10522 Rev 10 AI09152b STM690A/692A/703/704/802/805/817/818/819 Typical operating characteristics Figure 35. Power-fail comparator response time (assertion) 5V 1V/div PFO 0V 1.3V PFI 500mV/div 0V 500ns/div AI09153b Figure 36. Power-fail comparator response time (de-assertion) 5V 1V/div PFO 0V 1.3V PFI 500mV/div 0V 500ns/div Doc ID 10522 Rev 10 AI09154b 29/43 Typical operating characteristics STM690A/692A/703/704/802/805/817/818/819 Figure 37. Maximum transient duration vs. reset threshold overdrive 6000 Transient Duration (µs) 5000 4000 Reset occurs above the curve. 3000 2000 1000 0 0.001 0.01 0.1 1 10 Reset Comparator Overdrive, VRST – VCC (V) AI09156b Figure 38. E to ECON propagation delay vs. temperature E to ECON Propagation Delay (ns) 4.0 3.0 2.0 VCC = 3.0V VCC = 4.5V VCC = 5.5V 1.0 0.0 –40 –20 0 20 40 60 Temperature (°C) 30/43 Doc ID 10522 Rev 10 80 100 120 AI09157b STM690A/692A/703/704/802/805/817/818/819 4 Maximum ratings Maximum ratings Stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 5. Absolute maximum ratings Symbol TSTG TSLD(1) VIO Parameter Storage temperature (VCC off) Lead solder temperature for 10 seconds Input or output voltage Value Unit –55 to 150 °C 260 °C –0.3 to VCC +0.3 V VCC/VBAT Supply voltage –0.3 to 6.0 V IO Output current 20 mA PD Power dissipation 320 mW 1. Reflow at peak temperature of 260 °C. The time above 255 °C must not exceed 30 seconds. Doc ID 10522 Rev 10 31/43 DC and AC parameters 5 STM690A/692A/703/704/802/805/817/818/819 DC and AC parameters This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the measurement conditions summarized in Table 6: Operating and AC measurement conditions. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. Table 6. Operating and AC measurement conditions STM690A/692A/703/704/802/805/ 817/818/819 Unit VCC/VBAT supply voltage 1.0 to 5.5 V Ambient operating temperature (TA) –40 to 85 °C ≤5 ns Input pulse voltages 0.2 to 0.8VCC V Input and output timing ref. voltages 0.3 to 0.7VCC V Parameter Input rise and fall times Figure 39. E to ECON propagation delay test circuit VCC VCC VBAT 3.6V STMXXX 25 Equivalent Source Impedance E 50 50 ECON Cable 50pF CL(1) 50 GND AI08854 1. CL includes load capacitance and scope probe capacitance. 32/43 Doc ID 10522 Rev 10 STM690A/692A/703/704/802/805/817/818/819 DC and AC parameters Figure 40. AC testing input/output waveforms 0.8VCC 0.7VCC 0.3VCC 0.2VCC AI02568 Figure 41. MR timing waveform MR tMLRL RST (1) tMLMH trec AI07837a 1. RST for STM805. Figure 42. Watchdog timing VCC RST trec tWD WDI AI07891 Doc ID 10522 Rev 10 33/43 DC and AC parameters Table 7. STM690A/692A/703/704/802/805/817/818/819 DC and AC characteristics Alternative Test condition(1) Min Operating voltage TA = –40 to +85 °C 1.2(3) VCC supply current Excluding IOUT (VCC < 5.5 V) ICC VCC supply current in battery backup mode IBAT(4) VBAT supply current in battery backup mode Sym VCC , VBAT(2) VOUT1 VOUT2 Description VOUT voltage (active) VOUT voltage (battery backup) Max Unit 5.5 V 25 60 µA Excluding IOUT (VBAT = 2.3 V, VCC = 2.0 V, MR = VCC) 25 35 µA Excluding IOUT (VBAT = 3.6 V) 0.4 1.0 µA IOUT1 = 5 mA(5) VCC – 0.03 VCC – 0.015 V IOUT1 = 75 mA VCC – 0.3 VCC – 0.15 V IOUT1 = 250 µA, VCC > 2.5 V(5) VCC – 0.0015 VCC – 0.0006 V IOUT2 = 250 µA, VBAT = 2.3 V VBAT – 0.1 VBAT – 0.034 V VBAT – 0.14 V IOUT2 = 1 mA, VBAT = 2.3 V ILI Typ VCC to VOUT on-resistance 3 VBAT to VOUT on-resistance 100 4 Ω Ω Input leakage current (MR) 4.5 V < VCC < 5.5 V 75 125 300 µA Input leakage current (PFI) 0 V < VIN < VCC –25 2 +25 nA 120 160 µA Input leakage current (WDI)(6) WDI = VCC , time average WDI = GND, time average –20 –15 µA VIH Input high voltage (MR) 4.5 V < VCC < 5.5 V 2.0 V VIH Input high voltage (WDI) VRST (max) < VCC < 5.5 V 0.7VCC V VIL Input low voltage (MR) 4.5 V < VCC < 5.5 V 0.8 V VIL Input low voltage (WDI) VRST (max) < VCC < 5.5 V 0.3VCC V VCC = VRST (max), ISINK = 3.2 mA 0.3 V VCC = VRST (max), IOUT = 1.6 mA, E = 0 V 0.2VCC V ISINK = 50 µA, VCC = 1.0 V, VBAT = VCC , TA = 0°C to 85°C 0.3 V ISINK = 100 µA, VCC = 1.2 V, VBAT = VCC 0.3 V Output low voltage (PFO, RST, RST) VOL VOL 34/43 Output low voltage (ECON) Output low voltage (RST) Doc ID 10522 Rev 10 STM690A/692A/703/704/802/805/817/818/819 Table 7. Sym VOH VOH VOHB DC and AC parameters DC and AC characteristics (continued) Alternative Description Test condition(1) Min Output high voltage (RST, RST) ISOURCE = 1 mA VCC = VRST (max) 2.4 V Output high voltage (ECON) VCC = VRST (max), IOUT = 1.6 mA, E= VCC 0.8VCC V Output high voltage (PFO) ISOURCE = 75 µA, VCC = VRST (max) 0.8VCC V Output high voltage Typ Max Unit ISOURCE = 4 µA, VCC = 1.1 V, VBAT = VCC , TA = 0°C to 85°C 0.8 V ISOURCE = 4 µA, VCC = 1.2 V, VBAT = VCC 0.9 V VOH battery backup (RST, RST) ISOURCE = 100 µA, VCC = 0, VBAT = 2.8 V 0.8VBAT V VOH battery backup (ECON) ISOURCE = 75 µA, VCC = 0, VBAT = 2.8 V 0.8VBAT V Power-fail comparator (NOT available on STM818) VPFI PFI input threshold tPFD PFI to PFO propagation delay ISC PFO output short to GND current PFI falling (VCC = 5 V) All other versions 1.20 1.25 1.30 V STM802 1.225 1.250 1.275 V 2 VCC = 5 V, VPFO = 0 V 0.1 0.75 µs 2.0 mA Battery switchover VSO Battery backup switchover voltage(7)(8) (VCC < VBAT & VCC < VRST) Power-down Power-up VRST > VBAT VBAT V VRST < VBAT VRST V VRST > VBAT VBAT V VRST < VBAT VRST V 40 mV Hysteresis Reset thresholds VRST Reset threshold(9) STM690A/703, STM8XXL 4.50 4.65 4.75 V STM692A/704, STM8XXM 4.25 4.40 4.50 V Reset threshold hysteresis VCC to RST delay (from VRST, VCC falling at 10 V/ms) STM817/818/819 Doc ID 10522 Rev 10 25 mV 100 µs 35/43 DC and AC parameters Table 7. Sym STM690A/692A/703/704/802/805/817/818/819 DC and AC characteristics (continued) Alternative tREC Description Test condition(1) RST pulse width Min Typ Max Unit 140 200 280 ms Push-button reset input (STM703/704/819) tMLMH tMR MR pulse width tMLMR tMRD MR to RST output delay STM703/704 150 ns STM819 1 µs STM703/704 250 ns STM819 120 ns MR glitch immunity STM819 100 ns MR pull-up resistor MR = 0 V, VCC = 5 V 45 63 85 kΩ 1.60 2.24 s Watchdog timer (NOT available on STM703/704/819) tWD Watchdog timeout period VRST (max) < VCC < 5.5 V 1.12 WDI pulse width VRST (max) < VCC < 5.5 V 50 ns Chip-enable gating (STM818 only) VCC = VRST (max) 40 150 Ω 4.5 V < VCC < 5.5 V 2 7 ns Reset to ECON high delay (Power-down) 15 ECON short circuit current VCC = 5 V, disable mode, E = logic high, ECON = 0 V E to ECON resistance E to ECON propagation delay 0.1 0.75 µs 2.0 mA 1. Valid for ambient operating temperature: TA = –40 to 85 °C; VCC = 4.75 V to 5.5 V for “L” versions; VCC = 4.5 V to 5.5 V for “M” versions; and VBAT = 2.8 V (except where noted). 2. VCC supply current, logic input leakage, watchdog functionality, push-button reset functionality, PFI functionality, state of RST and RST tested at VBAT = 3.6 V, and VCC = 5.5 V. The state of RST or RST and PFO is tested at VCC = VCC (min). Either VCC or VBAT can go to 0 V if the other is greater than 2.0 V. 3. VCC (min) = 1.0 V for TA = 0 °C to +85 °C. 4. Tested at VBAT = 3.6 V, VCC = 3.5 V and 0 V. 5. Guaranteed by design. 6. WDI input is designed to be driven by a three-state output device. To float WDI, the “high impedance mode” of the output device must have a maximum leakage current of 10 µA and a maximum output capacitance of 200 pF. The output device must also be able to source and sink at least 200 µA when active. 7. When VBAT > VCC > VRST, VOUT remains connected to VCC until VCC drops below VRST. 8. When VRST > VCC > VBAT, VOUT remains connected to VCC until VCC drops below the battery voltage (VBAT) – 75 mV. 9. For VCC falling. 36/43 Doc ID 10522 Rev 10 STM690A/692A/703/704/802/805/817/818/819 6 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Doc ID 10522 Rev 10 37/43 Package mechanical data STM690A/692A/703/704/802/805/817/818/819 Figure 43. SO8 - 8-lead plastic small outline, 150 mils body width, package mechanical drawing A2 A C B ddd e D 8 E H 1 A1 L SO-A Note: Drawing is not to scale. Table 8. SO8 - 8-lead plastic small outline, 150 mils body width, package mechanical data mm inches Symbol Typ Min Max Typ Min Max A - 1.35 1.75 - 0.053 0.069 A1 - 0.10 0.25 - 0.004 0.010 B - 0.33 0.51 - 0.013 0.020 C - 0.19 0.25 - 0.007 0.010 D - 4.80 5.00 - 0.189 0.197 ddd - - 0.10 - - 0.004 E - 3.80 4.00 - 0.150 0.157 e 1.27 - - 0.050 - - H - 5.80 6.20 - 0.228 0.244 h - 0.25 0.50 - 0.010 0.020 L - 0.40 0.90 - 0.016 0.035 α - 0° 8° - 0° 8° N 38/43 8 Doc ID 10522 Rev 10 8 STM690A/692A/703/704/802/805/817/818/819 Package mechanical data Figure 44. TSSOP8 - 8-lead, thin shrink small outline, 3 x 3 mm body size, outline D 8 5 c E1 1 E 4 L A1 A A2 L1 CP b Note: e TSSOP8BM Drawing is not to scale. Table 9. TSSOP8 - 8-lead, thin shrink small outline, 3 x 3 mm body size, mechanical data mm inches Symbol Typ Min Max Typ Min Max A - - 1.10 - - 0.043 A1 - 0.05 0.15 - 0.002 0.006 A2 0.85 0.75 0.95 0.034 0.030 0.037 b - 0.25 0.40 - 0.010 0.016 c - 0.13 0.23 - 0.005 0.009 CP - - 0.10 - - 0.004 D 3.00 2.90 3.10 0.118 0.114 0.122 e 0.65 - - 0.026 - - E 4.90 4.65 5.15 0.193 0.183 0.203 E1 3.00 2.90 3.10 0.118 0.114 0.122 L 0.55 0.40 0.70 0.022 0.016 0.030 L1 0.95 - - 0.037 - - α - 0° 6° - 0° 6° N 8 Doc ID 10522 Rev 10 8 39/43 Part numbering 7 STM690A/692A/703/704/802/805/817/818/819 Part numbering Table 10. Ordering information scheme Example: STM690A M 6 E Device type STM690A/692A/703/704/802/805/817/818/819 Threshold voltage STM690A, STM703: blank: VRST = 4.50 V to 4.75 V STM692A, STM704: blank: VRST = 4.25 V to 4.50 V STM8xx: L: VRST = 4.50 V to 4.75 V M: VRST = 4.25 V to 4.50 V Package M = SO8 DS(1) = TSSOP8 Temperature range 6: –40 °C to 85 °C Shipping method E = ECOPACK® package, tubes F = ECOPACK® package, tape & reel 1. Contact local ST sales office for availability. For other options or for more information on any aspect of this device, please contact the ST sales office nearest you. 40/43 Doc ID 10522 Rev 10 STM690A/692A/703/704/802/805/817/818/819 Table 11. Part numbering Marking description Part number Reset threshold Package Topside marking STM690A 4.65 V SO8 690A STM692A 4.40 V SO8 692A STM703 4.65 V SO8 703 STM704 4.40 V SO8 704 STM802L 4.65 V SO8 802L STM802M 4.40 V SO8 802M STM805L 4.65 V SO8 805L STM817L 4.65 V SO8 817L TSSOP8 SO8 STM817M 4.40 V 817M TSSOP8 SO8 STM818L 4.65 V 818L TSSOP8 SO8 STM818M 4.40 V 818M TSSOP8 SO8 STM819L 4.65 V 819L TSSOP8 SO8 STM819M 4.40 V 819M TSSOP8 Doc ID 10522 Rev 10 41/43 Revision history 8 Revision history Table 12. 42/43 STM690A/692A/703/704/802/805/817/818/819 Document revision history Date Revision Changes Oct-2003 1 31-Oct-2003 1.1 22-Dec-2003 2 Reformatted; updated characteristics (cover page, Figure 2, 3, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16, Table 3, 4, 7, 9, 11). 16-Jan-2004 2.1 Add typical characteristics (Figure 18, 19, 21, 22, 24, 25, 26, 27, 28, 31, 32, 33, 34, 35, 36, 37, 38). 08-Apr-2004 2.2 Update characteristics (Figure 12, 22, 28, 32, 33, 34, 37; Table 1, 7). 25-May-2004 3 Remove references to “open drain” (cover page, 4, 7; Table 2); update characteristics (Table 3, 7). 05-Jul-2004 4 Update package availability, pin description; promote document (cover page, Figure 13, 14; Table 3, 7, 10). 29-Sep-2004 5 Clarify root part numbers, pin descriptions (Figure 10, 12, 39; Table 7, 10). 01-Mar-2005 6 Update characteristics (Figure 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38) 20-Jan-2006 7 Correct marking, update lead-free text (Table 10, 11) 21-Oct-2008 8 Reformatted, minor text changes; updated Table 3, 4, 7, 10, Figure 9, 10, 11, 12, 16, 39, Section 6: Package mechanical data. 20-Nov-2009 9 Updated text in Section 6, Table 5. 18-Aug-2010 10 Updated Section 2.4: Backup battery switchover. Initial release. Update DC characteristics (Table 7). Doc ID 10522 Rev 10 STM690A/692A/703/704/802/805/817/818/819 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. 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