STM8L101F2P6TR

STM8L101x1 STM8L101x2 STM8L101x3 8-bit ultra-low power microcontroller with up to 8 Kbytes Flash, multifunction timers, comparators, USART, SPI, I2C Datasheet - production data Features • Main microcontroller features – Supply voltage range 1.65 V to 3.6 V – Low power consumption (Halt: 0.3 µA, Active-halt: 0.8 µA, Dynamic Run: 150 µA/MHz) – STM8 Core with up to 16 CISC MIPS throughput – Temp. range: -40 to 85 °C and 125 °C • Memories – Up to 8 Kbytes of Flash program including up to 2 Kbytes of data EEPROM – Error correction code (ECC) – Flexible write and read protection modes – In-application and in-circuit programming – Data EEPROM capability – 1.5 Kbytes of static RAM • Clock management – Internal 16 MHz RC with fast wakeup time (typ. 4 µs) – Internal low consumption 38 kHz RC driving both the IWDG and the AWU • Reset and supply management – Ultra-low power POR/PDR – Three low-power modes: Wait, Active-halt, Halt • Interrupt management – Nested interrupt controller with software priority control – Up to 29 external interrupt sources • I/Os – Up to 30 I/Os, all mappable on external interrupt vectors – I/Os with programmable input pull-ups, high sink/source capability and one LED driver infrared output May 2017 This is information on a product in full production. UFQFPN32 5 x 5 mm UFQFPN28 4 x 4 mm LQFP32 7x7 mm TSSOP20 6.5 x 6.4 mm UFQFPN20 3 x 3 mm • Peripherals – Two 16-bit general purpose timers (TIM2 and TIM3) with up and down counter and 2 channels (used as IC, OC, PWM) – One 8-bit timer (TIM4) with 7-bit prescaler – Infrared remote control (IR) – Independent watchdog – Auto-wakeup unit – Beeper timer with 1, 2 or 4 kHz frequencies – SPI synchronous serial interface – Fast I2C Multimaster/slave 400 kHz – USART with fractional baud rate generator – 2 comparators with 4 inputs each • Development support – Hardware single wire interface module (SWIM) for fast on-chip programming and non intrusive debugging – In-circuit emulation (ICE) • 96-bit unique ID Table 1. Device summary Reference Part numbers STM8L101x1 STM8L101F1 STM8L101x2 STM8L101F2, STM8L101G2 STM8L101x3 STM8L101F3, STM8L101G3, STM8L101K3 DocID15275 Rev 16 1/88 www.st.com Contents STM8L101x1 STM8L101x2 STM8L101x3 Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 Product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1 Central processing unit STM8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.2 Development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.3 Single wire data interface (SWIM) and debug module . . . . . . . . . . . . . . . .11 3.4 Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.5 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.6 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.7 Voltage regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.8 Clock control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.9 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.10 Auto-wakeup counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.11 General purpose and basic timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.12 Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.13 Infrared (IR) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.14 Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.15 USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.16 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.17 I²C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5 Memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6 Interrupt vector mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7 Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8 Unique ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2/88 DocID15275 Rev 16 STM8L101x1 STM8L101x2 STM8L101x3 9 Electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 9.4 10 Contents 9.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 9.3.2 Power-up / power-down operating conditions . . . . . . . . . . . . . . . . . . . . 41 9.3.3 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9.3.4 Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.3.5 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 9.3.6 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 9.3.7 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 9.3.8 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 9.3.9 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 10.1 UFQFPN32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 10.2 LQFP32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 10.3 UFQFPN28 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 10.4 UFQFPN20 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 10.5 TSSOP20 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 11 Device ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 12 STM8 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 12.1 Emulation and in-circuit debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . 80 12.2 Software tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 12.3 12.2.1 STM8 toolset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 12.2.2 C and assembly toolchains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 DocID15275 Rev 16 3/88 4 Contents 13 4/88 STM8L101x1 STM8L101x2 STM8L101x3 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 DocID15275 Rev 16 STM8L101x1 STM8L101x2 STM8L101x3 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 STM8L101xx device feature summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Legend/abbreviation for table 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 STM8L101xx pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Flash and RAM boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 I/O Port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 General hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 CPU/SWIM/debug module/interrupt controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Unique ID registers (96 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Total current consumption in Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Total current consumption in Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Total current consumption and timing in Halt and Active-halt mode at VDD = 1.65 V to 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Flash program memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Output driving current (High sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Output driving current (true open drain ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Output driving current (PA0 with high sink LED driver capability). . . . . . . . . . . . . . . . . . . . 51 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 I2C characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 EMS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 EMI data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 UFQFPN32 - 32-lead ultra thin fine pitch quad flat no-lead package (5 x 5), package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 LQFP32- 32-pin low profile quad flat package (7x7), package mechanical data . . . . . . . . 68 UFQFPN28 - 28-lead ultra thin fine pitch quad flat no-lead package (4 x 4), package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 UFQFPN20 - 20-lead, 3x3 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 TSSOP20 - 20-lead thin shrink small package mechanical data . . . . . . . . . . . . . . . . . . . . 76 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 DocID15275 Rev 16 5/88 5 List of figures STM8L101x1 STM8L101x2 STM8L101x3 List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. 6/88 STM8L101xx device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Standard 20-pin UFQFPN package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 20-pin UFQFPN package pinout for STM8L101F1U6ATR, STM8L101F2U6ATR and STM8L101F3U6ATR part numbers. . . . . . . . . . . . . . . . . . . . . . 16 20-pin TSSOP package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Standard 28-pin UFQFPN package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 28-pin UFQFPN package pinout for STM8L101G3U6ATR and STM8L101G2U6ATR part numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 32-pin package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 IDD(RUN) vs. VDD, fCPU = 2 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 IDD(RUN) vs. VDD, fCPU = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 IDD(WAIT) vs. VDD, fCPU = 2 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 IDD(WAIT) vs. VDD, fCPU = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Typ. IDD(Halt) vs. VDD, fCPU = 2 MHz and 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Typical HSI frequency vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Typical HSI accuracy vs. temperature, VDD = 3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Typical HSI accuracy vs. temperature, VDD = 1.65 V to 3.6 V. . . . . . . . . . . . . . . . . . . . . . 46 Typical LSI RC frequency vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Typical VIL and VIH vs. VDD (High sink I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Typical VIL and VIH vs. VDD (true open drain I/Os). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Typical pull-up resistance RPU vs. VDD with VIN=VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Typical pull-up current IPU vs. VDD with VIN=VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Typ. VOL at VDD = 3.0 V (High sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Typ. VOL at VDD = 1.8 V (High sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Typ. VOL at VDD = 3.0 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Typ. VOL at VDD = 1.8 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Typ. VDD - VOH at VDD = 3.0 V (High sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Typ. VDD - VOH at VDD = 1.8 V (High sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Typical NRST pull-up resistance RPU vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Typical NRST pull-up current Ipu vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Recommended NRST pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Typical application with I2C bus and timing diagram 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 UFQFPN32 - 32-lead ultra thin fine pitch quad flat no-lead package outline (5 x 5). . . . . . 64 UFQFPN32 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 UFQFPN32 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 LQFP32 - 32-pin low profile quad flat package outline (7 x 7) . . . . . . . . . . . . . . . . . . . . . . 67 LQFP32 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 LQFP32 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 UFQFPN28 - 28-lead ultra thin fine pitch quad flat no-lead package outline (4 x 4 mm) . . 70 UFQFPN28 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 UFQFPN28 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 UFQFPN20 - 20-lead, 3x3 mm, 0.5 mm pitch, ultra thin fine pitch quad flat DocID15275 Rev 16 STM8L101x1 STM8L101x2 STM8L101x3 Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. List of figures package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 UFQFPN20 - 20-lead, 3x3 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 UFQFPN20 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 TSSOP20 - 20-lead thin shrink small package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 TSSOP20 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 TSSOP20 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 STM8L101xx ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 DocID15275 Rev 16 7/88 7 Introduction 1 STM8L101x1 STM8L101x2 STM8L101x3 Introduction This datasheet provides the STM8L101x1 STM8L101x2 STM8L101x3 pinout, ordering information, mechanical and electrical device characteristics. For complete information on the STM8L101x1 STM8L101x2 STM8L101x3 microcontroller memory, registers and peripherals, please refer to the STM8L reference manual. The STM8L101x1 STM8L101x2 STM8L101x3devices are members of the STM8L lowpower 8-bit family. They are referred to as low-density devices in the STM8L101x1 STM8L101x2 STM8L101x3 microcontroller family reference manual (RM0013) and in the STM8L Flash programming manual (PM0054). All devices of the SM8L product line provide the following benefits: • • • • 8/88 Reduced system cost – Up to 8 Kbytes of low-density embedded Flash program memory including up to 2 Kbytes of data EEPROM – High system integration level with internal clock oscillators and watchdogs. – Smaller battery and cheaper power supplies. Low power consumption and advanced features – Up to 16 MIPS at 16 MHz CPU clock frequency – Less than 150 µA/MH, 0.8 µA in Active-halt mode, and 0.3 µA in Halt mode – Clock gated system and optimized power management Short development cycles – Application scalability across a common family product architecture with compatible pinout, memory map and modular peripherals. – Full documentation and a wide choice of development tools Product longevity – Advanced core and peripherals made in a state-of-the art technology – Product family operating from 1.65 V to 3.6 V supply. DocID15275 Rev 16 STM8L101x1 STM8L101x2 STM8L101x3 2 Description Description The STM8L101x1 STM8L101x2 STM8L101x3 low-power family features the enhanced STM8 CPU core providing increased processing power (up to 16 MIPS at 16 MHz) while maintaining the advantages of a CISC architecture with improved code density, a 24-bit linear addressing space and an optimized architecture for low power operations. The family includes an integrated debug module with a hardware interface (SWIM) which allows non-intrusive in-application debugging and ultrafast Flash programming. All STM8L101xx microcontrollers feature low power low-voltage single-supply program Flash memory. The 8-Kbyte devices embed data EEPROM. The STM8L101xx low power family is based on a generic set of state-of-the-art peripherals. The modular design of the peripheral set allows the same peripherals to be found in different ST microcontroller families including 32-bit families. This makes any transition to a different family very easy, and simplified even more by the use of a common set of development tools. All STM8L low power products are based on the same architecture with the same memory mapping and a coherent pinout. Table 2. STM8L101xx device feature summary Features Flash STM8L101xx 2 Kbytes of Flash program memory 4 Kbytes of Flash program memory 8 Kbytes of Flash program memory including up to 2 Kbytes of Data EEPROM RAM 1.5 Kbytes Peripheral functions Independent watchdog (IWDG), Auto-wakeup unit (AWU), Beep, Serial peripheral interface (SPI), Inter-integrated circuit (I²C), Universal synchronous / asynchronous receiver / transmitter (USART), 2 comparators, Infrared (IR) interface Timers Two 16-bit timers, one 8-bit timer Operating voltage 1.65 to 3.6 V Operating temperature Packages -40 to +85 °C UFQFPN20 3x3 UFQFPN28 4x 4 UFQFPN20 3x3 TSSOP20 4.4 x 6.4 DocID15275 Rev 16 -40 to +85 °C or -40 to +125 °C UFQFPN28 4x4 UFQFPN20 3x3 UFQFPN32 LQFP32 9/88 22 Product overview 3 STM8L101x1 STM8L101x2 STM8L101x3 Product overview Figure 1. STM8L101xx device block diagram #9'' 0+]LQW5& N+]LQW5& 9'' &ORFN FRQWUROOHU &ORFNV WRFRUHDQG SHULSKHUDOV 5HVHW ,QIUDUHGLQWHUIDFH 3$>@ 3RUW$ 3%>@ 3RUW% 3&>@ 3RUW& 3'>@ 3RUW' &203B&+>@ .E\WHV 65$0 $GGUHVVDQGGDWDEXV ,5B7,0 86$57 5;7;&. ,ð& PXOWLPDVWHU 6'$6&/ 63, 026,0,62 6&.166 ELW7LPHU 7,0B&+>@ 7,0B75,* ELW7LPHU 7,0B&+>@ 7,0B75,* ELW7LPHU &203 ,:'* &203 %HHSHU &203B5() &203B&+>@ 1567 8SWR.E\WHV )ODVKPHPRU\ LQFOXGLQJ XSWR.E\WHV GDWD((3520 1HVWHGLQWHUUXSW FRQWUROOHU XSWRH[WHUQDO LQWHUUXSWV 'HEXJPRGXOH 6:,0 9'' 9WR9 966 3253'5 670 &RUH XSWR0+] 6:,0 3RZHU 9ROWUHJ $:8 %((3 069 Legend: AWU: Auto-wakeup unit Int. RC: internal RC oscillator I²C: Inter-integrated circuit multimaster interface POR/PDR: Power on reset / power down reset SPI: Serial peripheral interface SWIM: Single wire interface module USART: Universal synchronous / asynchronous receiver / transmitter IWDG: Independent watchdog 10/88 DocID15275 Rev 16 STM8L101x1 STM8L101x2 STM8L101x3 3.1 Product overview Central processing unit STM8 The 8-bit STM8 core is designed for code efficiency and performance. It features 21 internal registers, 20 addressing modes including indexed, indirect and relative addressing, and 80 instructions. 3.2 Development tools Development tools for the STM8 microcontrollers include: • The STice emulation system offering tracing and code profiling • The STVD high-level language debugger including C compiler, assembler and integrated development environment • The STVP Flash programming software The STM8 also comes with starter kits, evaluation boards and low-cost in-circuit debugging/programming tools. 3.3 Single wire data interface (SWIM) and debug module The debug module with its single wire data interface (SWIM) permits non-intrusive real-time in-circuit debugging and fast memory programming. The Single wire interface is used for direct access to the debugging module and memory programming. The interface can be activated in all device operation modes. The non-intrusive debugging module features a performance close to a full-featured emulator. Beside memory and peripherals, also CPU operation can be monitored in realtime by means of shadow registers. 3.4 Interrupt controller The STM8L101xx features a nested vectored interrupt controller: • Nested interrupts with 3 software priority levels • 26 interrupt vectors with hardware priority • Up to 29 external interrupt sources on 10 vectors • Trap and reset interrupts. DocID15275 Rev 16 11/88 22 Product overview 3.5 STM8L101x1 STM8L101x2 STM8L101x3 Memory The STM8L101xx devices have the following main features: • 1.5 Kbytes of RAM • The EEPROM is divided into two memory arrays (see the STM8L reference manual for details on the memory mapping): – Up to 8 Kbytes of low-density embedded Flash program including up to 2 Kbytes of data EEPROM. Data EEPROM and Flash program areas can be write protected independently by using the memory access security mechanism (MASS). – 64 option bytes (one block) of which 5 bytes are already used for the device. Error correction code is implemented on the EEPROM. 3.6 Low power modes To minimize power consumption, the product features three low power modes: 3.7 • Wait mode: CPU clock stopped, selected peripherals at full clock speed. • Active-halt mode: CPU and peripheral clocks are stopped. The programmable wakeup time is controlled by the AWU unit. • Halt mode: CPU and peripheral clocks are stopped, the device remains powered on. The RAM content is preserved. Wakeup is triggered by an external interrupt. Voltage regulators The STM8L101xx embeds an internal voltage regulator for generating the 1.8 V power supply for the core and peripherals. This regulator has two different modes: main voltage regulator mode (MVR) and low power voltage regulator mode (LPVR). When entering Halt or Active-halt modes, the system automatically switches from the MVR to the LPVR in order to reduce current consumption. 3.8 Clock control The STM8L101xx embeds a robust clock controller. It is used to distribute the system clock to the core and the peripherals and to manage clock gating for low power modes. This system clock is a 16-MHz High Speed Internal RC oscillator (HSI RC), followed by a programmable prescaler. In addition, a 38 kHz low speed internal RC oscillator is used by the independent watchdog (IWDG) and Auto-wakeup unit (AWU). 3.9 Independent watchdog The independent watchdog (IWDG) peripheral can be used to resolve processor malfunctions due to hardware or software failures. It is clocked by the 38 kHz LSI internal RC clock source, and thus stays active even in case of a CPU clock failure. 12/88 DocID15275 Rev 16 STM8L101x1 STM8L101x2 STM8L101x3 3.10 Product overview Auto-wakeup counter The auto-wakeup (AWU) counter is used to wakeup the device from Active-halt mode. 3.11 General purpose and basic timers STM8L101xx devices contain two 16-bit general purpose timers (TIM2 and TIM3) and one 8-bit basic timer (TIM4). 16-bit general purpose timers The 16-bit timers consist of 16-bit up/down auto-reload counters driven by a programmable prescaler. They perform a wide range of functions, including: • Time base generation • Measuring the pulse lengths of input signals (input capture) • Generating output waveforms (output compare, PWM and One pulse mode) • Interrupt capability on various events (capture, compare, overflow, break, trigger) 8-bit basic timer The 8-bit timer consists of an 8-bit up auto-reload counter driven by a programmable prescaler. It can be used for timebase generation with interrupt generation on timer overflow. 3.12 Beeper The STM8L101xx devices include a beeper function used to generate a beep signal in the range of 1, 2 or 4 kHz when the LSI clock is operating at a frequency of 38 kHz. 3.13 Infrared (IR) interface The STM8L101xx devices contain an infrared interface which can be used with an IR LED for remote control functions. Two timer output compare channels are used to generate the infrared remote control signals. 3.14 Comparators The STM8L101xx features two zero-crossing comparators (COMP1 and COMP2) sharing the same current bias and voltage reference. The voltage reference can be internal (comparison with ground) or external (comparison to a reference pin voltage). Each comparator is connected to 4 channels, which can be used to generate interrupt, timer input capture or timer break. Their polarity can be inverted. DocID15275 Rev 16 13/88 22 Product overview 3.15 STM8L101x1 STM8L101x2 STM8L101x3 USART The USART interface (USART) allows full duplex, asynchronous communications with external devices requiring an industry standard NRZ asynchronous serial data format. It offers a very wide range of baud rates. 3.16 SPI The serial peripheral interface (SPI) provides half/ full duplex synchronous serial communication with external devices. It can be configured as the master and in this case it provides the communication clock (SCK) to the external slave device. The interface can also operate in multi-master configuration. 3.17 I²C The inter-integrated circuit (I2C) bus interface is designed to serve as an interface between the microcontroller and the serial I2C bus. It provides multi-master capability, and controls all I²C bus-specific sequencing, protocol, arbitration and timing. It manages standard and fast speed modes. 14/88 DocID15275 Rev 16 STM8L101x1 STM8L101x2 STM8L101x3 4 Pin description Pin description 3$+6 3&+6 3&+6 3&+6 3& Figure 2. Standard 20-pin UFQFPN package pinout                 3& 3%+6 3%+6 3%+6 3%+6 3'+6 3%+6 3%+6 3%+6 3%+6 15673$+6 3$+6 3$+6 966 9'' 069 1. HS corresponds to 20 mA high sink/source capability. 2. High sink LED driver capability available on PA0. Refer to the description of the IR_CR register in the STM8L reference manual (RM0013). Note: The COMP_REF pin is not available in this standard 20-pin UFQFPN package. It is available on Port A6 in the Figure 3: 20-pin UFQFPN package pinout for STM8L101F1U6ATR, STM8L101F2U6ATR and STM8L101F3U6ATR part numbers. DocID15275 Rev 16 15/88 22 Pin description STM8L101x1 STM8L101x2 STM8L101x3 3$+6 3&+6 3&+6 3&+6 3& Figure 3. 20-pin UFQFPN package pinout for STM8L101F1U6ATR, STM8L101F2U6ATR and STM8L101F3U6ATR part numbers                 3& 3%+6 3%+6 3%+6 3%+6 3'+6 3%+6 3%+6 3%+6 3%+6 15673$+6 3$+6 3$+6 966 9'' 069 1. Please refer to the warning below. 2. HS corresponds to 20 mA high sink/source capability. 3. High sink LED driver capability available on PA0. Refer to the description of the IR_CR register in the STM8L reference manual (RM0013). Warning: 16/88 For the STM8L101F1U6ATR, STM8L101F2U6ATR and STM8L101F3U6ATR part numbers (devices with COMP_REF pin), all ports available on 32-pin packages must be considered as active ports. To avoid spurious effects, the user has to configure them as input pull-up. A small increase in consumption (typ. < 300 µA) may occur during the power up and reset phase until these ports are properly configured. DocID15275 Rev 16 STM8L101x1 STM8L101x2 STM8L101x3 Pin description Figure 4. 20-pin TSSOP package pinout 0#(3   0#(3 0#(3   0# 0!(3   0# .2340!(3   0" 0!(3   0"(3 0!(3   0"(3 633   0"(3 6$$   0"(3 0$(3   0"(3 0"(3   0"(3 069 1. HS corresponds to 20 mA high sink/source capability. 2. High sink LED driver capability available on PA0. Refer to the description of the IR_CR register in the STM8L reference manual (RM0013). 3&+6 3& 3&+6 3&+6 3&+6 3&+6 3$+6 Figure 5. Standard 28-pin UFQFPN package pinout 3$+6   3'+6 3$+6   3%+6 3$+6   3%+6 3$+6   3%+6 966   3%+6 9''  3%+6 3& 3%+6 3%+6       3%+6  3'+6  3'+6         3'+6  3'+6 15673$+6 069 1. HS corresponds to 20 mA high sink/source capability. 2. High sink LED driver capability available on PA0. Refer to the description of the IR_CR register in the STM8L reference manual (RM0013). Note: The COMP_REF pin is not available in this standard 28-pin UFQFPN package. It is available on Port A6 in the Figure 6: 28-pin UFQFPN package pinout for STM8L101G3U6ATR and STM8L101G2U6ATR part numbers. DocID15275 Rev 16 17/88 22 Pin description STM8L101x1 STM8L101x2 STM8L101x3 3&+6 3& 3&+6 3&+6 3&+6 3&+6 3$+6 Figure 6. 28-pin UFQFPN package pinout for STM8L101G3U6ATR and STM8L101G2U6ATR part numbers 3$+6   3'+6 3$+6   3%+6 3$+6   3%+6 3$+6   3%+6 966   3%+6 9''  3%+6 3& 3%+6 3%+6       3%+6  3'+6  3'+6         3'+6  3'+6 15673$+6 069 1. HS corresponds to 20 mA high sink/source capability. 2. High sink LED driver capability available on PA0. Refer to the description of the IR_CR register in the STM8L reference manual (RM0013). Warning: 18/88 For the STM8L101G3U6ATR and STM8L101G2U6ATR part numbers (devices with COMP_REF pin), all ports available on 32-pin packages must be considered as active ports. To avoid spurious effects, the user has to configure them as input pull-up. A small increase in consumption (typ. < 300 µA) may occur during the power up and reset phase until these ports are properly configured. DocID15275 Rev 16 STM8L101x1 STM8L101x2 STM8L101x3 Pin description 3& 3& 3&+6 3&+6 3&+6 3&+6 3&+6 3$+6 Figure 7. 32-pin package pinout           3'+6 3$+6   3'+6 3$+6   3'+6 3$+6   3'+6 3$+6   3%+6 3$+6   3%+6 966   3%+6 9''   3%+6 15673$+6 3%+6 3%+6 3%+6 3%+6 3'+6 3'+6 3'+6 3'+6         069 1. Example given for the UFQFPN32 package. The pinout is the same for the LQFP32 package. 2. HS corresponds to 20 mA high sink/source capability. 3. High sink LED driver capability available on PA0. Refer to the description of the IR_CR register in the STM8L reference manual (RM0013). DocID15275 Rev 16 19/88 22 Pin description STM8L101x1 STM8L101x2 STM8L101x3 Table 3. Legend/abbreviation for table 4 Type I= input, O = output, S = power supply Level Input CM = CMOS Output HS = high sink/source (20 mA) Port and control Input configuration Output Reset state float = floating, wpu = weak pull-up T = true open drain, OD = open drain, PP = push pull Bold X (pin state after reset release). Unless otherwise specified, the pin state is the same during the reset phase (i.e. “under reset”) and after internal reset release (i.e. at reset state). Table 4. STM8L101xx pin description wpu Ext. interrupt OD PP 1 1 1 NRST/PA1(2) I/O - X - HS - X Reset PA1 2 2 5 2 2 2 PA2 I/O X X X HS X X Port A2 - 3 - 6 3 3 3 PA3 I/O X X X HS X X Port A3 - - - - 4 4 4 PA4/TIM2_BKIN I/O X X X HS X X Port A4 Timer 2 - break input - - - 5 - 5 PA5/TIM3_BKIN I/O X X X HS X X Port A5 Timer 3 - break input - 3 - - 5 6 PA6/COMP_REF I/O X X X HS X X Port A6 Comparator external reference 4 4 7 6 6 7 VSS S - - - - - - Ground 5 5 8 7 7 8 VDD S - - - - - - Power supply 6 6 9 8 8 9 PD0/TIM3_CH2/ COMP1_CH3 I/O X X X HS X X Port D0 Timer 3 - channel 2 / Comparator 1 channel 3 - - - 9 9 10 PD1/TIM3_ETR/ COMP1_CH4 I/O X X X HS X X Port D1 Timer 3 - trigger / Comparator 1 channel 4 - - - 10 10 11 PD2/ COMP2_CH3 I/O X X X HS X X Port D2 Comparator 2 channel 3 - - - 11 11 12 PD3/ COMP2_CH4 I/O X X X HS X X Port D3 Comparator 2 channel 4 20/88 DocID15275 Rev 16 Main function (after reset) UFQFPN32 or LQFP32 4 High sink/source UFQFPN28 with COMP_REF(1) 1 floating standard UFQFPN28 1 Pin name Type TSSOP20 Output UFQFPN20 with COMP_REF(1) Input standard UFQFPN20 Pin number Alternate function STM8L101x1 STM8L101x2 STM8L101x3 Pin description Table 4. STM8L101xx pin description (continued) OD PP Main function (after reset) I/O X(3) X(3) X HS X X Port B0 Timer 2 - channel 1 / Comparator 1 channel 1 8 8 11 13 13 14 PB1/TIM3_CH1/ COMP1_CH2 I/O X X X HS X X Port B1 Timer 3 - channel 1 / Comparator 1 channel 2 9 9 12 14 14 15 PB2/ TIM2_CH2/ COMP2_CH1/ I/O X X X HS X X Port B2 Timer 2 - channel 2 / Comparator 2 channel 1 10 10 13 15 15 16 PB3/TIM2_ETR/ COMP2_CH2 I/O X X X HS X X Port B3 Timer 2 - trigger / Comparator 2 channel 2 11 11 14 16 16 17 PB4/SPI_NSS(3) I/O X(3) X(3) X HS X X Port B4 SPI master/slave select 12 12 15 17 17 18 PB5/SPI_SCK I/O X X X HS X X Port B5 SPI clock 13 13 16 18 18 19 PB6/SPI_MOSI I/O X X X HS X X Port B6 SPI master out/ slave in 14 14 17 19 19 20 PB7/SPI_MISO I/O X X X HS X X Port B7 SPI master in/ slave out - - - 20 20 21 PD4 I/O X X X HS X X Port D4 - - - - - - 22 PD5 I/O X X X HS X X Port D5 - - - - - - 23 PD6 I/O X X X HS X X Port D6 - - - - - - 24 PD7 I/O X X X HS X X Port D7 - I/O X - X - T(4) Port C0 I2C data Port C1 I2C clock 15 15 18 21 21 25 PC0/I2C_SDA Ext. interrupt High sink/source PB0/TIM2_CH1/ COMP1_CH1 (3) wpu 10 12 12 13 floating 7 Pin name Type 7 UFQFPN32 or LQFP32 UFQFPN28 with COMP_REF(1) Alternate function standard UFQFPN28 TSSOP20 Output UFQFPN20 with COMP_REF(1) Input standard UFQFPN20 Pin number 16 16 19 22 22 26 PC1/I2C_SCL I/O X - X - T(4) 17 17 20 23 23 27 PC2/USART_RX I/O X X X HS X X Port C2 USART receive 18 18 1 24 24 28 PC3/USART_TX I/O X X X HS X X Port C3 USART transmit 19 19 2 25 25 29 PC4/USART_CK/ I/O X CCO X X HS X X Port C4 USART synchronous clock / Configurable clock output DocID15275 Rev 16 21/88 22 Pin description STM8L101x1 STM8L101x2 STM8L101x3 Table 4. STM8L101xx pin description (continued) OD PP X X HS X X Port C5 - - - - 27 27 31 PC6 I/O X X X HS X X Port C6 - X HS(6) Port A0 SWIM input and output /Beep output/Timer Infrared output PA0(5)/SWIM/ 28 28 32 BEEP/IR_TIM (6) I/O X (5) X X X Main function (after reset) Ext. interrupt I/O X High sink/source wpu 26 26 30 PC5 floating - Pin name Type - UFQFPN32 or LQFP32 standard UFQFPN28 - 20 20 3 UFQFPN28 with COMP_REF(1) TSSOP20 Output UFQFPN20 with COMP_REF(1) Input standard UFQFPN20 Pin number Alternate function 1. Please refer to the warning below. 2. At power-up, the PA1/NRST pin is a reset input pin with pull-up. To be used as a general purpose pin (PA1), it can be configured only as a general purpose pin (PA1), it can be configured only as output push-pull, not neither as output opendrain nor as a general purpose input. Refer to Section Configuring NRST/PA1 pin as general purpose output in the STM8L reference manual (RM0013). 3. A pull-up is applied to PB0 and PB4 during the reset phase. These two pins are input floating after reset release. 4. In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer, weak pull-up and protection diode to VDD are not implemented). 5. The PA0 pin is in input pull-up during the reset phase and after reset release. 6. High sink LED driver capability available on PA0. Slope control of all GPIO pins can be programmed except true open drain pins and by default is limited to 2 MHz. Warning: 22/88 For the STM8L101F1U6ATR, STM8L101F2U6ATR, STM8L101F3U6ATR, STM8L101G2U6ATR and STM8L101G3U6ATR part numbers (devices with COMP_REF pin), all ports available on 32-pin packages must be considered as active ports. To avoid spurious effects, the user has to configure them as input pull-up. A small increase in consumption (typ. < 300 µA) may occur during the power up and reset phase until these ports are properly configured. DocID15275 Rev 16 STM8L101x1 STM8L101x2 STM8L101x3 5 Memory and register map Memory and register map Figure 8. Memory map [ [)) [ 5$0 .E\WHV LQFOXGLQJ 6WDFN XSWR E\WHV 5HVHUYHG [)) [ 2SWLRQE\WHV [)) [ [ [ [ [ [)) [ [)) [ 5HVHUYHG 8QLTXH,' 5HVHUYHG  *3,2DQGSHULSKHUDOUHJLVWHUV  5HVHUYHG [()) [) [))) [ [) [ &386:,0'HEXJ,7& 5HJLVWHUV ,QWHUUXSWYHFWRUV /RZGHQVLW\ )ODVKSURJUDPPHPRU\ XSWR.E\WHV LQFOXGLQJ 'DWD((3520 XSWR.E\WHV [))) 069 1. Table 5 lists the boundary addresses for each memory size. The top of the stack is at the RAM end address. 2. Refer to Table 7 for an overview of hardware register mapping, to Table 6 for details on I/O port hardware registers, and to Table 8 for information on CPU/SWIM/debug module controller registers. DocID15275 Rev 16 23/88 33 Memory and register map STM8L101x1 STM8L101x2 STM8L101x3 Table 5. Flash and RAM boundary addresses Memory area Size Start address End address RAM 1.5 Kbytes 0x00 0000 0x00 05FF 2 Kbytes 0x00 8000 0x00 87FF 4 Kbytes 0x00 8000 0x00 8FFF 8 Kbytes 0x00 8000 0x00 9FFF Flash program memory Note: 2 Kbytes of Data EEPROM is only available on devices with 8 Kbytes flash program memory. Table 6. I/O Port hardware register map Register label Register name Reset status 0x00 5000 PA_ODR Port A data output latch register 0x00 0x00 5001 PA_IDR Port A input pin value register 0xxx PA_DDR Port A data direction register 0x00 0x00 5003 PA_CR1 Port A control register 1 0x00 0x00 5004 PA_CR2 Port A control register 2 0x00 0x00 5005 PB_ODR Port B data output latch register 0x00 0x00 5006 PB_IDR Port B input pin value register 0xxx PB_DDR Port B data direction register 0x00 0x00 5008 PB_CR1 Port B control register 1 0x00 0x00 5009 PB_CR2 Port B control register 2 0x00 0x00 500A PC_ODR Port C data output latch register 0x00 0x00 500B PC_IDR Port C input pin value register 0xxx PC_DDR Port C data direction register 0x00 0x00 500D PC_CR1 Port C control register 1 0x00 0x00 500E PC_CR2 Port C control register 2 0x00 0x00 500F PD_ODR Port D data output latch register 0x00 0x00 5010 PD_IDR Port D input pin value register 0xxx PD_DDR Port D data direction register 0x00 0x00 5012 PD_CR1 Port D control register 1 0x00 0x00 5013 PD_CR2 Port D control register 2 0x00 Address 0x00 5002 0x00 5007 0x00 500C 0x00 5011 24/88 Block Port A Port B Port C Port D DocID15275 Rev 16 STM8L101x1 STM8L101x2 STM8L101x3 Memory and register map Table 7. General hardware register map Register label Register name Reset status 0x00 5050 FLASH_CR1 Flash control register 1 0x00 0x00 5051 FLASH_CR2 Flash control register 2 0x00 FLASH _PUKR Flash Program memory unprotection register 0x00 0x00 5053 FLASH _DUKR Data EEPROM unprotection register 0x00 0x00 5054 FLASH _IAPSR Flash in-application programming status register 0xX0 Address 0x00 5052 Block Flash 0x00 5055 to 0x00 509F Reserved area (75 bytes) 0x00 50A0 EXTI_CR1 External interrupt control register 1 0x00 0x00 50A1 EXTI_CR2 External interrupt control register 2 0x00 EXTI_CR3 External interrupt control register 3 0x00 EXTI_SR1 External interrupt status register 1 0x00 0x00 50A4 EXTI_SR2 External interrupt status register 2 0x00 0x00 50A5 EXTI_CONF External interrupt port select register 0x00 WFE_CR1 WFE control register 1 0x00 WFE_CR2 WFE control register 2 0x00 0x00 50A2 0x00 50A3 0x00 50A6 0x00 50A7 ITC-EXTI WFE 0x00 50A8 to 0x00 50AF 0x00 50B0 0x00 50B1 Reserved area (8 bytes) RST RST_CR Reset control register 0x00 RST_SR Reset status register 0x01 0x00 50B2 to 0x00 50BF Reserved area (14 bytes) 0x00 50C0 0x00 50C1 to 0x00 50C2 0x00 50C3 CLK_CKDIVR Clock divider register Reserved area (2 bytes) CLK CLK_PCKENR Peripheral clock gating register 0x00 50C4 0x00 50C5 0x00 50C6 to 0x00 50DF 0x03 0x00 Reserved (1 byte) CLK_CCOR Configurable clock control register 0x00 Reserved area (25 bytes) DocID15275 Rev 16 25/88 33 Memory and register map STM8L101x1 STM8L101x2 STM8L101x3 Table 7. General hardware register map (continued) Address Block 0x00 50E0 0x00 50E1 IWDG 0x00 50E2 Register label Register name Reset status IWDG_KR IWDG key register 0xXX IWDG_PR IWDG prescaler register 0x00 IWDG_RLR IWDG reload register 0xFF 0x00 50E3 to 0x00 50EF Reserved area (13 bytes) 0x00 50F0 0x00 50F1 AWU 0x00 50F2 0x00 50F3 BEEP AWU_CSR AWU control/status register 0x00 AWU_APR AWU asynchronous prescaler buffer register 0x3F AWU_TBR AWU timebase selection register 0x00 BEEP_CSR BEEP control/status register 0x1F 0x00 50F4 to 0x00 51FF Reserved area (268 bytes) 0x00 5200 SPI_CR1 SPI control register 1 0x00 0x00 5201 SPI_CR2 SPI control register 2 0x00 SPI_ICR SPI interrupt control register 0x00 0x00 5203 SPI_SR SPI status register 0x02 0x00 5204 SPI_DR SPI data register 0x00 0x00 5202 SPI 0x00 5205 to 0x00 520F Reserved area (11 bytes) 0x00 5210 I2C_CR1 I2C control register 1 0x00 0x00 5211 I2C_CR2 I2C control register 2 0x00 0x00 5212 I2C_FREQR I2C frequency register 0x00 0x00 5213 I2C_OARL I2C own address register low 0x00 0x00 5214 I2C_OARH I2C own address register high 0x00 0x00 5215 0x00 5216 I2C_DR I2C data register 0x00 I2C_SR1 I2C status register 1 0x00 0x00 5218 I2C_SR2 I2C status register 2 0x00 0x00 5219 I2C_SR3 I2C status register 3 0x00 0x00 521A I2C_ITR I2C interrupt control register 0x00 0x00 521B I2C_CCRL I2C Clock control register low 0x00 0x00 521C I2C_CCRH I2C Clock control register high 0x00 0x00 521D I2C_TRISER I2C TRISE register 0x02 0x00 5217 26/88 Reserved area (1 byte) I2C DocID15275 Rev 16 STM8L101x1 STM8L101x2 STM8L101x3 Memory and register map Table 7. General hardware register map (continued) Address Block Register label 0x00 521E to 0x00 522F Register name Reset status Reserved area (18 bytes) 0x00 5230 USART_SR USART status register 0xC0 0x00 5231 USART_DR USART data register 0xXX 0x00 5232 USART_BRR1 USART baud rate register 1 0x00 USART_BRR2 USART baud rate register 2 0x00 USART_CR1 USART control register 1 0x00 0x00 5235 USART_CR2 USART control register 2 0x00 0x00 5236 USART_CR3 USART control register 3 0x00 0x00 5237 USART_CR4 USART control register 4 0x00 0x00 5233 0x00 5234 0x00 5238 to 0x00 524F USART Reserved area (18 bytes) DocID15275 Rev 16 27/88 33 Memory and register map STM8L101x1 STM8L101x2 STM8L101x3 Table 7. General hardware register map (continued) Register label Register name Reset status 0x00 5250 TIM2_CR1 TIM2 control register 1 0x00 0x00 5251 TIM2_CR2 TIM2 control register 2 0x00 0x00 5252 TIM2_SMCR TIM2 slave mode control register 0x00 0x00 5253 TIM2_ETR TIM2 external trigger register 0x00 0x00 5254 TIM2_IER TIM2 interrupt enable register 0x00 0x00 5255 TIM2_SR1 TIM2 status register 1 0x00 0x00 5256 TIM2_SR2 TIM2 status register 2 0x00 0x00 5257 TIM2_EGR TIM2 event generation register 0x00 0x00 5258 TIM2_CCMR1 TIM2 capture/compare mode register 1 0x00 0x00 5259 TIM2_CCMR2 TIM2 capture/compare mode register 2 0x00 TIM2_CCER1 TIM2 capture/compare enable register 1 0x00 TIM2_CNTRH TIM2 counter high 0x00 0x00 525C TIM2_CNTRL TIM2 counter low 0x00 0x00 525D TIM2_PSCR TIM2 prescaler register 0x00 0x00 525E TIM2_ARRH TIM2 auto-reload register high 0xFF 0x00 525F TIM2_ARRL TIM2 auto-reload register low 0xFF 0x00 5260 TIM2_CCR1H TIM2 capture/compare register 1 high 0x00 0x00 5261 TIM2_CCR1L TIM2 capture/compare register 1 low 0x00 0x00 5262 TIM2_CCR2H TIM2 capture/compare register 2 high 0x00 0x00 5263 TIM2_CCR2L TIM2 capture/compare register 2 low 0x00 0x00 5264 TIM2_BKR TIM2 break register 0x00 0x00 5265 TIM2_OISR TIM2 output idle state register 0x00 Address 0x00 525A 0x00 525B 0x00 5266 to 0x00 527F 28/88 Block TIM2 Reserved area (26 bytes) DocID15275 Rev 16 STM8L101x1 STM8L101x2 STM8L101x3 Memory and register map Table 7. General hardware register map (continued) Register label Register name Reset status 0x00 5280 TIM3_CR1 TIM3 control register 1 0x00 0x00 5281 TIM3_CR2 TIM3 control register 2 0x00 0x00 5282 TIM3_SMCR TIM3 slave mode control register 0x00 0x00 5283 TIM3_ETR TIM3 external trigger register 0x00 0x00 5284 TIM3_IER TIM3 interrupt enable register 0x00 0x00 5285 TIM3_SR1 TIM3 status register 1 0x00 0x00 5286 TIM3_SR2 TIM3 status register 2 0x00 0x00 5287 TIM3_EGR TIM3 event generation register 0x00 0x00 5288 TIM3_CCMR1 TIM3 capture/compare mode register 1 0x00 0x00 5289 TIM3_CCMR2 TIM3 capture/compare mode register 2 0x00 TIM3_CCER1 TIM3 capture/compare enable register 1 0x00 TIM3_CNTRH TIM3 counter high 0x00 0x00 528C TIM3_CNTRL TIM3 counter low 0x00 0x00 528D TIM3_PSCR TIM3 prescaler register 0x00 0x00 528E TIM3_ARRH TIM3 auto-reload register high 0xFF 0x00 528F TIM3_ARRL TIM3 auto-reload register low 0xFF 0x00 5290 TIM3_CCR1H TIM3 capture/compare register 1 high 0x00 0x00 5291 TIM3_CCR1L TIM3 capture/compare register 1 low 0x00 0x00 5292 TIM3_CCR2H TIM3 capture/compare register 2 high 0x00 0x00 5293 TIM3_CCR2L TIM3 capture/compare register 2 low 0x00 0x00 5294 TIM3_BKR TIM3 break register 0x00 0x00 5295 TIM3_OISR TIM3 output idle state register 0x00 Address 0x00 528A 0x00 528B Block TIM3 0x00 5296 to 0x00 52DF Reserved area (74 bytes) 0x00 52E0 TIM4_CR1 TIM4 control register 1 0x00 0x00 52E1 TIM4_CR2 TIM4 control register 2 0x00 0x00 52E2 TIM4_SMCR TIM4 Slave mode control register 0x00 0x00 52E3 TIM4_IER TIM4 interrupt enable register 0x00 TIM4_SR1 TIM4 Status register 1 0x00 0x00 52E5 TIM4_EGR TIM4 event generation register 0x00 0x00 52E6 TIM4_CNTR TIM4 counter 0x00 0x00 52E7 TIM4_PSCR TIM4 prescaler register 0x00 0x00 52E8 TIM4_ARR TIM4 auto-reload register low 0xFF 0x00 52E4 TIM4 DocID15275 Rev 16 29/88 33 Memory and register map STM8L101x1 STM8L101x2 STM8L101x3 Table 7. General hardware register map (continued) Address Block Register label 0x00 52E9 to 0x00 52FE Register name Reset status Reserved area (23 bytes) 0x00 52FF IRTIM 0x00 5300 0x00 5301 COMP 0x00 5302 IR_CR Infra-red control register 0x00 COMP_CR Comparator control register 0x00 COMP_CSR Comparator status register 0x00 COMP_CCS Comparator channel selection register 0x00 Table 8. CPU/SWIM/debug module/interrupt controller registers Register label Register name Reset status 0x00 7F00 A Accumulator 0x00 0x00 7F01 PCE Program counter extended 0x00 0x00 7F02 PCH Program counter high 0x80 0x00 7F03 PCL Program counter low 0x00 0x00 7F04 XH X index register high 0x00 XL X index register low 0x00 0x00 7F06 YH Y index register high 0x00 0x00 7F07 YL Y index register low 0x00 0x00 7F08 SPH Stack pointer high 0x05 0x00 7F09 SPL Stack pointer low 0xFF 0x00 7F0A CC Condition code register 0x28 Address 0x00 7F05 Block CPU 0x00 7F0B to 0x00 7F5F 0x00 7F60 Reserved area (85 bytes) CFG CFG_GCR 0x00 7F61 0x00 7F6F 0x00 Reserved area (15 bytes) 0x00 7F70 ITC_SPR1 Interrupt Software priority register 1 0xFF 0x00 7F71 ITC_SPR2 Interrupt Software priority register 2 0xFF 0x00 7F72 ITC_SPR3 Interrupt Software priority register 3 0xFF ITC_SPR4 Interrupt Software priority register 4 0xFF ITC_SPR5 Interrupt Software priority register 5 0xFF 0x00 7F75 ITC_SPR6 Interrupt Software priority register 6 0xFF 0x00 7F76 ITC_SPR7 Interrupt Software priority register 7 0xFF 0x00 7F77 ITC_SPR8 Interrupt Software priority register 8 0xFF 0x00 7F73 0x00 7F74 30/88 Global configuration register ITC-SPR (1) DocID15275 Rev 16 STM8L101x1 STM8L101x2 STM8L101x3 Memory and register map Table 8. CPU/SWIM/debug module/interrupt controller registers (continued) Address Block Register label 0x00 7F78 to 0x00 7F79 0x00 7F80 Register name Reset status Reserved area (2 bytes) SWIM SWIM_CSR 0x00 7F81 to 0x00 7F8F SWIM control status register 0x00 Reserved area (15 bytes) 0x00 7F90 DM_BK1RE Breakpoint 1 register extended byte 0xFF 0x00 7F91 DM_BK1RH Breakpoint 1 register high byte 0xFF 0x00 7F92 DM_BK1RL Breakpoint 1 register low byte 0xFF 0x00 7F93 DM_BK2RE Breakpoint 2 register extended byte 0xFF 0x00 7F94 DM_BK2RH Breakpoint 2 register high byte 0xFF DM_BK2RL Breakpoint 2 register low byte 0xFF 0x00 7F96 DM_CR1 Debug module control register 1 0x00 0x00 7F97 DM_CR2 Debug module control register 2 0x00 0x00 7F98 DM_CSR1 Debug module control/status register 1 0x10 0x00 7F99 DM_CSR2 Debug module control/status register 2 0x00 0x00 7F9A DM_ENFCTR Enable function register 0xFF 0x00 7F95 DM 1. Refer to Table 7: General hardware register map on page 25 (addresses 0x00 50A0 to 0x00 50A5) for a list of external interrupt registers. DocID15275 Rev 16 31/88 33 Interrupt vector mapping 6 STM8L101x1 STM8L101x2 STM8L101x3 Interrupt vector mapping Table 9. Interrupt mapping IRQ No. Source block - RESET - TRAP 0 - 1 FLASH 2-3 - 4 AWU 5 - 6 EXTIB 7 Wakeup from Halt mode Wakeup from Active-halt mode Wakeup from Wait (WFI mode) Wakeup from Wait (WFE mode) Yes Yes Yes Yes 0x00 8000 Software interrupt - - - - 0x00 8004 Reserved - - - - Description Reset address 0x00 8008 (1) 0x00 800C EOP/WR_PG_DIS - - Yes Reserved - - - - 0x00 8010 -0x00 8017 Auto wakeup from Halt - Yes Yes Yes(1) 0x00 8018 Reserved - - - - 0x00 801C External interrupt port B Yes Yes Yes Yes 0x00 8020 EXTID External interrupt port D Yes Yes Yes Yes 0x00 8024 8 EXTI0 External interrupt 0 Yes Yes Yes Yes 0x00 8028 9 EXTI1 External interrupt 1 Yes Yes Yes Yes 0x00 802C 10 EXTI2 External interrupt 2 Yes Yes Yes Yes 0x00 8030 11 EXTI3 External interrupt 3 Yes Yes Yes Yes 0x00 8034 12 EXTI4 External interrupt 4 Yes Yes Yes Yes 0x00 8038 13 EXTI5 External interrupt 5 Yes Yes Yes Yes 0x00 803C 14 EXTI6 External interrupt 6 Yes Yes Yes Yes 0x00 8040 15 EXTI7 External interrupt 7 Yes Yes Yes Yes 0x00 8044 16 - Reserved - - - - 0x00 8048 17 - Reserved - - - - 0x00 804C -0x00 804F 18 COMP Comparators - - Yes Yes(1) 0x00 8050 19 TIM2 Update /Overflow/Trigger/Break - - Yes Yes 0x00 8054 20 TIM2 Capture/Compare - - Yes Yes 0x00 8058 Yes Yes(1) 0x00 805C (1) 0x00 8060 21 TIM3 22 TIM3 2324 - 25 TIM4 26 32/88 SPI Update /Overflow/Break - - Yes Vector Capture/Compare - - Yes Reserved - - - - 0x00 80640x00 806B Update /Trigger - - Yes Yes(1) 0x00 806C Yes Yes(1) 0x00 8070 End of Transfer Yes Yes DocID15275 Rev 16 Yes STM8L101x1 STM8L101x2 STM8L101x3 Interrupt vector mapping Table 9. Interrupt mapping (continued) IRQ No. Source block 27 USART 28 USART 29 I2C Wakeup from Halt mode Wakeup from Active-halt mode Wakeup from Wait (WFI mode) Wakeup from Wait (WFE mode) Transmission complete/transmit data register empty - - Yes Yes(1) 0x00 8074 Receive Register DATA FULL/overrun/idle line detected/parity error - - Yes Yes(1) 0x00 8078 Yes Yes Yes Yes(1) 0x00 807C Description I2C interrupt(2) Vector address 1. In WFE mode, this interrupt is served if it has been previously enabled. After processing the interrupt, the processor goes back to WFE mode. Refer to Section Wait for event (WFE) mode in the RM0013 reference manual. 2. The device is woken up from Halt or Active-halt mode only when the address received matches the interface address. DocID15275 Rev 16 33/88 33 Option bytes 7 STM8L101x1 STM8L101x2 STM8L101x3 Option bytes Option bytes contain configurations for device hardware features as well as the memory protection of the device. They are stored in a dedicated row of the memory. All option bytes can be modified only in ICP mode (with SWIM) by accessing the EEPROM address. See Table 10 for details on option byte addresses. Refer to the STM8L Flash programming manual (PM0054) and STM8 SWIM and Debug Manual (UM0470) for information on SWIM programming procedures. Table 10. Option bytes Addr. Option name Option byte No. Option bits 7 6 5 4 3 2 1 0 Factory default setting 0x4800 Read-out protection (ROP) OPT1 ROP[7:0] 0x00 0x4807 - - Must be programmed to 0x00 0x00 0x4802 UBC (User Boot code size) OPT2 UBC[7:0] 0x00 0x4803 DATASIZE OPT3 DATASIZE[7:0] 0x00 0x4808 Independent watchdog option OPT4 [1:0] Reserved IWDG _HALT IWDG _HW 0x00 Table 11. Option byte description 34/88 OPT1 ROP[7:0] Memory readout protection (ROP) 0xAA: Enable readout protection (write access via SWIM protocol) Refer to Read-out protection section in the STM8L reference manual (RM0013) for details. OPT2 UBC[7:0] Size of the user boot code area 0x00: no UBC 0x01-0x02: UBC contains only the interrupt vectors. 0x03: Page 0 and 1 reserved for the interrupt vectors. Page 2 is available to store user boot code. Memory is write protected ... 0x7F - Page 0 to 126 reserved for UBC, memory is write protected Refer to User boot area (UBC) section in the STM8L reference manual (RM0013) for more details. UBC[7] is forced to 0 internally by HW. DocID15275 Rev 16 STM8L101x1 STM8L101x2 STM8L101x3 Option bytes Table 11. Option byte description (continued) OPT3 OPT4 DATASIZE[7:0] Size of the data EEPROM area 0x00: no data EEPROM area (1) 0x01: 1 page reserved for data storage from 0x9FC0 to 0x9FFF(1) 0x02: 2 pages reserved for data storage from 0x9F80 to 0x9FFF(1) ... (1) 0x20: 32 pages reserved for data storage from 0x9800 to 0x9FFF(1) Refer to Data EEPROM (DATA) section in the STM8L reference manual (RM0013) for more details. DATASIZE[7:6] are forced to 0 internal by HW. IWDG_HW: Independent watchdog 0: Independent watchdog activated by software 1: Independent watchdog activated by hardware IWDG_HALT: Independent window watchdog reset on Halt/Active-halt 0: Independent watchdog continues running in Halt/Active-halt mode 1: Independent watchdog stopped in Halt/Active-halt mode 1. 0x00 is the only allowed value for 4 Kbyte STM8L101xx devices. Caution: After a device reset, read access to the program memory is not guaranteed if address 0x4807 is not programmed to 0x00. DocID15275 Rev 16 35/88 35 Unique ID 8 STM8L101x1 STM8L101x2 STM8L101x3 Unique ID STM8L101xx devices feature a 96-bit unique device identifier which provides a reference number that is unique for any device and in any context. The 96 bits of the identifier can never be altered by the user. The unique device identifier can be read in single bytes and may then be concatenated using a custom algorithm. The unique device identifier is ideally suited: • For use as serial numbers • For use as security keys to increase the code security in the program memory while using and combining this unique ID with software cryptographic primitives and protocols before programming the internal memory • To activate secure boot processes. Table 12. Unique ID registers (96 bits) Address 0x4925 0x4926 0x4927 Unique ID bits 7 6 5 4 3 U_ID[7:0] X co-ordinate on the wafer U_ID[15:8] U_ID[23:16] 0x4928 Y co-ordinate on the wafer 0x4929 Wafer number U_ID[39:32] U_ID[31:24] 0x492A U_ID[47:40] 0x492B U_ID[55:48] 0x492C U_ID[63:56] 0x492D 36/88 Content description Lot number U_ID[71:64] 0x492E U_ID[79:72] 0x492F U_ID[87:80] 0x4930 U_ID[95:88] DocID15275 Rev 16 2 1 0 STM8L101x1 STM8L101x2 STM8L101x3 Electrical parameters 9 Electrical parameters 9.1 Parameter conditions Unless otherwise specified, all voltages are referred to VSS. 9.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA= 25 °C and TA = TA max (given by the selected temperature range). Note: The values given at 85 °C