STM8L101F2T6

STM8L101xx 8-bit ultralow power microcontroller with up to 8 Kbytes Flash, multifunction timers, comparators, USART, SPI, I2C Preliminary data Features ■ Main microcontroller features – Supply voltage range 1.65 V to 3.6 V – Low power consumption (Halt: 0.3 µA, Active-halt: 0.8 µA, Dynamic Run: 150 µA/MHz) – STM8 Core with up to 16 CISC MIPS throughput – Temp. range: -40 to 85 °C and 125 °C Memories – Up to 8 Kbytes of Flash program including up to 2 Kbytes of data EEPROM – Error correction code (ECC) – Flexible write and read protection modes – In-application and in-circuit programming – Data EEPROM capability – 1.5 Kbytes of static RAM Clock management – Internal 16 MHz RC with fast wakeup time (typ. 4 µs) – Internal low consumption 38 kHz RC driving both the IWDG and the AWU Reset and supply management – Ultralow power, ultrasafe power-on-reset /power down reset – Three low power modes: Wait, Active-halt, Halt Interrupt management – Nested interrupt controller with software priority control – Up to 29 external interrupt sources I/Os – Up to 30 I/Os, all mappable on external interrupt vectors – I/Os with prog. input pull-ups, high sink/source capability and one LED driver infrared output ■ ■ WFQFPN32 LQFP32 WFQFPN28 UFQFPN20 TSSOP20 ■ ■ Peripherals – Two 16-bit general purpose timers (TIM2 and TIM3) with up and down counter and 2 channels (used as IC, OC, PWM) – One 8-bit timer (TIM4) with 7-bit prescaler – Infrared remote control (IR) – Independent watchdog – Auto-wakeup unit – Beeper timer with 1, 2 or 4 kHz frequencies – SPI synchronous serial interface – Fast I2C Multimaster/slave 400 kHz – USART with fractional baud rate generator – 2 comparators with 4 inputs each Development support – Hardware single wire interface module (SWIM) for fast on-chip programming and non intrusive debugging – In-circuit emulation (ICE) 96-bit unique ID Device summary Part number STM8L101F2, STM8L101F3, STM8L101G2, STM8L101G3 STM8L101K3 ■ ■ ■ Table 1. Reference STM8L101xx ■ September 2009 Doc ID 15275 Rev 7 1/77 www.st.com 1 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. Contents STM8L101xx Contents 1 2 3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 Central processing unit STM8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Single wire data interface (SWIM) and debug module . . . . . . . . . . . . . . . 10 Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Voltage regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Clock control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Auto-wakeup counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 General purpose and basic timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Infrared (IR) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 I²C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4 5 6 7 8 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Interrupt vector mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Unique ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2/77 Doc ID 15275 Rev 7 STM8L101xx Contents 9 Electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.1.1 9.1.2 9.1.3 9.1.4 9.1.5 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.2 9.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 9.3.1 9.3.2 9.3.3 9.3.4 9.3.5 9.3.6 9.3.7 9.3.8 9.3.9 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Power-up / power-down operating conditions . . . . . . . . . . . . . . . . . . . . 41 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 9.4 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 10 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 10.1 10.2 ECOPACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 11 12 Device ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 STM8 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 12.1 12.2 Emulation and in-circuit debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . 72 Software tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 12.2.1 12.2.2 STM8 toolset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 C and assembly toolchains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 12.3 Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Doc ID 15275 Rev 7 3/77 List of tables STM8L101xx List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Device features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Legend/abbreviation for table 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 STM8L101xx pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Flash and RAM boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 I/O Port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 General hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 CPU/SWIM/debug module/interrupt controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Unique ID registers (96 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Total current consumption in Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Total current consumption in Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Total current consumption and timing in Halt and Active-halt mode at VDD = 1.65 V to 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Flash program memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Output driving current (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Output driving current (true open drain ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Output driving current (PA0 with high sink LED driver capability). . . . . . . . . . . . . . . . . . . . 52 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 I2C characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 EMS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 EMI data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 WFQFPN32 - 32-lead very very thin fine pitch quad flat no-lead package (5 x 5), package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 LQFP32- 32-pin low profile quad flat package (7x7), package mechanical data . . . . . . . . 67 WFQFPN28 - 28-lead very very thin fine pitch quad flat no-lead package (4 x 4), package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 UFQFPN20 3 x 3 mm 0.6 mm mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 20-lead thin shrink small package, mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 4/77 Doc ID 15275 Rev 7 STM8L101xx List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. STM8L101 device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Standard 20-pin UFQFPN package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 20-pin UFQFPN package pinout for STM8L101F3U6ATR and STM8L101F2U6ATR part numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 20-pin TSSOP package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Standard 28-pin WFQFPN package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 28-pin WFQFPN package pinout for STM8L101G3U6ATR and STM8L101G2U6ATR part numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 32-pin package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 IDD(RUN) vs. VDD@ fCPU = 2 MHz @4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 IDD(RUN) vs. VDD@ fCPU = 16 MHz @4 temperatures. . . . . . . . . . . . . . . . . . . . . . . . . . 41 IDD(WAIT) vs. VDD@ fCPU = 2 MHz @4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 IDD(WAIT) vs. VDD@ fCPU = 16 MHz @4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . 42 Typ. IDD(Halt) vs. VDD @ fCPU = 2 MHz and 16 MHz @4 temperatures. . . . . . . . . . . . . 43 Typical HSI frequency vs VDD @ 4 temperatures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Typical HSI accuracy at VDD = 3 V vs temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Typical HSI accuracy at VDD = 1.65 V to 3.6 V vs temperature. . . . . . . . . . . . . . . . . . . . . 46 Typical LSI RC frequency vs. VDD @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Typical VIL and VIH vs VDD (standard I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Typical VIL and VIH vs VDD (true open drain I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Typical pull-up resistance RPU vs VDD @ 4 temperatures with VIN=VSS . . . . . . . . . . . . . 50 Typical pull-up current Ipu vs VDD @ 4 temperatures with VIN=VSS . . . . . . . . . . . . . . . . . 51 Typ. VOL @ VDD = 3.0 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Typ. VOL @ VDD = 1.8 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Typ. VOL @ VDD = 3.0 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Typ. VOL @ VDD = 1.8 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Typ. VDD - VOH @ VDD = 3.0 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Typ. VDD - VOH @ VDD = 1.8 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Typical NRST pull-up resistance RPU vs VDD @ 4 temperatures . . . . . . . . . . . . . . . . . . . . 54 Typical NRST pull-up current Ipu vs VDD @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . 55 Recommended NRST pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Typical application with I2C bus and timing diagram 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 WFQFPN32 - 32-lead very very thin fine pitch quad flat no-lead package outline (5 x 5) . 65 WFQFPN32 recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 LQFP32 - 32-pin low profile quad flat package outline (7 x 7) . . . . . . . . . . . . . . . . . . . . . . 67 LQFP32 recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 WFQFPN28 - 28-lead very very thin fine pitch quad flat no-lead package outline (4 x 4) . 68 WFQFPN28 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 UFQFPN20 3 x 3 mm 0.6 mm package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 UFQFPN20 recommended footprint (1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Doc ID 15275 Rev 7 5/77 List of figures Figure 45. Figure 46. Figure 47. STM8L101xx TSSOP20 - 20-lead thin shrink small package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 TSSOP20 recommended footprint (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 STM8L101xx ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 6/77 Doc ID 15275 Rev 7 STM8L101xx Introduction 1 Introduction This datasheet provides the STM8L101xx pinout, ordering information, mechanical and electrical device characteristics. For complete information on the STM8L101xx microcontroller memory, registers and peripherals, please refer to the STM8L reference manual. 2 Description The STM8L101xx devices are members of the STM8L low power 8-bit family. All devices of the SM8L product line provide the following benefits: ● Reduced system cost – – – Up to 8 Kbytes of embedded Flash program memory including up to 2 Kbytes of data EEPROM High system integration level with internal clock oscillators and watchdogs. Smaller battery and cheaper power supplies. Up to 16 MIPS at 16 MHz CPU clock frequency less than 150 µA/MH, 0.8 µA in Active-halt mode, and 0.3 µA in Halt mode Clock gated system and optimized power management Application scalability across a common family product architecture with compatible pinout, memory map and modular peripherals. Full documentation and a wide choice of development tools Advanced core and peripherals made in a state-of-the art technology Product family operating from 1.65 V to 3.6 V supply ● Low power consumption and advanced features – – – ● Short development cycles – – ● Product longevity – – The STM8L101xx low power family features the enhanced STM8 CPU core providing increased processing power (up to 16 MIPS at 16 MHz) while maintaining the advantages of a CISC architecture with improved code density, a 24-bit linear addressing space and an optimized architecture for low power operations. The family includes an integrated debug module with a hardware interface (SWIM) which allows non-intrusive In-Application debugging and ultrafast Flash programming. All STM8L101xx microcontrollers feature low power low-voltage single-supply program Flash memory. The 8-Kbyte devices embed data EEPROM. The STM8L101xx low power family is based on a generic set of state-of-the-art peripherals. The modular design of the peripheral set allows the same peripherals to be found in different ST microcontroller families including 32-bit families. This makes any transition to a different family very easy, and simplified even more by the use of a common set of development tools. Doc ID 15275 Rev 7 7/77 Description STM8L101xx All STM8L low power products are based on the same architecture with the same memory mapping and a coherent pinout. Table 2. Device features Features Flash RAM STM8L101xx 4 Kbytes of Flash program memory 8 Kbytes of Flash program memory including up to 2 Kbytes of Data EEPROM 1.5 Kbytes Independent watchdog (IWDG), Auto-wakeup unit (AWU), Beep, Serial peripheral interface (SPI), Inter-integrated circuit (I²C), Universal synchronous / asynchronous receiver / transmitter (USART), 2 comparators, Infrared (IR) interface Two 16-bit timers, one 8-bit timer 1.65 to 3.6 V -40 to +85 °C WFQFPN28 4x 4 UFQFPN20 3x3 TSSOP20 4.4 x 6.4 -40 to +85 °C or -40 to +125 °C WFQFPN28 4x4 UFQFPN20 3x3 WFQFPN32 LQFP32 Peripheral functions Timers Operating voltage Operating temperature Packages 8/77 Doc ID 15275 Rev 7 STM8L101xx Product overview 3 Product overview Figure 1. STM8L101 device block diagram @VDD VDD18 Power Volt. reg. 16 MHz int RC 38 kHz int RC Clock controller Clocks to core and peripherals VDD =1.65 V to 3.6 V VSS Reset POR/PDR NRST STM8 Core up to 16 MHz Nested interrupt controller up to 29 external interrupts Debug module (SWIM) Address and data bus Up to 8 Kbytes Flash memory (including up to 2 Kbytes data EEPROM) 1.5 Kbytes SRAM SWIM USART I²C1 multimaster SPI 16-bit Timer 2 16-bit Timer 3 8-bit Timer 4 IWDG AWU RX, TX, CK SDA, SCL IR_TIM Infrared interface MOSI, MISO, SCK, NSS TIM2_CH[2:1] TIM2_TRIG TIM3_CH[2:1] TIM3_TRIG PA[6:0] PB[7:0] PC[6:0] PD[7:0] Port A Port B Port C Port D COMP1_CH[4:1] COMP1 COMP_REF COMP2_CH[4:1] COMP2 Beeper BEEP Legend: AWU: Auto-wakeup unit Int. RC: internal RC oscillator I²C: Inter-integrated circuit multimaster interface POR/PDR: Power on reset / power down reset SPI: Serial peripheral interface SWIM: Single wire interface module USART: Universal synchronous / asynchronous receiver / transmitter IWDG: Independent watchdog Doc ID 15275 Rev 7 9/77 Product overview STM8L101xx 3.1 Central processing unit STM8 The 8-bit STM8 core is designed for code efficiency and performance. It features 21 internal registers, 20 addressing modes including indexed, indirect and relative addressing, and 80 instructions. 3.2 Development tools Development tools for the STM8 microcontrollers include: ● ● ● The STice emulation system offering tracing and code profiling The STVD high-level language debugger including C compiler, assembler and integrated development environment The STVP Flash programming software The STM8 also comes with starter kits, evaluation boards and low-cost in-circuit debugging/programming tools. 3.3 Single wire data interface (SWIM) and debug module The debug module with its single wire data interface (SWIM) permits non-intrusive real-time in-circuit debugging and fast memory programming. The Single wire interface is used for direct access to the debugging module and memory programming. The interface can be activated in all device operation modes. The non-intrusive debugging module features a performance close to a full-featured emulator. Beside memory and peripherals, also CPU operation can be monitored in realtime by means of shadow registers. 3.4 Interrupt controller The STM8L101xx features a nested vectored interrupt controller: ● ● ● ● Nested interrupts with 3 software priority levels 26 interrupt vectors with hardware priority Up to 29 external interrupt sources on 10 vectors Trap and reset interrupts 10/77 Doc ID 15275 Rev 7 STM8L101xx Product overview 3.5 Memory The STM8L101xx devices have the following main features: ● ● 1.5 Kbytes of RAM The EEPROM is divided into two memory arrays (see the STM8L reference manual for details on the memory mapping): – Up to 8 Kbytes of embedded Flash program including up to 2 Kbytes of data EEPROM. Data EEPROM and Flash program areas can be write protected independently by using the memory access security mechanism (MASS). 64 option bytes (one block) of which 5 bytes are already used for the device. – Error correction code is implemented on the EEPROM. 3.6 Low power modes To minimize power consumption, the product features three low power modes: ● ● ● Wait mode: CPU clock stopped, selected peripherals at full clock speed. Active-halt mode: CPU and peripheral clocks are stopped. The programmable wakeup time is controlled by the AWU unit. Halt mode: CPU and peripheral clocks are stopped, the device remains powered on. Wakeup is triggered by an external interrupt. 3.7 Voltage regulators The STM8L101xx embeds an internal voltage regulator for generating the 1.8 V power supply for the core and peripherals. This regulator has two different modes: main voltage regulator mode (MVR) and low power voltage regulator mode (LPVR). When entering Halt or Active-halt modes, the system automatically switches from the MVR to the LPVR in order to reduce current consumption. 3.8 Clock control The STM8L101xx embeds a robust clock controller. It is used to distribute the system clock to the core and the peripherals and to manage clock gating for low power modes. This system clock is a 16-MHz High Speed Internal RC oscillator (HSI RC), followed by a programmable prescaler. In addition, a 38 kHz low speed internal RC oscillator is used by the independent watchdog (IWDG) and Auto-wakeup unit (AWU). 3.9 Independent watchdog The independent watchdog (IWDG) peripheral can be used to resolve processor malfunctions due to hardware or software failures. It is clocked by the 38 kHZ LSI internal RC clock source, and thus stays active even in case of a CPU clock failure. Doc ID 15275 Rev 7 11/77 Product overview STM8L101xx 3.10 Auto-wakeup counter The auto-wakeup (AWU) counter is used to wakeup the device from Active-halt mode. 3.11 General purpose and basic timers STM8L101xx devices contain two 16-bit general purpose timers (TIM2 and TIM3) and one 8-bit basic timer (TIM4). 16-bit general purpose timers The 16-bit timers consist of 16-bit up/down auto-reload counters driven by a programmable prescaler. They perform a wide range of functions, including: ● ● ● ● ● Time base generation Measuring the pulse lengths of input signals (input capture) Generating output waveforms (output compare, PWM and one pulse Mode) Interrupt capability on various events (capture, compare, overflow, break, trigger) Synchronization with other timers or external signals (external clock, reset, trigger and enable) 8-bit basic timer The 8-bit timer consists of an 8-bit up auto-reload counter driven by a programmable prescaler. It can be used for timebase generation with interrupt generation on timer overflow. 3.12 Beeper The STM8L101xx devices include a beeper function used to generate a beep signal in the range of 1, 2 or 4 kHz when the LSI clock is operating at a frequency of 38 kHz. 3.13 Infrared (IR) interface The STM8L101xx devices contain an infrared interface which can be used with an IR LED for remote control functions. Two timer output compare channels are used to generate the infrared remote control signals. 3.14 Comparators The STM8L101xx features two zero-crossing comparators (COMP1 and COMP2) sharing the same current bias and voltage reference. The voltage reference can be internal (comparison with ground) or external (comparison to a reference pin voltage). Each comparator is connected to 4 channels, which can be used to generate interrupt, timer input capture or timer break. Their polarity can be inverted. 12/77 Doc ID 15275 Rev 7 STM8L101xx Product overview 3.15 USART The USART interface (USART) allows full duplex, asynchronous communications with external devices requiring an industry standard NRZ asynchronous serial data format. It offers a very wide range of baud rates. 3.16 SPI The serial peripheral interface (SPI) provides half/ full duplex synchronous serial communication with external devices. It can be configured as the master and in this case it provides the communication clock (SCK) to the external slave device. The interface can also operate in multi-master configuration. 3.17 I²C The inter-integrated circuit (I2C) Bus Interface is designed to serve as an interface between the microcontroller and the serial I2C bus. It provides multi-master capability, and controls all I²C bus-specific sequencing, protocol, arbitration and timing. It manages standard and fast speed modes. Doc ID 15275 Rev 7 13/77 Pin description STM8L101xx 4 Pin description Figure 2. Standard 20-pin UFQFPN package pinout PA0 (HS) / SWIM / BEEP / IR_TIM PC4 (HS) / USART_CK / CCO PC2 (HS) / USART_RX PC3 (HS) / USART_TX 20 19 18 17 16 15 14 13 12 11 NRST / PA1 (HS) PA2 (HS) PA3 (HS) VSS VDD 1 2 3 4 5 6 7 8 9 10 PC1 / I²C_SCL PC0 / I²C_SDA PB7 (HS) / SPI_MISO PB6 (HS) / SPI_MOSI PB5 (HS) / SPI_SCK PB4 (HS) / SPI_NSS 1. HS corresponds to 20 mA high sink/source capability. 2. High sink LED driver capability available on PA0. Refer to the description of the IR_CR register in the STM8L reference manual (RM0013). Note: The COMP_REF pin is not available in this standard 20-pin UFQFPN package. It is available on Port A6 in the 20-pin UFQFPN package pinout for STM8L101F3U6ATR and STM8L101F2U6ATR part numbers (Figure 3 on page 15). 14/77 Doc ID 15275 Rev 7 PB3 (HS) / TIM2_TRIG / COMP2_CH2 PB0 (HS) / TIM2_CH1 / COMP1_CH1 PB1 (HS) / TIM3_CH1 /COMP1_CH2 PD0 (HS) / TIM3_CH2 / COMP1_CH3 PB2 (HS) / TIM2_CH2 / COMP2_CH1 STM8L101xx Figure 3. Pin description 20-pin UFQFPN package pinout for STM8L101F3U6ATR and STM8L101F2U6ATR part numbers PA0 (HS) / SWIM / BEEP / IR_TIM PC4 (HS) / USART_CK / CCO PC2 (HS) / USART_RX PC3 (HS) / USART_TX 20 19 18 17 16 15 14 13 12 11 NRST / PA1 (HS) PA2 (HS) PA6 (HS) / COMP_REF VSS VDD 1 2 3 4 5 6 7 8 9 10 PC1 / I²C_SCL PC0 / I²C_SDA PB7 (HS) / SPI_MISO PB6 (HS) / SPI_MOSI PB5 (HS) / SPI_SCK PB4 (HS) / SPI_NSS 1. Please refer to the warning below. 2. HS corresponds to 20 mA high sink/source capability. 3. High sink LED driver capability available on PA0. Refer to the description of the IR_CR register in the STM8L reference manual (RM0013). Warning: For the STM8L101F3U6ATR and STM8L101F2U6ATR part numbers (devices with COMP_REF pin), all ports available on 32-pin packages must be considered as active ports. To avoid spurious effects, you have to configure them as input pull-up. A small increase in consumption (typ. < 300 µA) may occur during the power up and reset phase until these ports are properly configured . Doc ID 15275 Rev 7 PB3 (HS) / TIM2_TRIG / COMP2_CH2 PD0 (HS) / TIM3_CH2 / COMP1_CH3 PB0 (HS) / TIM2_CH1 / COMP1_CH1 PB2 (HS) / TIM2_CH2 / COMP2_CH1 PB1 (HS) / TIM3_CH1 /COMP1_CH2 15/77 Pin description Figure 4. 20-pin TSSOP package pinout STM8L101xx PC3 (HS) / USART_TX PC4 (HS) / USART_CK/ CCO PA0 (HS) / SWIM / BEEP / IR_TIM NRST / PA1 (HS) PA2 (HS) PA3 (HS) VSS VDD PD0 (HS) / TIM3_CH2 / COMP1_CH3 PB0 (HS) / TIM2_CH1 / COMP1_CH1 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 PC2 (HS) / USART_RX PC1 / I²C_SCL PC0 / I²C_SDA PB7 (HS) / SPI_MISO PB6 (HS) / SPI_MOSI PB5 (HS) / SPI_SCK PB4 (HS) / SPI_NSS PB3 (HS) /TIM2_TRIG /COMP2_CH2 PB2 (HS) / TIM2_CH2 / COMP2_CH1 PB1 (HS) / TIM3_CH1 / COMP1_CH2 1. HS corresponds to 20 mA high sink/source capability. 2. High sink LED driver capability available on PA0. Refer to the description of the IR_CR register in the STM8L reference manual (RM0013). 16/77 Doc ID 15275 Rev 7 STM8L101xx Figure 5. Standard 28-pin WFQFPN package pinout PA0 (HS) / SWIM / BEEP / IR_TIM PC4 (HS) / USART_CK / CCO Pin description PC2 (HS) / USART_RX 23 PC3 (HS) / USART_TX 28 27 26 25 24 PC1 / I²C_SCL 22 21 20 19 18 17 16 15 PC6 (HS) PC5 (HS) NRST / PA1 (HS) PA2 (HS) PA3 (HS) PA4 (HS) / TIM2_BKIN PA5 (HS) / TIM3_BKIN VSS VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PC0 / I²C_SDA PD4 (HS) PB7 (HS) / SPI_MISO PB6 (HS) / SPI_MOSI PB5 (HS) / SPI_SCK PB4 (HS) / SPI_NSS PB3 (HS) / TIM2_TRIG / COMP2_CH2 PD1 (HS) / TIM3_TRIG / COMP1_CH4 PD2(HS) / COMP2_CH3 PD0 (HS) / TIM3_CH2 / COMP1_CH3 / COMP2_CH4 PB0 (HS) / TIM2_CH1 / COMP1_CH1 PB1 (HS) / TIM3_CH1 / COMP1_CH2 1. HS corresponds to 20 mA high sink/source capability. 2. High sink LED driver capability available on PA0. Refer to the description of the IR_CR register in the STM8L reference manual (RM0013). Note: The COMP_REF pin is not available in this standard 28-pin WFQFPN package. It is available on Port A6 in the 28-pin WFQFPN package pinout for STM8L101G3U6ATR and STM8L101G2U6ATR part numbers (Figure 6 on page 18). Doc ID 15275 Rev 7 PB2 (HS) / TIM2_CH2 / COMP2_CH1 PD3(HS) 17/77 Pin description Figure 6. 28-pin WFQFPN package pinout for STM8L101G3U6ATR and STM8L101G2U6ATR part numbers PA0 (HS) / SWIM / BEEP / IR_TIM PC4 (HS) / USART_CK / CCO STM8L101xx PC2 (HS) / USART_RX 23 PC3 (HS) / USART_TX 28 27 26 25 24 PC1 / I²C_SCL 22 21 20 19 18 17 16 15 PC6 (HS) PC5 (HS) NRST / PA1 (HS) PA2 (HS) PA3 (HS) PA4 (HS) / TIM2_BKIN PA6 (HS) / COMP_REF VSS VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PC0 / I²C_SDA PD4 (HS) PB7 (HS) / SPI_MISO PB6 (HS) / SPI_MOSI PB5 (HS) / SPI_SCK PB4 (HS) / SPI_NSS PB3 (HS) / TIM2_TRIG / COMP2_CH2 PD1 (HS) / TIM3_TRIG / COMP1_CH4 PD2(HS) / COMP2_CH3 PD0 (HS) / TIM3_CH2 / COMP1_CH3 PD3(HS) / COMP2_CH4 PB0 (HS) / TIM2_CH1 / COMP1_CH1 PB1 (HS) / TIM3_CH1 / COMP1_CH2 1. HS corresponds to 20 mA high sink/source capability. 2. High sink LED driver capability available on PA0. Refer to the description of the IR_CR register in the STM8L reference manual (RM0013). Warning: For the STM8L101G3U6ATR and STM8L101G2U6ATR part numbers (devices with COMP_REF pin), all ports available on 32-pin packages must be considered as active ports. To avoid spurious effects, you have to configure them as input pull-up. A small increase in consumption (typ. < 300 µA) may occur during the power up and reset phase until these ports are properly configured . 18/77 Doc ID 15275 Rev 7 PB2 (HS) / TIM2_CH2 / COMP2_CH1 STM8L101xx Figure 7. 32-pin package pinout PA0 (HS) / SWIM / BEEP / IR_TIM Pin description PC4 (HS) / USART_CK / CCO PC2 (HS) / USART_RX PC3 (HS) / USART_TX 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 PC0 / I²C_SDA PC1 / I²C_SCL PC6 (HS) PC5 (HS) NRST / PA1 (HS) PA2 (HS) PA3 (HS) PA4 (HS) / TIM2_BKIN PA5 (HS) / TIM3_BKIN PA6 (HS) / COMP_REF VSS VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PD7 (HS) PD6 (HS) PD5 (HS) PD4 (HS) PB7 (HS) / SPI_MISO PB6 (HS) / SPI_MOSI PB5 (HS) / SPI_SCK PB4 (HS) / SPI_NSS PD1 (HS) / TIM3_TRIG / COMP1_CH4 1. Example given for the WFQFPN32 package. The pinout is the same for the LQFP32 package. 2. HS corresponds to 20 mA high sink/source capability. 3. High sink LED driver capability available on PA0. Refer to the description of the IR_CR register in the STM8L reference manual (RM0013). Doc ID 15275 Rev 7 PB3 (HS) / TIM2_TRIG / COMP2_CH2 PB0 (HS) / TIM2_CH1 / COMP1_CH1 PB1 (HS) / TIM3_CH1 / COMP1_CH2 PD0 (HS) / TIM3_CH2 / COMP1_CH3 PB2 (HS) / TIM2_CH2 / COMP2_CH1 PD2 (HS) / / COMP2_CH3 PD3 (HS) / COMP2_CH4 19/77 Pin description Table 3. Type Level Output Port and control Input configuration Output HS = high sink/source (20 mA) float = floating, wpu = weak pull-up T = true open drain, OD = open drain, PP = push pull STM8L101xx Legend/abbreviation for table 4 I= input, O = output, S = power supply Input CM = CMOS Reset state is shown in bold. Table 4. STM8L101xx pin description Input Output Pin number WFQFPN28 with COMP_REF(1) UFQFPN20 with COMP_REF(1) WFQFPN32 or LQFP32 standard WFQFPN28 standard UFQFPN20 wpu OD Pin name High sink/source Ext. interrupt TSSOP20 Main function (after reset) Reset Port A2 Port A3 Port A4 Port A5 Port A6 Ground Port D0 Port D1 Port D2 Port D3 Port B0 Type floating Alternate function 1 2 3 4 5 6 1 2 3 4 5 6 4 5 6 7 8 9 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 NRST/PA1(2) PA2 PA3 PA4/TIM2_BKIN PA5/TIM3_BKIN PA6/COMP_REF VSS VDD PD0/TIM3_CH2/ COMP1_CH3 PD1/TIM3_TRIG/ COMP1_CH4 PD2/ COMP2_CH3 PD3/ COMP2_CH4 PB0/TIM2_CH1/ COMP1_CH1 I/O I/O X I/O X I/O X I/O X I/O X S S I/O X X X X X X X X X X X X X HS X HS X HS X HS X HS X HS X X X X X X X PP PA1 Timer 2 - break input Timer 3 - break input Comparator external reference Power supply HS X X Timer 3 - channel 2 / Comparator 1 channel 3 Timer 3 - trigger / Comparator 1 channel 4 Comparator 2 channel 3 Comparator 2 channel 4 Timer 2 - channel 1 / Comparator 1 channel 1 - - - 9 9 10 I/O X X X HS X X - - - 10 10 11 11 11 12 I/O X I/O X X X X X HS X HS X X X 7 7 10 12 12 13 I/O X X X HS X X 20/77 Doc ID 15275 Rev 7 STM8L101xx Table 4. STM8L101xx pin description (continued) Input Output Pin description Pin number WFQFPN28 with COMP_REF(1) UFQFPN20 with COMP_REF(1) WFQFPN32 or LQFP32 standard WFQFPN28 standard UFQFPN20 High sink/source Ext. interrupt TSSOP20 Main function (after reset) Port B1 Port B2 Port B3 Port B4 Port B5 Port B6 Port B7 Port D4 Port D5 Port D6 Port D7 Port C0 Port C1 Port C2 Port C3 Port C4 Port C5 Type floating wpu OD Pin name Alternate function PP 8 8 11 13 13 14 PB1/TIM3_CH1/ COMP1_CH2 PB2/ TIM2_CH2/ COMP2_CH1/ PB3/TIM2_TRIG/ COMP2_CH2 PB4/SPI_NSS PB5/SPI_SCK PB6/SPI_MOSI PB7/SPI_MISO PD4 PD5 PD6 PD7 PC0/I2C_SDA PC1/I2C_SCL PC2/USART_RX PC3/USART_TX I/O X X X HS X X Timer 3 - channel 1 / Comparator 1 channel 2 Timer 2 - channel 2 / Comparator 2 channel 1 Timer 2 - trigger / Comparator 2 channel 2 SPI master/slave select SPI clock SPI master out/ slave in SPI master in/ slave out 9 9 12 14 14 15 I/O X X X HS X X 10 10 13 15 15 16 I/O X X X HS X X 11 12 13 14 15 16 17 18 19 - 11 12 13 14 15 16 17 18 19 - 14 16 16 17 15 17 17 18 16 18 18 19 17 19 19 20 20 20 21 22 23 24 I/O X I/O X I/O X I/O X I/O X I/O X I/O X I/O X I/O X I/O X I/O X I/O X X X X X X X X X X X X X X X X X X X X X X X X X X X X X HS X HS X HS X HS X HS X HS X HS X HS X T T (3) (3) X X X X X X X X 18 21 21 25 19 22 22 26 20 23 23 27 1 2 24 24 28 25 25 29 26 26 30 I2C data I2C clock USART receive USART transmit USART synchronous clock / Configurable clock output HS X HS X HS X HS X X X X X PC4/USART_CK/ I/O X CCO PC5 I/O X Doc ID 15275 Rev 7 21/77 Pin description Table 4. STM8L101xx pin description (continued) Input Output STM8L101xx Pin number WFQFPN28 with COMP_REF(1) UFQFPN20 with COMP_REF(1) WFQFPN32 or LQFP32 standard WFQFPN28 standard UFQFPN20 High sink/source Ext. interrupt TSSOP20 Main function (after reset) Port C6 Port A0 Type floating wpu OD Pin name Alternate function - - - 27 27 31 PC6 I/O X X X HS X HS( 4) X PP 20 20 3 28 28 32 PA0/SWIM/BEEP/ I/O X IR_TIM (4) X X X X SWIM input and output /Beep output/Timer Infrared output 1. Please refer to the warning below. 2. When the PA1/NRST pin is used as general purpose (PA1), it can be configured only as output open-drain or push-pull, not as a general purpose input. Refer to Section 7.1.2: Configuring NRST/PA1 pin as general purpose output. 3. In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer and protection diode to VDD are not implemented). 4. High sink LED driver capability available on PA0. Warning: For the STM8L101F2U6ATR, STM8L101F3U6ATR, STM8L101G2U6ATR and STM8L101G3U6ATR part numbers (devices with COMP_REF pin), all ports available on 32-pin packages must be considered as active ports. To avoid spurious effects, you have to configure them as input pull-up. A small increase in consumption (typ. < 300 µA) may occur during the power up and reset phase until these ports are properly configured . 22/77 Doc ID 15275 Rev 7 STM8L101xx Memory and register map 5 Memory and register map Figure 8. Memory map 0x00 0000 RAM (1.5 Kbytes) (1) including Stack (up to 513 bytes) (1) Reserved 0x00 47FF 0x00 4800 Option bytes 0x00 48FF 0x 004900 Reserved 0x00 49FF 0x00 5000 GPIO and peripheral registers(2) 0x00 57FF 0x00 5800 Reserved 0x00 7EFF 0x00 7F00 0x00 7FFF 0x00 8000 0x00 807F 0x00 8080 CPU/SWIM/Debug/ITC Registers Interrupt vectors 0x00 05FF 0x00 0600 Flash program memory (up to 8 Kbytes) (1) including Data EEPROM (up to 2 Kbytes) 0x00 9FFF 1. Table 5 lists the boundary addresses for each memory size. The top of the stack is at the RAM end address. 2. Refer to Table 7 for an overview of hardware register mapping, to Table 6 for details on I/O port hardware registers, and to Table 8 for information on CPU/SWIM/debug module controller registers. Doc ID 15275 Rev 7 23/77 Memory and register map Table 5. Flash and RAM boundary addresses Size 1.5 Kbytes 4 Kbytes Flash program memory 8 Kbytes 0x00 8000 Start Address 0x00 0000 0x00 8000 STM8L101xx Memory area RAM End address 0x00 05FF 0x00 8FFF 0x00 9FFF Table 6. Address 0x00 5000 0x00 5001 0x00 5002 0x00 5003 0x00 5004 0x00 5005 0x00 5006 0x00 5007 0x00 5008 0x00 5009 0x00 500A 0x00 500B 0x00 500C 0x00 500D 0x00 500E 0x00 500F 0x00 5010 0x00 5011 0x00 5012 0x00 5013 I/O Port hardware register map Block Register label PA_ODR PA_IDR Port A PA_DDR PA_CR1 PA_CR2 PB_ODR PB_IDR Port B PB_DDR PB_CR1 PB_CR2 PC_ODR PC_IDR Port C PC_DDR PC_CR1 PC_CR2 PD_ODR PD_IDR Port D PD_DDR PD_CR1 PD_CR2 Register name Port A data output latch register Port A input pin value register Port A data direction register Port A control register 1 Port A control register 2 Port B data output latch register Port B input pin value register Port B data direction register Port B control register 1 Port B control register 2 Port C data output latch register Port C input pin value register Port C data direction register Port C control register 1 Port C control register 2 Port D data output latch register Port D input pin value register Port D data direction register Port D control register 1 Port D control register 2 Reset status 0x00 0xxx 0x00 0x00 0x00 0x00 0xxx 0x00 0x00 0x00 0x00 0xxx 0x00 0x00 0x00 0x00 0xxx 0x00 0x00 0x00 24/77 Doc ID 15275 Rev 7 STM8L101xx Table 7. Address 0x00 5050 0x00 5051 0x00 5052 0x00 5053 0x00 5054 0x00 5065 to 0x00 509F 0x00 50A0 0x00 50A1 0x00 50A2 ITC-EXTI 0x00 50A3 0x00 50A4 0x00 50A5 0x00 50A6 WFE 0x00 50A7 0x00 50A8 to 0x00 50AF 0x00 50B0 RST 0x00 50B1 0x00 50B4 to 0x00 50BF 0x00 50C0 0x00 50C1 to 0x00 50C2 0x00 50C3 0x00 50C4 0x00 50C5 0x00 50C7 to 0x00 50DF CLK_CCOR CLK_CKDIVR RST_SR RST_CR WFE_CR2 EXTI_SR1 EXTI_SR2 EXTI_CONF WFE_CR1 EXTI_CR1 EXTI_CR2 EXTI_CR3 Flash Memory and register map General hardware register map Block Register label FLASH_CR1 FLASH_CR2 FLASH _PUKR FLASH _DUKR FLASH _IAPSR Register name Flash control register 1 Flash control register 2 Flash Program memory unprotection register Data EEPROM unprotection register Flash in-application programming status register Reserved area (59 bytes) External interrupt control register 1 External interrupt control register 2 External interrupt control register 3 External interrupt status register 1 External interrupt status register 2 External interrupt port select register WFE control register 1 WFE control register 2 Reserved area (8 bytes) Reset control register Reset status register Reserved area (12 bytes) Clock divider register Reserved area (2 bytes) CLK CLK_PCKENR Peripheral clock gating register Reserved (1 byte) Configurable clock control register Reserved area (18 bytes) 0x00 0x00 0x03 0x00 0x01 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 Reset status 0x00 0x00 0x00 0x00 0xX0 Doc ID 15275 Rev 7 25/77 Memory and register map Table 7. Address 0x00 50E0 0x00 50E1 0x00 50E2 0x00 50E3 to 0x00 50EF 0x00 50F0 0x00 50F1 0x00 50F2 0x00 50F3 0x00 50F4 to 0x00 50FF 0x00 5200 0x00 5201 0x00 5202 0x00 5203 0x00 5204 0x00 5205 to 0x00 520F 0x00 5210 0x00 5211 0x00 5212 0x00 5213 0x00 5214 0x00 5215 0x00 5216 I2C 0x00 5217 0x00 5218 0x00 5219 0x00 521A 0x00 521B 0x00 521C 0x00 521D I2C_SR1 I2C_SR2 I2C_SR3 I2C_ITR I2C_CCRL I2C_CCRH I2C_TRISER I2C status register 1 I2C status register 2 I2C status register 3 I2C interrupt control register I2C Clock control register low I2C Clock control register high I2C TRISE register I2C_DR I2C_CR1 I2C_CR2 I2C_FREQR I2C_OARL I2C_OARH SPI SPI_CR1 SPI_CR2 SPI_ICR SPI_SR SPI_DR BEEP AWU AWU_CSR AWU_APR AWU_TBR BEEP_CSR IWDG STM8L101xx General hardware register map (continued) Block Register label IWDG_KR IWDG_PR IWDG_RLR Register name IWDG Key register IWDG Prescaler register IWDG Reload register Reserved area (13 bytes) AWU control/status register AWU asynchronous prescaler buffer register AWU timebase selection register BEEP control/status register Reserved area (12 bytes) SPI control register 1 SPI control register 2 SPI interrupt control register SPI status register SPI data register Reserved area (11 bytes) I2C control register 1 I2C control register 2 I2C frequency register I2C Own address register low I2C Own address register high Reserved area (1 byte) I2C data register 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x02 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x02 0x00 0x00 0x3F 0x00 0x1F Reset status 0xXX 0x00 0xFF 26/77 Doc ID 15275 Rev 7 STM8L101xx Table 7. Address 0x00 521E to 0x00 522F 0x00 5230 0x00 5231 0x00 5232 0x00 5233 USART 0x00 5234 0x00 5235 0x00 5236 0x00 5237 0x00 523B to 0x00 524F USART_CR1 USART_CR2 USART_CR3 USART_CR4 USART_SR USART_DR USART_BRR1 USART_BRR2 Memory and register map General hardware register map (continued) Block Register label Register name Reset status Reserved area (18 bytes) USART Status Register USART Data Register USART Baud Rate Register 1 USART Baud Rate Register 2 USART Control Register 1 USART Control Register 2 USART Control Register 3 USART Control Register 4 Reserved area (21 bytes) 0xC0 0xXX 0x00 0x00 0x00 0x00 0x00 0x00 Doc ID 15275 Rev 7 27/77 Memory and register map Table 7. Address 0x00 5250 0x00 5251 0x00 5252 0x00 5253 0x00 5254 0x00 5255 0x00 5256 0x00 5257 0x00 5258 0x00 5259 0x00 525A TIM2 0x00 525B 0x00 525C 0x00 525D 0x00 525E 0x00 525F 0x00 5260 0x00 5261 0x00 5262 0x00 5263 0x00 5264 0x00 5265 0x00 5256 to 0x00 527F TIM2_CNTRH TIM2_CNTRL TIM2_PSCR TIM2_ARRH TIM2_ARRL TIM2_CCR1H TIM2_CCR1L TIM2_CCR2H TIM2_CCR2L TIM2_BKR TIM2_OISR TIM2 Counter high TIM2 Counter low TIM2 Prescaler register TIM2 Auto-reload register high TIM2 Auto-reload register low STM8L101xx General hardware register map (continued) Block Register label TIM2_CR1 TIM2_CR2 TIM2_SMCR TIM2_ETR TIM2_IER TIM2_SR1 TIM2_SR2 TIM2_EGR TIM2_CCMR1 TIM2_CCMR2 TIM2_CCER1 Register name TIM2 Control register 1 TIM2 Control register 2 TIM2 Slave Mode Control register TIM2 external trigger register TIM2 Interrupt enable register TIM2 Status register 1 TIM2 Status register 2 TIM2 Event Generation register TIM2 Capture/Compare mode register 1 TIM2 Capture/Compare mode register 2 TIM2 Capture/Compare enable register 1 Reset status 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xFF 0xFF 0x00 0x00 0x00 0x00 0x00 0x00 TIM2 Capture/Compare register 1 high TIM2 Capture/Compare register 1 low TIM2 Capture/Compare register 2 high TIM2 Capture/Compare register 2 low TIM2 Break register TIM2 Output idle state register Reserved area (42 bytes) 28/77 Doc ID 15275 Rev 7 STM8L101xx Table 7. Address 0x00 5280 0x00 5281 0x00 5282 0x00 5283 0x00 5284 0x00 5285 0x00 5286 0x00 5287 0x00 5288 0x00 5289 0x00 528A TIM3 0x00 528B 0x00 528C 0x00 528D 0x00 528E 0x00 528F 0x00 5290 0x00 5291 0x00 5292 0x00 5293 0x00 5294 0x00 5295 0x00 5296 to 0x00 52DF 0x00 52E0 0x00 52E1 0x00 52E2 0x00 52E3 0x00 52E4 0x00 52E5 0x00 52E6 0x00 52E7 0x00 52E8 TIM4 TIM4_CR1 TIM4_CR2 TIM4_SMCR TIM4_IER TIM4_SR1 TIM4_EGR TIM4_CNTR TIM4_PSCR TIM4_ARR TIM3_CNTRH TIM3_CNTRL TIM3_PSCR TIM3_ARRH TIM3_ARRL TIM3_CCR1H TIM3_CCR1L TIM3_CCR2H TIM3_CCR2L TIM3_BKR TIM3_OISR Memory and register map General hardware register map (continued) Block Register label TIM3_CR1 TIM3_CR2 TIM3_SMCR TIM3_ETR TIM3_IER TIM3_SR1 TIM3_SR2 TIM3_EGR TIM3_CCMR1 TIM3_CCMR2 TIM3_CCER1 Register name TIM3 Control register 1 TIM3 Control register 2 TIM3 Slave Mode Control register TIM3 external trigger register TIM3 Interrupt enable register TIM3 Status register 1 TIM3 Status register 2 TIM3 Event Generation register TIM3 Capture/Compare mode register 1 TIM3 Capture/Compare mode register 2 TIM3 Capture/Compare enable register 1 TIM3 Counter high TIM3 Counter low TIM3 Prescaler register TIM3 Auto-reload register high TIM3 Auto-reload register low TIM3 Capture/Compare register 1 high TIM3 Capture/Compare register 1 low TIM3 Capture/Compare register 2 high TIM3 Capture/Compare register 2 low TIM3 Break register TIM3 Output idle state register Reserved area (74 bytes) TIM4 Control register 1 TIM4 Control register 2 TIM4 Slave Mode Control Register TIM4 Interrupt enable register TIM4 Status register 1 TIM4 Event Generation register TIM4 Counter TIM4 Prescaler register TIM4 Auto-reload register low 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xFF Reset status 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xFF 0xFF 0x00 0x00 0x00 0x00 0x00 0x00 Doc ID 15275 Rev 7 29/77 Memory and register map Table 7. Address 0x00 52E9 to 0x00 52FE 0x00 52FF 0x00 5300 0x00 5301 0x00 5302 COMP IR IR_CR COMP_CR COMP_CSR COMP_CCS STM8L101xx General hardware register map (continued) Block Register label Register name Reset status Reserved area (23 bytes) Infra-red control register Comparator control register Comparator status register Comparator channel selection register 0x00 0x00 0x00 0x00 Table 8. Address 0x00 7F00 0x00 7F01 0x00 7F02 0x00 7F03 0x00 7F04 0x00 7F05 0x00 7F06 0x00 7F07 0x00 7F08 0x00 7F09 0x00 7F0A 0x00 7F0B to 0x00 7F5F 0x00 7F60 0x00 7F61 0x00 7F6F 0x00 7F70 0x00 7F71 0x00 7F72 0x00 7F73 0x00 7F74 0x00 7F75 0x00 7F76 0x00 7F77 CPU/SWIM/debug module/interrupt controller registers Block Register label A PCE PCH PCL XH CPU XL YH YL SPH SPL CC Register name Accumulator Program counter extended Program counter high Program counter low X index register high X index register low Y index register high Y index register low Stack pointer high Stack pointer low Condition code register Reserved area (85 bytes) CFG CFG_GCR Global configuration register Reserved area (15 bytes) ITC_SPR1 ITC_SPR2 ITC_SPR3 ITC-SPR (1) Reset status 0x00 0x00 0x80 0x00 0x00 0x00 0x00 0x00 0x05 0xFF 0x28 0x00 Interrupt Software priority register 1 Interrupt Software priority register 2 Interrupt Software priority register 3 Interrupt Software priority register 4 Interrupt Software priority register 5 Interrupt Software priority register 6 Interrupt Software priority register 7 Interrupt Software priority register 8 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF ITC_SPR4 ITC_SPR5 ITC_SPR6 ITC_SPR7 ITC_SPR8 30/77 Doc ID 15275 Rev 7 STM8L101xx Table 8. Address 0x00 7F78 to 0x00 7F79 0x00 7F80 0x00 7F81 to 0x00 7F8F 0x00 7F90 0x00 7F91 0x00 7F92 0x00 7F93 0x00 7F94 0x00 7F95 0x00 7F96 0x00 7F97 0x00 7F98 0x00 7F99 0x00 7F9A DM DM_BK1RE DM_BK1RH DM_BK1RL DM_BK2RE DM_BK2RH DM_BK2RL DM_CR1 DM_CR2 DM_CSR1 DM_CSR2 DM_ENFCTR SWIM SWIM_CSR Memory and register map CPU/SWIM/debug module/interrupt controller registers (continued) Block Register label Register name Reset status Reserved area (2 bytes) SWIM control status register Reserved area (15 bytes) Breakpoint 1 register extended byte Breakpoint 1 register high byte Breakpoint 1 register low byte Breakpoint 2 register extended byte Breakpoint 2 register high byte Breakpoint 2 register low byte Debug module control register 1 Debug module control register 2 Debug module control/status register 1 Debug module control/status register 2 Enable function register 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0x00 0x00 0x10 0x00 0xFF 0x00 1. Refer to Table 7: General hardware register map on page 25 (addresses 0x00 50A0 to 0x00 50A5) for a list of external interrupt registers. Doc ID 15275 Rev 7 31/77 Interrupt vector mapping STM8L101xx 6 Table 9. IRQ No. Interrupt vector mapping Interrupt mapping Wakeup from Halt mode Yes Wakeup from Active-halt mode Yes Wakeup from Wait (WFI mode) Yes Wakeup from Wait (WFE mode) Yes Vector address 0x00 8000 0x00 8004 0x00 8008 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes(1) Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes (1) Source block RESET TRAP Reset Description Software interrupt Reserved 0 1 2-3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 2324 25 26 TIM4 SPI COMP TIM2 TIM2 TIM3 TIM3 EXTIB EXTID EXTI0 EXTI1 EXTI2 EXTI3 EXTI4 EXTI5 EXTI6 EXTI7 AWU FLASH EOP/WR_PG_DIS Reserved Auto wakeup from Halt Reserved External interrupt port B External interrupt port D External interrupt 0 External interrupt 1 External interrupt 2 External interrupt 3 External interrupt 4 External interrupt 5 External interrupt 6 External interrupt 7 Reserved Reserved Comparators Update /Overflow/Trigger/Break Capture/Compare Update /Overflow/Break Capture/Compare Reserved Update /Trigger End of Transfer 0x00 800C 0x00 8010 -0x00 8017 0x00 8018 0x00 801C 0x00 8020 0x00 8024 0x00 8028 0x00 802C 0x00 8030 0x00 8034 0x00 8038 0x00 803C 0x00 8040 0x00 8044 0x00 8048 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes(1) Yes Yes Yes(1) Yes Yes(1) Yes(1) (1) 0x00 804C -0x00 804F 0x00 8050 0x00 8054 0x00 8058 0x00 805C 0x00 8060 0x00 80640x00 806B 0x00 806C 0x00 8070 32/77 Doc ID 15275 Rev 7 STM8L101xx Table 9. IRQ No. Interrupt vector mapping Interrupt mapping (continued) Wakeup from Halt mode Wakeup from Active-halt mode Wakeup from Wait (WFI mode) Yes Wakeup from Wait (WFE mode) Yes(1) Vector address Source block Description 27 USART Transmission complete/transmit data register empty Receive Register DATA FULL/overrun/idle line detected/parity error I2C interrupt(2) - 0x00 8074 28 29 USART I2C Yes Yes Yes Yes Yes(1) Yes(1) 0x00 8078 0x00 807C 1. In WFE mode, this interrupt is served if it has been previously enabled. After processing the interrupt, the processor goes back to WFE mode. Section : Wait for event (WFE) mode on page 70. 2. The device is woken up from Halt or Active-halt mode only when the address received matches the interface address. Doc ID 15275 Rev 7 33/77 Option bytes STM8L101xx 7 Option bytes Option Bytes contain configurations for device hardware features as well as the memory protection of the device. They are stored in a dedicated row of the memory. All option bytes can be modified only in ICP mode (with SWIM) by accessing the EEPROM address. See Table 10 for details on option byte addresses. Refer to the STM8L Flash programming manual (PM0054) and STM8 SWIM and Debug Manual (UM0320) for information on SWIM programming procedures. Table 10. Addr. Option bytes Option name Read-out protection (ROP) Option byte No. OPT1 OPT2 OPT3 OPT4 [1:0] Option bits 7 6 5 4 3 ROP[7:0] Must be programmed to 0x00 UBC[7:0] DATASIZE[7:0] Reserved IWDG _HALT IWDG _HW 2 1 0 Factory default setting 0x00 0x00 0x00 0x00 0x00 0x4800 0x4807 0x4802 0x4803 0x4808 UBC(User Boot code size) DATASIZE Independent watchdog option Table 11. OPT1 Option byte description ROP[7:0] Memory readout protection (ROP) 0xAA: Enable Readout protection (write access via SWIM protocol) Refer to Read-out protection section in the STM8L reference manual (RM0013) for details. UBC[7:0] Size of the user boot code area 0x00: no UBC 0x01-0x02: UBC contains only the interrupt vectors. 0x03: Page 0 and 1 reserved for the interrupt vectors. Page 2 is available to store user boot code. Memory is write protected ... 0x7F - Page 0 to 126 reserved for UBC, memory is write protected Refer to User boot area (UBC) section in the STM8L reference manual (RM0013) for more details. DATASIZE[7:0] Size of the data EEPROM area 0x00: no data EEPROM area (1) 0x01 - 1 page reserved for data storage.(1) ... (1) 0x20 - 32 pages reserved for data storage.(1) Refer to Data EEPROM (DATA) section in the STM8L reference manual (RM0013) for more details. OPT2 OPT3 34/77 Doc ID 15275 Rev 7 STM8L101xx Table 11. Option byte description (continued) IWDG_HW: Independent watchdog 0: Independent watchdog activated by software 1: Independent watchdog activated by hardware OPT4 Option bytes IWDG_HALT: Independent window watchdog reset on Halt/Active-halt 0: Independent watchdog continues running in Halt/Active-halt mode 1: Independent watchdog stopped in Halt/Active-halt mode 1. 0x00 is the only allowed value for 4 Kbyte STM8L101xx devices. Caution: After a device reset, read access to the program memory is not guaranteed if address 0x4807 is not programmed to 0x00. Doc ID 15275 Rev 7 35/77 Unique ID STM8L101xx 8 Unique ID devices feature a 96-bit unique device identifier which provides a reference number that is unique for any device and in any context. The 96 bits of the identifier can never be altered by the user. The unique device identifier can be read in single bytes and may then be concatenated using a custom algorithm. The unique device identifier is ideally suited: ● ● For use as serial numbers For use as security keys to increase the code security in the program memory while using and combining this unique ID with software crytograhic primitives and protocols before programming the internal memory. To activate secure boot processes Unique ID registers (96 bits) Content description X co-ordinate on the wafer Y co-ordinate on the wafer Wafer number Unique ID bits 7 6 5 4 3 U_ID[7:0] U_ID[15:8] U_ID[23:16] U_ID[31:24] U_ID[39:32] U_ID[47:40] U_ID[55:48] U_ID[63:56] Lot number U_ID[71:64] U_ID[79:72] U_ID[87:80] U_ID[95:88] 2 1 0 ● Table 12. Address 0x4925 0x4926 0x4927 0x4928 0x4929 0x492A 0x492B 0x492C 0x492D 0x492E 0x492F 0x4930 36/77 Doc ID 15275 Rev 7 STM8L101xx Electrical parameters 9 9.1 Electrical parameters Parameter conditions Unless otherwise specified, all voltages are referred to VSS. 9.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA= 25 °C and TA = TA max (given by the selected temperature range). Note: The values given at 85 °C VDD while a negative injection is induced by VINVDD while a negative injection is induced by VIN