STM8S208S6T6C

STM8S207xx STM8S208xx Performance line, 24 MHz STM8S 8-bit MCU, up to 128 Kbytes Flash, integrated EEPROM,10-bit ADC, timers, 2 UARTs, SPI, I²C, CAN Features ■ Core – Max fCPU: up to 24 MHz, 0 wait states @ fCPU ≤ 16 MHz – Advanced STM8 core with Harvard architecture and 3-stage pipeline – Extended instruction set – Max 20 MIPS @ 24 MHz Memories – Program: up to 128 Kbytes Flash; data retention 20 years at 55 °C after 10 kcycles – Data: up to 2 Kbytes true data EEPROM; endurance 300 kcycles – RAM: up to 6 Kbytes Clock, reset and supply management – 2.95 to 5.5 V operating voltage – Flexible clock control: – Low power crystal resonator oscillator – External clock input – Internal, user-trimmable 16 MHz RC – Internal low power 128 kHz RC – Clock security system with clock monitor – Power management: – Wait, active-halt, & halt low power modes – Peripheral clocks switched off individually – Permanently active, low consumption power-on and power-down reset Interrupt management – Nested interrupt controller with 32 interrupts – Up to 37 external interrupts on 6 vectors Timers – 2x 16-bit general purpose timers, with 2+3 CAPCOM channels (IC, OC or PWM) – Advanced control timer: 16-bit, 4 CAPCOM channels, 3 complementary outputs, deadtime insertion and flexible synchronization – 8-bit basic timer with 8-bit prescaler – Auto wakeup timer – Window watchdog, independent watchdog ■ LQFP80 14x14 LQFP64 14x14 LQFP64 10x10 LQFP48 7x7 LQFP44 10x10 LQFP32 7x7 ■ ■ Communications interfaces – High speed 1 Mbit/s active beCAN 2.0B – UART with clock output for synchronous operation - LIN master mode – UART with LIN 2.1 compliant, master/slave modes and automatic resynchronization – SPI interface up to 10 Mbit/s – I2C interface up to 400 Kbit/s 10-bit ADC with up to 16 channels I/Os – Up to 68 I/Os on an 80-pin package including 18 high sink outputs – Highly robust I/O design, immune against current injection – Development support – Single wire interface module (SWIM) and debug module (DM) Unique ID – 96-bit unique key for each device Device summary ■ ■ ■ ■ Table 1. Part numbers: STM8S207xx STM8S207MB, STM8S207M8, STM8S207RB, STM8S207R8, STM8S207R6, STM8S207CB, STM8S207C8, STM8S207C6, STM8S207SB, STM8S207S8, STM8S207S6, STM8S207K6 Part numbers: STM8S208xx STM8S208MB, STM8S208RB, STM8S208R8, STM8S208R6, STM8S208CB, STM8S208C8, STM8S208C6, STM8S208SB, STM8S208S8, STM8S208S6 ■ April 2010 Doc ID 14733 Rev 9 www.st.com 1/103 1 Contents STM8S207xx, STM8S208xx Contents 1 2 3 4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.12 4.13 4.14 Central processing unit STM8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Single wire interface module (SWIM) and debug module (DM) . . . . . . . . 14 Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Flash program and data EEPROM memory . . . . . . . . . . . . . . . . . . . . . . . 15 Clock controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Watchdog timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Auto wakeup counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 TIM1 - 16-bit advanced control timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 TIM2, TIM3 - 16-bit general purpose timers . . . . . . . . . . . . . . . . . . . . . . . 18 TIM4 - 8-bit basic timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Analog-to-digital converter (ADC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.14.1 4.14.2 4.14.3 4.14.4 4.14.5 UART1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 UART3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 beCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1 5.2 Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6 Memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.1 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2/103 Doc ID 14733 Rev 9 STM8S207xx, STM8S208xx Contents 6.2 Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7 8 9 10 Interrupt vector mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Unique ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 10.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 10.1.1 10.1.2 10.1.3 10.1.4 10.1.5 10.1.6 10.1.7 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Typical current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 10.2 10.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 10.3.1 10.3.2 10.3.3 10.3.4 10.3.5 10.3.6 10.3.7 10.3.8 10.3.9 VCAP external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 External clock sources and timing characteristics . . . . . . . . . . . . . . . . . 65 Internal clock sources and timing characteristics . . . . . . . . . . . . . . . . . 67 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Reset pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 SPI serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 I2C interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 10.3.10 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 10.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 11 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 11.1 11.2 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 11.1.1 LQFP package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 11.2.1 11.2.2 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . . 97 Doc ID 14733 Rev 9 3/103 Contents STM8S207xx, STM8S208xx 12 STM8 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 12.1 12.2 Emulation and in-circuit debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . 98 Software tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 12.2.1 12.2.2 STM8 toolset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 C and assembly toolchains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 12.3 Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 13 14 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 4/103 Doc ID 14733 Rev 9 STM8S207xx, STM8S208xx List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 STM8S20xxx performance line features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers . . . . . . . . . . . . . . . 16 TIM timer features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Legend/abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Flash, Data EEPROM and RAM boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 I/O port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 General hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 CPU/SWIM/debug module/interrupt controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Unique ID registers (96 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Operating conditions at power-up/power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Total current consumption with code execution in run mode at VDD = 5 V . . . . . . . . . . . . . 58 Total current consumption with code execution in run mode at VDD = 3.3 V . . . . . . . . . . . 59 Total current consumption in wait mode at VDD = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Total current consumption in wait mode at VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Total current consumption in active halt mode at VDD = 5 V, TA -40 to 85° C . . . . . . . . . . 61 Total current consumption in active halt mode at VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . 61 Total current consumption in halt mode at VDD = 5 V, TA -40 to 85° C . . . . . . . . . . . . . . . 62 Total current consumption in halt mode at VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Wakeup times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Total current consumption and timing in forced reset state . . . . . . . . . . . . . . . . . . . . . . . . 63 Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 HSE user external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Flash program memory/data EEPROM memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Output driving current (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Output driving current (true open drain ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Output driving current (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 ADC accuracy with RAIN < 10 kΩ , VDDA = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 ADC accuracy with RAIN < 10 kΩ RAIN, VDDA = 3.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 EMS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 EMI data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Doc ID 14733 Rev 9 5/103 List of tables Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. STM8S207xx, STM8S208xx ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 80-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 64-pin low profile quad flat package mechanical data (14 x 14) . . . . . . . . . . . . . . . . . . . . . 91 64-pin low profile quad flat package mechanical data (10 x 10) . . . . . . . . . . . . . . . . . . . . . 92 48-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 44-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 32-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 6/103 Doc ID 14733 Rev 9 STM8S207xx, STM8S208xx List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. STM8S20xxx performance line block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Flash memory organisation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 LQFP 80-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 LQFP 64-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 LQFP 48-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 LQFP 44-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 LQFP 32-pin pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Supply current measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 fCPUmax versus VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Typ. IDD(RUN) vs VDD, HSI RC osc, fCPU = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Typ. IDD(WFI) vs VDD, HSI RC osc, fCPU = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 HSE external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 HSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Typical HSI frequency variation vs VDD at 4 temperatures. . . . . . . . . . . . . . . . . . . . . . . . . 67 Typical LSI frequency variation vs VDD @ 25 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Typical VIL and VIH vs VDD @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Typical pull-up resistance vs VDD @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Typical pull-up current vs VDD @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Typ. VOL @ VDD = 5 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Typ. VOL @ VDD = 3.3 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Typ. VOL @ VDD = 5 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Typ. VOL @ VDD = 3.3 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Typ. VOL @ VDD = 5 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Typ. VOL @ VDD = 3.3 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Typ. VDD - VOH @ VDD = 5 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Typ. VDD - VOH @ VDD = 3.3 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Typ. VDD - VOH @ VDD = 5 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Typ. VDD - VOH @ VDD = 3.3 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Typical NRST VIL and VIH vs VDD @ 4 temperatures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Typical NRST pull-up resistance vs VDD @ 4 temperatures. . . . . . . . . . . . . . . . . . . . . . . . 77 Typical NRST pull-up current Ipu vs VDD @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . 77 Recommended reset pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Typical application with I2C bus and timing diagram(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Typical application with ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 80-pin low profile quad flat package (14 x 14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 64-pin low profile quad flat package (14 x 14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 64-pin low profile quad flat package (10 x 10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 48-pin low profile quad flat package (7 x 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 44-pin low profile quad flat package (10 x 10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 32-pin low profile quad flat package (7 x 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Doc ID 14733 Rev 9 7/103 List of figures Figure 49. STM8S207xx, STM8S208xx STM8S207xx/208xx performance line ordering information scheme(1) . . . . . . . . . . . . . . 100 8/103 Doc ID 14733 Rev 9 STM8S207xx, STM8S208xx Introduction 1 Introduction This datasheet contains the description of the STM8S20xxx performance line features, pinout, electrical characteristics, mechanical data and ordering information. ● For complete information on the STM8S microcontroller memory, registers and peripherals, please refer to the STM8S microcontroller family reference manual (RM0016). For information on programming, erasing and protection of the internal Flash memory please refer to the STM8S Flash programming manual (PM0051). For information on the debug and SWIM (single wire interface module) refer to the STM8 SWIM communication protocol and debug module user manual (UM0470). For information on the STM8 core, please refer to the STM8 CPU programming manual (PM0044). ● ● ● Doc ID 14733 Rev 9 9/103 Description STM8S207xx, STM8S208xx 2 Description The STM8S20xxx performance line 8-bit microcontrollers offer from 32 to 128 Kbytes Flash program memory. They are referred to as high-density devices in the STM8S microcontroller family Reference Manual (RM0016). All devices of the STM8S20xxx performance line provide the following benefits: ● Reduced system cost – – Integrated true data EEPROM for up to 300 k write/erase cycles High system integration level with internal clock oscillators, watchdog and brownout reset. 20 MIPS at 24 MHz CPU clock frequency Robust I/O, independent watchdogs with separate clock source Clock security system Applications scalability across a common family product architecture with compatible pinout, memory map and and modular peripherals. Full documentation and a wide choice of development tools Advanced core and peripherals made in a state-of-the art technology A family of products for applications with 2.95 V to 5.5 V operating supply ● Performance and robustness – – – ● Short development cycles – – ● Product longevity – – 10/103 Doc ID 14733 Rev 9 STM8S207xx, STM8S208xx Table 2. STM8S20xxx performance line features Timer complementary outputs Maximum number of GPIOs (I/O) Timer CAPCOM channels A/D Converter channels High density Flash Program memory (bytes) Data EEPROM (bytes) Description Ext. Interrupt pins Device STM8S207MB STM8S207M8 STM8S207RB STM8S207R8 STM8S207R6 STM8S207CB STM8S207C8 STM8S207C6 STM8S207SB STM8S207S8 STM8S207S6 STM8S207K6 STM8S208MB STM8S208RB STM8S208R8 STM8S208R6 STM8S208CB STM8S208C8 STM8S208C6 STM8S208SB STM8S208S8 STM8S208S6 80 80 64 64 64 48 48 48 44 44 44 32 80 64 64 64 48 48 48 44 44 44 68 68 52 52 52 38 38 38 34 34 34 25 68 52 52 52 38 38 38 34 34 34 37 37 36 36 36 35 35 35 31 31 31 23 37 37 37 37 35 35 35 31 31 31 9 9 9 9 9 9 9 9 8 8 8 8 9 9 9 9 9 9 9 8 8 8 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 16 16 16 16 16 10 10 10 9 9 9 7 16 16 16 16 10 10 10 9 9 9 18 18 16 16 16 16 16 16 15 15 15 12 18 16 16 16 16 16 16 15 15 15 128 K 64 K 128 K 64 K 32 K 128 K 64 K 32 K 128 K 64 K 32 K 32 K 128 K 128 K 64 K 32 K 128 K 64 K 32 K 128 K 64 K 32 K 2048 2048 2048 1536 1024 2048 1536 1024 1536 1536 1024 1024 2048 2048 2048 2048 2048 2048 2048 1536 1536 1536 6K 6K 6K 4K 2K 6K 4K 2K 4K 4K 2K 2K 6K 6K 6K 6K 6K 6K 6K 4K 4K 4K No Yes Doc ID 14733 Rev 9 11/103 beCAN interface High sink I/Os RAM (bytes) Pin count Block diagram STM8S207xx, STM8S208xx 3 Block diagram Figure 1. STM8S20xxx performance line block diagram Reset block Clock controller Reset Reset XTAL 1-24 MHz RC int. 16 MHz Detector POR BOR RC int. 128 kHz Clock to peripherals and core Window WDG STM8 core Independent WDG Single wire debug interf. Debug/SWIM Up to 128 Kbytes high density program Flash Up to 2 Kbytes data EEPROM Address and data bus Up to 6 Kbytes RAM Boot ROM Up to 4 CAPCOM channels + 3 complementary outputs Up to 5 CAPCOM channels 400 Kbit/s I2C 10 Mbit/s SPI LIN master SPI emul. UART1 Master/slave autosynchro UART3 16-bit advanced control timer (TIM1) 1 Mbit/s beCAN 16-bit general purpose timers (TIM2, TIM3) 16 channels ADC2 8-bit basic timer (TIM4) 1/2/4 kHz beep Beeper AWU timer 12/103 Doc ID 14733 Rev 9 STM8S207xx, STM8S208xx Product overview 4 Product overview The following section intends to give an overview of the basic features of the STM8S20xxx performance line functional modules and peripherals. For more detailed information please refer to the corresponding family reference manual (RM0016). 4.1 Central processing unit STM8 The 8-bit STM8 core is designed for code efficiency and performance. It contains 6 internal registers which are directly addressable in each execution context, 20 addressing modes including indexed indirect and relative addressing and 80 instructions. Architecture and registers ● ● ● ● ● ● ● ● Harvard architecture 3-stage pipeline 32-bit wide program memory bus - single cycle fetching for most instructions X and Y 16-bit index registers - enabling indexed addressing modes with or without offset and read-modify-write type data manipulations 8-bit accumulator 24-bit program counter - 16-Mbyte linear memory space 16-bit stack pointer - access to a 64 K-level stack 8-bit condition code register - 7 condition flags for the result of the last instruction Addressing ● ● ● 20 addressing modes Indexed indirect addressing mode for look-up tables located anywhere in the address space Stack pointer relative addressing mode for local variables and parameter passing Instruction set ● ● ● ● ● ● ● 80 instructions with 2-byte average instruction size Standard data movement and logic/arithmetic functions 8-bit by 8-bit multiplication 16-bit by 8-bit and 16-bit by 16-bit division Bit manipulation Data transfer between stack and accumulator (push/pop) with direct stack access Data transfer using the X and Y registers or direct memory-to-memory transfers Doc ID 14733 Rev 9 13/103 Product overview STM8S207xx, STM8S208xx 4.2 Single wire interface module (SWIM) and debug module (DM) The single wire interface module and debug module permits non-intrusive, real-time incircuit debugging and fast memory programming. SWIM Single wire interface module for direct access to the debug module and memory programming. The interface can be activated in all device operation modes. The maximum data transmission speed is 145 bytes/ms. Debug module The non-intrusive debugging module features a performance close to a full-featured emulator. Beside memory and peripherals, also CPU operation can be monitored in realtime by means of shadow registers. ● ● ● ● R/W to RAM and peripheral registers in real-time R/W access to all resources by stalling the CPU Breakpoints on all program-memory instructions (software breakpoints) Two advanced breakpoints, 23 predefined configurations 4.3 Interrupt controller ● ● ● ● Nested interrupts with three software priority levels 32 interrupt vectors with hardware priority Up to 37 external interrupts on six vectors including TLI Trap and reset interrupts 14/103 Doc ID 14733 Rev 9 STM8S207xx, STM8S208xx Product overview 4.4 Flash program and data EEPROM memory ● ● ● ● Up to 128 Kbytes of high density Flash program single voltage Flash memory Up to 2K bytes true data EEPROM Read while write: Writing in data memory possible while executing code in program memory. User option byte area Write protection (WP) Write protection of Flash program memory and data EEPROM is provided to avoid unintentional overwriting of memory that could result from a user software malfunction. There are two levels of write protection. The first level is known as MASS (memory access security system). MASS is always enabled and protects the main Flash program memory, data EEPROM and option bytes. To perform in-application programming (IAP), this write protection can be removed by writing a MASS key sequence in a control register. This allows the application to write to data EEPROM, modify the contents of main program memory or the device option bytes. A second level of write protection, can be enabled to further protect a specific area of memory known as UBC (user boot code). Refer to Figure 2. The size of the UBC is programmable through the UBC option byte (Table 13.), in increments of 1 page (512 bytes) by programming the UBC option byte in ICP mode. This divides the program memory into two areas: ● ● Main program memory: Up to 128 Kbytes minus UBC User-specific boot code (UBC): Configurable up to 128 Kbytes The UBC area remains write-protected during in-application programming. This means that the MASS keys do not unlock the UBC area. It protects the memory used to store the boot program, specific code libraries, reset and interrupt vectors, the reset routine and usually the IAP and communication routines. Figure 2. Flash memory organisation Data EEPROM memory Data memory area (2 Kbytes) Option bytes UBC area Remains write protected during IAP Up to 128 Kbytes Flash program memory Programmable area from 1 Kbyte (2 first pages) up to 128 Kbytes (1 page steps) Program memory area Write access possible for IAP Doc ID 14733 Rev 9 15/103 Product overview STM8S207xx, STM8S208xx Read-out protection (ROP) The read-out protection blocks reading and writing the Flash program memory and data EEPROM memory in ICP mode (and debug mode). Once the read-out protection is activated, any attempt to toggle its status triggers a global erase of the program and data memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller. 4.5 Clock controller The clock controller distributes the system clock (fMASTER) coming from different oscillators to the core and the peripherals. It also manages clock gating for low power modes and ensures clock robustness. Features ● Clock prescaler: To get the best compromise between speed and current consumption the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler. Safe clock switching: Clock sources can be changed safely on the fly in run mode through a configuration register. The clock signal is not switched until the new clock source is ready. The design guarantees glitch-free switching. Clock management: To reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory. Master clock sources: Four different clock sources can be used to drive the master clock: – – – – 1-24 MHz high-speed external crystal (HSE) Up to 24 MHz high-speed user-external clock (HSE user-ext) 16 MHz high-speed internal RC oscillator (HSI) 128 kHz low-speed internal RC (LSI) ● ● ● ● Startup clock: After reset, the microcontroller restarts by default with an internal 2 MHz clock (HSI/8). The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts. Clock security system (CSS): This feature can be enabled by software. If an HSE clock failure occurs, the internal RC (16 MHz/8) is automatically selected by the CSS and an interrupt can optionally be generated. Configurable main clock output (CCO): This outputs an external clock for use by the application. Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers Peripheral clock TIM1 TIM3 TIM2 TIM4 Bit PCKEN13 PCKEN12 PCKEN11 PCKEN10 Peripheral clock UART3 UART1 SPI I2C Bit PCKEN27 PCKEN26 PCKEN25 PCKEN24 Peripheral clock beCAN Reserved Reserved Reserved Bit PCKEN23 PCKEN22 PCKEN21 PCKEN20 Peripheral clock ADC AWU Reserved Reserved ● ● Table 3. Bit PCKEN17 PCKEN16 PCKEN15 PCKEN14 16/103 Doc ID 14733 Rev 9 STM8S207xx, STM8S208xx Product overview 4.6 Power management For efficent power management, the application can be put in one of four different low-power modes. You can configure each mode to obtain the best compromise between lowest power consumption, fastest start-up time and available wakeup sources. ● ● Wait mode: In this mode, the CPU is stopped, but peripherals are kept running. The wakeup is performed by an internal or external interrupt or reset. Active halt mode with regulator on: In this mode, the CPU and peripheral clocks are stopped. An internal wakeup is generated at programmable intervals by the auto wake up unit (AWU). The main voltage regulator is kept powered on, so current consumption is higher than in active halt mode with regulator off, but the wakeup time is faster. Wakeup is triggered by the internal AWU interrupt, external interrupt or reset. Active halt mode with regulator off: This mode is the same as active halt with regulator on, except that the main voltage regulator is powered off, so the wake up time is slower. Halt mode: In this mode the microcontroller uses the least power. The CPU and peripheral clocks are stopped, the main voltage regulator is powered off. Wakeup is triggered by external event or reset. ● ● 4.7 Watchdog timers The watchdog system is based on two independent timers providing maximum security to the applications. Activation of the watchdog timers is controlled by option bytes or by software. Once activated, the watchdogs cannot be disabled by the user program without performing a reset. Window watchdog timer The window watchdog is used to detect the occurrence of a software fault, usually generated by external interferences or by unexpected logical conditions, which cause the application program to abandon its normal sequence. The window function can be used to trim the watchdog behavior to match the application perfectly. The application software must refresh the counter before time-out and during a limited time window. A reset is generated in two situations: 1. 2. Timeout: At 16 MHz CPU clock the time-out period can be adjusted between 75 µs up to 64 ms. Refresh out of window: The downcounter is refreshed before its value is lower than the one stored in the window register. Doc ID 14733 Rev 9 17/103 Product overview STM8S207xx, STM8S208xx Independent watchdog timer The independent watchdog peripheral can be used to resolve processor malfunctions due to hardware or software failures. It is clocked by the 128 kHZ LSI internal RC clock source, and thus stays active even in case of a CPU clock failure The IWDG time base spans from 60 µs to 1 s. 4.8 Auto wakeup counter ● ● ● Used for auto wakeup from active halt mode Clock source: Internal 128 kHz internal low frequency RC oscillator or external clock LSI clock can be internally connected to TIM3 input capture channel 1 for calibration 4.9 Beeper The beeper function outputs a signal on the BEEP pin for sound generation. The signal is in the range of 1, 2 or 4 kHz. 4.10 TIM1 - 16-bit advanced control timer This is a high-end timer designed for a wide range of control applications. With its complementary outputs, dead-time control and center-aligned PWM capability, the field of applications is extended to motor control, lighting and half-bridge driver ● ● 16-bit up, down and up/down autoreload counter with 16-bit prescaler Four independent capture/compare channels (CAPCOM) configurable as input capture, output compare, PWM generation (edge and center aligned mode) and single pulse mode output Synchronization module to control the timer with external signals Break input to force the timer outputs into a defined state Three complementary outputs with adjustable dead time Encoder mode Interrupt sources: 3 x input capture/output compare, 1 x overflow/update, 1 x break ● ● ● ● ● 4.11 TIM2, TIM3 - 16-bit general purpose timers ● ● ● ● ● 16-bit autoreload (AR) up-counter 15-bit prescaler adjustable to fixed power of 2 ratios 1…32768 Timers with 3 or 2 individually configurable capture/compare channels PWM mode Interrupt sources: 2 or 3 x input capture/output compare, 1 x overflow/update 18/103 Doc ID 14733 Rev 9 STM8S207xx, STM8S208xx Product overview 4.12 TIM4 - 8-bit basic timer ● ● ● 8-bit autoreload, adjustable prescaler ratio to any power of 2 from 1 to 128 Clock source: CPU clock Interrupt source: 1 x overflow/update Table 4. TIM timer features Counter size (bits) 16 16 16 8 Counting CAPCOM Complem. Ext. mode trigger channels outputs Up/down Up Up Up 4 3 2 0 3 0 0 0 Yes No No No No Timer synchronization/ chaining Timer Prescaler TIM1 TIM2 TIM3 TIM4 Any integer from 1 to 65536 Any power of 2 from 1 to 32768 Any power of 2 from 1 to 32768 Any power of 2 from 1 to 128 4.13 Analog-to-digital converter (ADC2) STM8S20xxx performance line products contain a 10-bit successive approximation A/D converter (ADC2) with up to 16 multiplexed input channels and the following main features: ● ● ● ● ● ● ● Input voltage range: 0 to VDDA Dedicated voltage reference (VREF) pins available on 80 and 64-pin devices Conversion time: 14 clock cycles Single and continuous modes External trigger input Trigger from TIM1 TRGO End of conversion (EOC) interrupt 4.14 Communication interfaces The following communication interfaces are implemented: ● ● ● ● ● UART1: Full feature UART, SPI emulation, LIN2.1 master capability, Smartcard mode, IrDA mode, single wire mode. UART3: Full feature UART, LIN2.1 master/slave capability SPI : Full and half-duplex, 10 Mbit/s I²C: Up to 400 Kbit/s beCAN (rev. 2.0A,B) - 3 Tx mailboxes - up to 1 Mbit/s Doc ID 14733 Rev 9 19/103 Product overview STM8S207xx, STM8S208xx 4.14.1 UART1 Main features ● ● ● ● ● ● ● One Mbit/s full duplex SCI SPI emulation High precision baud rate generator Smartcard emulation IrDA SIR encoder decoder LIN master mode Single wire half duplex mode Asynchronous communication (UART mode) ● ● ● ● Full duplex communication - NRZ standard format (mark/space) Programmable transmit and receive baud rates up to 1 Mbit/s (fCPU/16) and capable of following any standard baud rate regardless of the input frequency Separate enable bits for transmitter and receiver Two receiver wakeup modes: – – Address bit (MSB) Idle line (interrupt) ● ● Transmission error detection with interrupt generation Parity control Synchronous communication ● ● ● ● Full duplex synchronous transfers SPI master operation 8-bit data communication Maximum speed: 1 Mbit/s at 16 MHz (fCPU/16) LIN master mode ● ● Emission: Generates 13-bit synch break frame Reception: Detects 11-bit break frame 4.14.2 UART3 Main features ● ● ● 1 Mbit/s full duplex SCI LIN master capable High precision baud rate generator 20/103 Doc ID 14733 Rev 9 STM8S207xx, STM8S208xx Product overview Asynchronous communication (UART mode) ● ● ● ● Full duplex communication - NRZ standard format (mark/space) Programmable transmit and receive baud rates up to 1 Mbit/s (fCPU/16) and capable of following any standard baud rate regardless of the input frequency Separate enable bits for transmitter and receiver Two receiver wakeup modes: – – Address bit (MSB) Idle line (interrupt) ● ● Transmission error detection with interrupt generation Parity control LIN master capability ● ● Emission: Generates 13-bit synch break frame Reception: Detects 11-bit break frame LIN slave mode ● ● ● ● ● ● ● Autonomous header handling - one single interrupt per valid message header Automatic baud rate synchronization - maximum tolerated initial clock deviation ±15 % Synch delimiter checking 11-bit LIN synch break detection - break detection always active Parity check on the LIN identifier field LIN error management Hot plugging support 4.14.3 SPI ● ● ● ● ● ● ● Maximum speed: 10 Mbit/s (fMASTER/2) both for master and slave Full duplex synchronous transfers Simplex synchronous transfers on two lines with a possible bidirectional data line Master or slave operation - selectable by hardware or software CRC calculation 1 byte Tx and Rx buffer Slave/master selection input pin Doc ID 14733 Rev 9 21/103 Product overview STM8S207xx, STM8S208xx 4.14.4 I2C ● I2C master features: – – Clock generation Start and stop generation slave features: Programmable I2C address detection Stop bit detection ● I2C – – ● ● Generation and detection of 7-bit/10-bit addressing and general call Supports different communication speeds: – – Standard speed (up to 100 kHz) Fast speed (up to 400 kHz) 4.14.5 beCAN The beCAN controller (basic enhanced CAN), interfaces the CAN network and supports the CAN protocol version 2.0A and B. It has been designed to manage a high number of incoming messages efficiently with a minimum CPU load. For safety-critical applications the beCAN controller provides all hardware functions to support the CAN time triggered communication option (TTCAN). The maximum transmission speed is 1 Mbit. Transmission ● ● ● Three transmit mailboxes Configurable transmit priority by identifier or order request Time stamp on SOF transmission Reception ● ● ● ● ● ● ● ● 8-, 11- and 29-bit ID One receive FIFO (3 messages deep) Software-efficient mailbox mapping at a unique address space FMI (filter match index) stored with message Configurable FIFO overrun Time stamp on SOF reception Six filter banks, 2 x 32 bytes (scalable to 4 x 16-bit) each, enabling various masking configurations, such as 12 filters for 29-bit ID or 48 filters for 11-bit ID Filtering modes: – – Mask mode permitting ID range filtering ID list mode Disable automatic retransmission mode 16-bit free running timer Configurable timer resolution Time stamp sent in last two data bytes ● Time triggered communication option – – – – 22/103 Doc ID 14733 Rev 9 STM8S207xx, STM8S208xx Pinouts and pin description 5 5.1 Pinouts and pin description Package pinouts Figure 3. LQFP 80-pin pinout 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 NRST OSCIN/PA1 OSCOUT/PA2 VSSIO_1 VSS VCAP VDD VDDIO_1 [TIM3_CH1] TIM2_CH3/PA3 UART1_RX/ (HS) PA4 UART1_TX/ (HS) PA5 UART1_CK/ (HS) PA6 (HS) PH0 (HS) PH1 PH2 PH3 AIN15/PF7 AIN14/PF6 AIN13/PF5 AIN12/PF4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 PD7/TLI [TIM1_CH4] PD6/UART3_RX PD5/UART3_TX PD4 (HS)/TIM2_CH1 [BEEP] PD3 (HS)/TIM2_CH2 [ADC_ETR] PD2 (HS)/TIM3_CH1 [TIM2_CH3] PD1 (HS)/SWIM PD0 (HS)/TIM3_CH2 [TIM1_BKIN] [CLK_CCO] PI7 PI6 PE0 (HS)/CLK_CCO PE1(T)/I2C_SCL PE2 (T]/I 2C_SDA PE3/TIM1_BKIN PE4 PG7 PG6 PG5 PI5 PI4 PI3 PI2 PI1 PI0 PG4 PG3 PG2 PG1/CAN_RX PG0/CAN_TX PC7 (HS)/SPI_MISO PC6 (HS)/SPI_MOSI VDDIO_2 VSSIO_2 PC5 (HS)/SPI_SCK PC4 (HS)/TIM1_CH4 PC3 (HS)/TIM1_CH3 PC2 (HS)/TIM1_CH2 PC1 (HS)/TIM1_CH1 PC0/ADC_ETR PE5/SPI_NSS 1. 2. 3. 4. (HS) high sink capability. (T) True open drain (P-buffer and protection diode to VDD not implemented). [ ] alternate function remapping option (If the same alternate function is shown twice, it indicates an exclusive choice not a duplication of the function). CAN_RX and CAN_TX is available on STM8S208xx devices only. AIN11/PF3 VREF+ VDDA VSSA VREFAIN10/PF0 AIN7/PB7 AIN6/PB6 [I2C_SDA] AIN5/PB5 [I2C_SCL] AIN4/PB4 [TIM1_ETR] AIN3/PB3 [TIM1_CH3N] AIN2/PB2 [TIM1_CH2N] AIN1/PB1 [TIM1_CH1N] AIN0/PB0 TIM1_ETR/PH4 TIM1_CH3N/PH5 TIM1_CH2N/PH6 TIM1_CH1N/PH7 AIN8/PE7 AIN9/PE6 Doc ID 14733 Rev 9 23/103 Pinouts and pin description Figure 4. LQFP 64-pin pinout STM8S207xx, STM8S208xx NRST OSCIN/PA1 OSCOUT/PA2 VSSIO_1 VSS VCAP VDD VDDIO_1 [TIM3_CH1] TIM2_CH3/PA3 UART1_RX/ (HS) PA4 UART1_TX/ (HS) PA5 UART1_CK/ (HS) PA6 AIN15/PF7 AIN14/PF6 AIN13/PF5 AIN12/PF4 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 1 47 2 46 3 45 4 44 5 43 6 42 7 41 8 40 9 39 10 38 11 37 12 36 13 35 14 34 15 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 AIN11/PF3 VREF+ VDDA VSSA VREFAIN10/PF0 AIN7/PB7 AIN6/PB6 [I2C_SDA] AIN5/PB5 [I2C_SCL] AIN4/PB4 [TIM1_ETR] AIN3/PB3 [TIM1_CH3N] AIN2/PB2 [TIM1_CH2N] AIN1/PB1 [TIM1_CH1N] AIN0/PB0 AIN8/PE7 AIN9/PE6 PD7/TLI [TIM1_CH4] PD6/UART3_RX PD5/UART3_TX PD4 (HS)/TIM2_CH1 [BEEP] PD3 (HS)/TIM2_CH2[ADC_ETR] PD2 (HS)/TIM3_CH1[TIM2_CH3] PD1 (HS)/SWIM PD0 (HS)/TIM3_CH2 [TIM1_BKIN] [CLK_CCO] PE0 (HS)/CLK_CCO PE1 (T)/I2C_SCL PE2 (T)/I2C_SDA PE3/TIM1_BKIN PE4 PG7 PG6 PG5 PI0 PG4 PG3 PG2 PG1/CAN_RX PG0/CAN_TX PC7 (HS)/SPI_MISO PC6 (HS)/SPI_MOSI VDDIO_2 VSSIO_2 PC5 (HS)/SPI_SCK PC4 (HS)/TIM1_CH4 PC3 (HS)/TIM1_CH3 PC2 (HS)/TIM1_CH2 PC1 (HS)/TIM1_CH1 PE5/SPI_NSS 1. 2. 3. 4. (HS) high sink capability. (T) True open drain (P-buffer and protection diode to VDD not implemented). [ ] alternate function remapping option (If the same alternate function is shown twice, it indicates an exclusive choice not a duplication of the function). CAN_RX and CAN_TX is available on STM8S208xx devices only. 24/103 Doc ID 14733 Rev 9 STM8S207xx, STM8S208xx Figure 5. LQFP 48-pin pinout PD7/TLI [TIM1_CH4] PD6/UART3_RX PD5/UART3_TX PD4 (HS)/TIM2_CH1 [BEEP] PD3 (HS)/TIM2_CH2 [ADC_ETR] PD2 (HS)/TIM3_CH1 [TIM2_CH3] PD1 (HS)/SWIM PD0 (HS)/TIM3_CH2 [TIM1_BKIN] [CLK_CCO] PE0 (HS)/CLK_CCO PE1 (T)/I2C_SCL PE2 (T)/I2C_SDA PE3/TIM1_BKIN Pinouts and pin description NRST OSCIN/PA1 OSCOUT/PA2 VSSIO_1 VSS VCAP VDD VDDIO_1 [TIM3_CH1] TIM2_CH3/PA3 UART1_RX/(HS) PA4 UART1_TX/(HS) PA5 UART1_CK/(HS) PA6 48 47 46 45 44 43 42 41 40 39 38 37 36 1 2 35 34 3 33 4 32 5 31 6 30 7 29 8 28 9 27 10 26 11 25 12 13 14 15 16 17 18 19 20 21 2223 24 VDDA VSSA AIN7/PB7 AIN6/PB6 [I2C_SDA] AIN5/PB5 [I2C_SCL] AIN4/PB4 [TIM1_ETR/AIN3/PB3 [TIM1_CH3N] AIN2/PB2 [TIM1_CH2N] AIN1/PB1 [TIM1_CH1N] AIN0/PB0 AIN8/PE7 AIN9/PE6 PG1/CAN_RX PG0/CAN_TX PC7 (HS)/SPI_MISO PC6 (HS)/SPI_MOSI VDDIO_2 VSSIO_2 PC5 (HS)/SPI_SCK PC4 (HS)/TIM1_CH4 PC3 (HS)/TIM1_CH3 PC2 (HS)/TIM1_CH2 PC1 (HS)/TIM1_CH1 PE5/SPI_NSS 1. 2. 3. 4. (HS) high sink capability. (T) True open drain (P-buffer and protection diode to VDD not implemented). [ ] alternate function remapping option (If the same alternate function is shown twice, it indicates an exclusive choice not a duplication of the function). CAN_RX and CAN_TX is available on STM8S208xx devices only. Doc ID 14733 Rev 9 25/103 Pinouts and pin description Figure 6. LQFP 44-pin pinout STM8S207xx, STM8S208xx NRST OSCIN/PA1 OSCOUT/PA2 VSSIO_1 VSS VCAP VDD VDDIO_1 UART1_RX/ UART1_TX/ UART1_CK/ 44 43 42 41 40 39 38 37 36 35 34 1 33 2 32 3 31 4 30 5 29 6 28 7 27 8 26 9 25 10 24 11 23 12 13 14 15 16 17 18 19 20 21 22 VDDA VSSA AIN7/PB7 AIN6/PB6 [I2C_SDA] AIN5/PB5 [I2C_SCL] AIN4/PB4 [TIM1_ETR] AIN3/PB3 [TIM1_CH3N] AIN2/PB2 [TIM1_CH2N] AIN1/PB1 (TIM1_CH1N] AIN0/PB0 AIN9/PE6 PD7/TLI [TIM1_CH4] PD6/UART3_RX PD5/UART3_TX PD4 (HS)/TIM2_CH1[BEEP] PD3 (HS)/TIM2_CH2 [ADC_ETR] PD2 (HS)/TIM3_CH1 [TIM2_CH3] PD1 (HS)/SWIM PD0 (HS)/TIM3_CH2 [TIM1_BKIN] [CLK_CCO] PE0 (HS)/CLK_CCO PE1 (T)/I2C_SCL PE2 (T)/I2C_SDA PG1/CAN_RX PG0/CAN_TX PC7 (HS)/SPI_MISO PC6 (HS)/SPI_MOSI VDDIO_2 VSSIO_2 PC5 (HS)/SPI_SCK PC3 (HS)/TIM1_CH3 PC2 (HS)/TIM1_CH2 PC1 (HS)/TIM1_CH1 PE5/SPI_NSS 1. 2. 3. 4. (HS) high sink capability. (T) True open drain (P-buffer and protection diode to VDD not implemented). [ ] alternate function remapping option (If the same alternate function is shown twice, it indicates an exclusive choice not a duplication of the function). CAN_RX and CAN_TX is available on STM8S208xx devices only. 26/103 Doc ID 14733 Rev 9 STM8S207xx, STM8S208xx Figure 7. LQFP 32-pin pinout PD7/TLI [TIM1_CH4] PD6/UART3_RX PD5/UART3_TX PD4 (HS)/TIM2_CH1 [BEEP] PD3 (HS)/TIM2_CH2 [ADC_ETR] PD2 (HS)/TIM3_CH1[TIM2_CH3] PD1 (HS)/SWIM PD0 (HS)/TIM3_CH2 [TIM1_BKIN] [CLK_CCO] Pinouts and pin description NRST OSCIN/PA1 OSCOUT/PA2 VSS VCAP VDD VDDIO AIN12/PF4 1 2 3 4 5 6 7 8 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 9 10 11 12 13 14 1516 VDDA VSSA [I2C_SDA] AIN5/PB5 [I2C_SCL] AIN4/PB4 [TIM1_ETR] AIN3/PB3 [TIM1_CH3N] AIN2/PB2 [TIM1_CH2N] AIN1/PB1 [TIM1_CH1N] AIN0/PB0 PC7 (HS)/SPI_MISO PC6 (HS)/SPI_MOSI PC5 (HS)/SPI_SCK PC4 (HS)/TIM1_CH4 PC3 (HS)/TIM1_CH3 PC2 (HS)/TIM1_CH2 PC1 (HS)/TIM1_CH1 PE5/SPI_NSS 1. 2. (HS) high sink capability. [ ] alternate function remapping option (If the same alternate function is shown twice, it indicates an exclusive choice not a duplication of the function). Table 5. Type Level Legend/abbreviations I= Input, O = Output, S = Power supply Input Output CM = CMOS HS = High sink Output speed O1 = Slow (up to 2 MHz) O2 = Fast (up to 10 MHz) O3 = Fast/slow programmability with slow as default state after reset O4 = Fast/slow programmability with fast as default state after reset float = floating, wpu = weak pull-up T = True open drain, OD = Open drain, PP = Push pull Port and control Input configuration Output Reset state Bold X Doc ID 14733 Rev 9 27/103 Pinouts and pin description Table 6. Pin description Main function (after reset) Input Ext. interrupt Type High sink LQFP32 floating Output STM8S207xx, STM8S208xx Pin number LQFP80 LQFP64 LQFP48 LQFP44 Speed wpu OD Pin name 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 NRST 2 PA1/OSCIN 3 PA2/OSCOUT - VSSIO_1 4 VSS 5 VCAP 6 VDD 7 VDDIO_1 - PA3/TIM2_CH3 I/O I/O X I/O X S S S S S I/O X X X X X O1 X O1 X PP Default alternate function Alternate function after remap [option bit] Reset X Port A1 X Port A2 Resonator/ crystal in Resonator/ crystal out I/O ground Digital ground 1.8 V regulator capacitor Digital power supply I/O power supply X X X X O1 X X Port A3 Timer 2 channel3 TIM3_CH1 [AFR1] 10 10 10 - PA4/UART1_RX(1) I/O X - PA5/UART1_TX I/O X X HS O3 X X HS O3 X X Port A4 UART1 receive X Port A5 UART1 transmit 11 11 11 10 12 12 12 11 13 14 15 16 - - PA6/UART1_CK - PH0 - PH1 - PH2 - PH3 - PF7/AIN15 - PF6/AIN14 - PF5/AIN13 8 PF4/AIN12 - PF3/AIN11 - VREF+ 9 VDDA I/O X I/O X I/O X I/O X I/O X I/O X I/O X I/O X I/O X I/O X S S X X X X X X X X X X X HS O3 X HS O3 X HS O3 X O1 X O1 X O1 X O1 X O1 X O1 X O1 X UART1 X Port A6 synchronous clock X Port H0 X Port H1 X Port H2 X Port H3 X X X X X Port F7 Port F6 Port F5 Port F4 Port F3 Analog input 15 Analog input 14 Analog input 13 Analog input 12 Analog input 11 17 13 18 14 19 15 20 16 21 17 22 18 ADC positive reference voltage Analog power supply 23 19 13 12 28/103 Doc ID 14733 Rev 9 STM8S207xx, STM8S208xx Table 6. Pin description (continued) Pinouts and pin description Main function (after reset) Pin number Type LQFP80 LQFP64 LQFP48 LQFP44 LQFP32 floating Input Ext. interrupt High sink Output Speed wpu OD Pin name 24 20 14 13 10 VSSA 25 21 26 22 - VREF- PF0/AIN10 - PB7/AIN7 - PB6/AIN6 S S I/O X I/O X I/O X I/O X I/O X I/O X X X X X X X X X X X X O1 X O1 X O1 X O1 X O1 X O1 X X PP Default alternate function Alternate function after remap [option bit] Analog ground ADC negative reference voltage Port F0 Analog input 10 Analog input 7 Analog input 6 Analog input 5 Analog input 4 Analog input 3 Analog input 2 Analog input 1 Analog input 0 Timer 1 trigger input I2C_SDA [AFR6] I2C_SCL [AFR6] TIM1_ETR [AFR5] TIM1_ CH3N [AFR5] TIM1_ CH2N [AFR5] TIM1_ CH1N [AFR5] 27 23 15 14 28 24 16 15 X Port B7 X Port B6 X Port B5 X Port B4 X Port B3 29 25 17 16 11 PB5/AIN5 30 26 18 17 12 PB4/AIN4 31 27 19 18 13 PB3/AIN3 32 28 20 19 14 PB2/AIN2 I/O X X X O1 X X Port B2 33 29 21 20 15 PB1/AIN1 I/O X X X O1 X X Port B1 34 30 22 21 16 PB0/AIN0 I/O X X X O1 X X Port B0 35 - - - - PH4/TIM1_ETR I/O X X O1 X X Port H4 36 - - - - PH5/ TIM1_CH3N I/O X X O1 X Timer 1 X Port H5 inverted channel 3 Timer 1 X Port H6 inverted channel 2 Timer 1 X Port H7 inverted channel 2 X X Port E7 Analog input 8 Port E6 Analog input 9 37 - - - - PH6/ TIM1_CH2N I/O X X O1 X 38 - - - - PH7/ TIM1_CH1N I/O X - PE7/AIN8 - PE6/AIN9 I/O X I/O X X X X X X O1 X O1 X O1 X 39 31 23 40 32 24 22 Doc ID 14733 Rev 9 29/103 Pinouts and pin description Table 6. Pin description (continued) Main function (after reset) Input Ext. interrupt Type High sink LQFP32 floating Output STM8S207xx, STM8S208xx Pin number LQFP80 LQFP64 LQFP48 LQFP44 Speed wpu OD Pin name PP Default alternate function Alternate function after remap [option bit] 41 33 25 23 17 PE5/SPI_NSS I/O X X X O1 X X SPI Port E5 master/slave select ADC trigger input Timer 1 channel 1 Timer 1channel 2 Timer 1 channel 3 Timer 1 channel 4 42 - - - - PC0/ADC_ETR I/O X I/O X I/O X I/O X I/O X I/O X S S I/O X X X X X X X X O1 X X Port C0 X Port C1 X Port C2 X Port C3 X Port C4 43 34 26 24 18 PC1/TIM1_CH1 44 35 27 25 19 PC2/TIM1_CH2 45 36 28 26 20 PC3/TIM1_CH3 46 37 29 21 PC4/TIM1_CH4 X HS O3 X X HS O3 X X HS O3 X X HS O3 X X HS O3 X 47 38 30 27 22 PC5/SPI_SCK 48 39 31 28 49 40 32 29 - VSSIO_2 - VDDIO_2 X Port C5 SPI clock I/O ground I/O power supply 50 41 33 30 23 PC6/SPI_MOSI X X HS O3 X SPI master X Port C6 out/ slave in X Port C7 X Port G0 SPI master in/ slave out beCAN transmit 51 42 34 31 24 PC7/SPI_MISO 52 43 35 32 53 44 36 33 54 45 55 46 56 47 57 48 58 59 60 61 62 - PG0/CAN_TX(2) - PG1/CAN_RX(2) - PG2 - PG3 - PG4 - PI0 - PI1 - PI2 - PI3 - PI4 - PI5 - PG5 - PG6 I/O X I/O X I/O X I/O X I/O X I/O X I/O X I/O X I/O X I/O X I/O X I/O X I/O X I/O X X X X X X X X X X X X X X X X HS O3 X O1 X O1 X O1 X O1 X O1 X O1 X O1 X O1 X O1 X O1 X O1 X O1 X O1 X X Port G1 beCAN receive X Port G2 X Port G3 X Port G4 X X X X X X Port I0 Port I1 Port I2 Port I3 Port I4 Port I5 63 49 64 50 X Port G5 X Port G6 30/103 Doc ID 14733 Rev 9 STM8S207xx, STM8S208xx Table 6. Pin description (continued) Pinouts and pin description Main function (after reset) Pin number Type LQFP80 LQFP64 LQFP48 LQFP44 LQFP32 floating Input Ext. interrupt High sink Output Speed wpu OD Pin name 65 51 66 52 - - - PG7 - PE4 - PE3/TIM1_BKIN - PE2/I2C_SDA - PE1/I2C_SCL - PE0/CLK_CCO - PI6 - PI7 I/O X I/O X I/O X I/O X I/O X I/O X I/O X I/O X X X X X X X X X X X O1 X O1 X O1 X O1 T(3) O1 T(3) X Port G7 X X Port E4 Port E3 Timer 1 break input 67 53 37 PP Default alternate function Alternate function after remap [option bit] 68 54 38 34 69 55 39 35 70 56 40 36 71 72 - Port E2 I2C data Port E1 I2C clock X X X Port E0 Port I6 Port I7 TIM1_BKIN [AFR3]/ CLK_CCO [AFR2] Configurable clock output X HS O3 X O1 X O1 X 73 57 41 37 25 PD0/TIM3_CH2 I/O X X X HS O3 X Timer 3 X Port D0 channel 2 SWIM data interface Timer 3 channel 1 Timer 2 channel 2 Timer 2 channel 1 UART3 data transmit UART3 data receive Top level interrupt 74 58 42 38 26 PD1/SWIM 75 59 43 39 27 PD2/TIM3_CH1 76 60 44 40 28 PD3/TIM2_CH2 77 61 45 41 29 I/O X I/O X I/O X X X X X X X X X HS O4 X X HS O3 X X HS O3 X X HS O3 X X X X O1 X O1 X O1 X X Port D1 X Port D2 X Port D3 X Port D4 X Port D5 X Port D6 X Port D7 TIM2_CH3 [AFR1] ADC_ETR [AFR0] BEEP output [AFR7] PD4/TIM2_CH1/B I/O X EEP I/O X I/O X I/O X 78 62 46 42 30 PD5/ UART3_TX 79 63 47 43 31 PD6/ UART3_RX(1) 80 64 48 44 32 PD7/TLI TIM1_CH4 [AFR4] 1. The default state of UART1_RX and UART3_RX pins is controlled by the ROM bootloader. These pins are pulled up as part of the bootloader activation process and returned to the floating state before a return from the bootloader. 2. The beCAN interface is available on STM8S208xx devices only 3. In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer and protection diode to VDD are not implemented). Doc ID 14733 Rev 9 31/103 Pinouts and pin description STM8S207xx, STM8S208xx 5.2 Alternate function remapping As shown in the rightmost column of the pin description table, some alternate functions can be remapped at different I/O ports by programming one of eight AFR (alternate function remap) option bits. Refer to Section 8: Option bytes on page 47. When the remapping option is active, the default alternate function is no longer available. To use an alternate function, the corresponding peripheral must be enabled in the peripheral registers. Alternate function remapping does not effect GPIO capabilities of the I/O ports (see the GPIO section of the family reference manual, RM0016). 32/103 Doc ID 14733 Rev 9 STM8S207xx, STM8S208xx Memory and register map 6 6.1 Memory and register map Memory map Figure 8. Memory map 0x00 0000 RAM (up to 6 Kbytes) 1024 bytes stack Reserved 0x00 3FFF 0x00 4000 Up to 2 Kbytes data EEPROM 0x00 47FF 0x00 4800 0x00 487F 0x00 4900 0x00 4FFF 0x00 5000 0x00 57FF 0x00 5800 0x00 5FFF 0x00 6000 2 Kbytes boot ROM 0x00 67FF 0x00 6800 Reserved 0x00 7EFF 0x00 7F00 0x00 7FFF 0x00 8000 0x00 807F 0x00 8080 CPU/SWIM/debug/ITC registers (see Table 10 ) 32 interrupt vectors GPIO and peripheral registers (see Table 8 and Table 9) Reserved Option bytes Reserved 0x00 17FF 0x00 1800 Flash program memory (64 to 128 Kbytes) 0x02 7FFF Doc ID 14733 Rev 9 33/103 Memory and register map STM8S207xx, STM8S208xx Table 7 lists the boundary addresses for each memory size. The top of the stack is at the RAM end address in each case. Table 7. Flash, Data EEPROM and RAM boundary addresses Size (bytes) 128 K Flash program memory 64 K 32 K 6K RAM 4K 2K 2048 Data EEPROM 1536 1024 Start address 0x00 8000 0x00 8000 0x00 8000 0x00 0000 0x00 0000 0x00 0000 0x00 4000 0x00 4000 0x00 4000 End address 0x02 7FFF 0x01 7FFF 0x00 FFFF 0x00 17FF 0x00 1000 0x00 07FF 0x00 47FF 0x00 45FF 0x00 43FF Memory area 6.2 Register map Table 8. Address 0x00 5000 0x00 5001 0x00 5002 0x00 5003 0x00 5004 0x00 5005 0x00 5006 0x00 5007 0x00 5008 0x00 5009 0x00 500A 0x00 500B 0x00 500C 0x00 500D 0x00 500E Port C Port B Port A I/O port hardware register map Block Register label PA_ODR PA_IDR PA_DDR PA_CR1 PA_CR2 PB_ODR PB_IDR PB_DDR PB_CR1 PB_CR2 PC_ODR PB_IDR PC_DDR PC_CR1 PC_CR2 Register name Port A data output latch register Port A input pin value register Port A data direction register Port A control register 1 Port A control register 2 Port B data output latch register Port B input pin value register Port B data direction register Port B control register 1 Port B control register 2 Port C data output latch register Port C input pin value register Port C data direction register Port C control register 1 Port C control register 2 Reset status 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 34/103 Doc ID 14733 Rev 9 STM8S207xx, STM8S208xx Table 8. Address 0x00 500F 0x00 5010 0x00 5011 0x00 5012 0x00 5013 0x00 5014 0x00 5015 0x00 5016 0x00 5017 0x00 5018 0x00 5019 0x00 501A 0x00 501B 0x00 501C 0x00 501D 0x00 501E 0x00 501F 0x00 5020 0x00 5021 0x00 5022 0x00 5023 0x00 5024 0x00 5025 0x00 5026 0x00 5027 0x00 5028 0x00 5029 0x00 502A 0x00 502B 0x00 502C Port I Port H Port G Port F Port E Port D Memory and register map I/O port hardware register map (continued) Block Register label PD_ODR PD_IDR PD_DDR PD_CR1 PD_CR2 PE_ODR PE_IDR PE_DDR PE_CR1 PE_CR2 PF_ODR PF_IDR PF_DDR PF_CR1 PF_CR2 PG_ODR PG_IDR PG_DDR PG_CR1 PG_CR2 PH_ODR PH_IDR PH_DDR PH_CR1 PH_CR2 PI_ODR PI_IDR PI_DDR PI_CR1 PI_CR2 Register name Port D data output latch register Port D input pin value register Port D data direction register Port D control register 1 Port D control register 2 Port E data output latch register Port E input pin value register Port E data direction register Port E control register 1 Port E control register 2 Port F data output latch register Port F input pin value register Port F data direction register Port F control register 1 Port F control register 2 Port G data output latch register Port G input pin value register Port G data direction register Port G control register 1 Port G control register 2 Port H data output latch register Port H input pin value register Port H data direction register Port H control register 1 Port H control register 2 Port I data output latch register Port I input pin value register Port I data direction register Port I control register 1 Port I control register 2 Reset status 0x00 0x00 0x00 0x02 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 Doc ID 14733 Rev 9 35/103 Memory and register map Table 9. General hardware register map Block Register label STM8S207xx, STM8S208xx Address 0x00 5050 to 0x00 5059 0x00 505A 0x00 505B 0x00 505C 0x00 505D 0x00 505E 0x00 505F 0x00 5060 to 0x00 5061 0x00 5062 0x00 5063 0x00 5064 0x00 5065 to 0x00 509F 0x00 50A0 Register name Reset status Reserved area (10 bytes) FLASH_CR1 FLASH_CR2 FLASH_NCR2 Flash FLASH _FPR FLASH _NFPR FLASH _IAPSR Flash control register 1 Flash control register 2 Flash complementary control register 2 Flash protection register Flash complementary protection register Flash in-application programming status register Reserved area (2 bytes) Flash FLASH _PUKR Flash Program memory unprotection register Reserved area (1 byte) Flash FLASH _DUKR Data EEPROM unprotection register Reserved area (59 bytes) EXTI_CR1 ITC EXTI_CR2 External interrupt control register 1 External interrupt control register 2 Reserved area (17 bytes) RST RST_SR Reset status register Reserved area (12 bytes) CLK_ICKR CLK CLK_ECKR Internal clock control register External clock control register Reserved area (1 byte) 0x01 0x00 xx 0x00 0x00 0x00 0x00 0x00 0x00 0xFF 0x00 0xFF 0x00 0x00 50A1 0x00 50A2 to 0x00 50B2 0x00 50B3 0x00 50B4 to 0x00 50BF 0x00 50C0 0x00 50C1 0x00 50C2 36/103 Doc ID 14733 Rev 9 STM8S207xx, STM8S208xx Table 9. General hardware register map (continued) Block Register label CLK_CMSR CLK_SWR CLK_SWCR CLK_CKDIVR CLK_PCKENR1 CLK CLK_CSSR CLK_CCOR CLK_PCKENR2 CLK_CANCCR CLK_HSITRIMR CLK_SWIMCCR Memory and register map Address 0x00 50C3 0x00 50C4 0x00 50C5 0x00 50C6 0x00 50C7 0x00 50C8 0x00 50C9 0x00 50CA 0x00 50CB 0x00 50CC 0x00 50CD 0x00 50CE to 0x00 50D0 0x00 50D1 Register name Clock master status register Clock master switch register Clock switch control register Clock divider register Peripheral clock gating register 1 Clock security system register Configurable clock control register Peripheral clock gating register 2 CAN clock control register HSI clock calibration trimming register SWIM clock control register Reserved area (3 bytes) Reset status 0xE1 0xE1 0bxxxx 0000 0x18 0xFF 0x00 0x00 0xFF 0x00 xx x0 WWDG_CR WWDG WWDG_WR WWDG control register WWDR window register Reserved area (13 bytes) 0x7F 0x7F 0x00 50D2 0x00 50D3 to 0x00 50DF 0x00 50E0 0x00 50E1 0x00 50E2 0x00 50E3 to 0x00 50EF 0x00 50F0 0x00 50F1 0x00 50F2 0x00 50F3 0x00 50F4 to 0x00 50FF BEEP AWU IWDG IWDG_KR IWDG_PR IWDG_RLR IWDG key register IWDG prescaler register IWDG reload register Reserved area (13 bytes) 0x00 0xFF AWU_CSR1 AWU_APR AWU_TBR BEEP_CSR AWU control/status register 1 AWU asynchronous prescaler buffer register AWU timebase selection register BEEP control/status register Reserved area (12 bytes) 0x00 0x3F 0x00 0x1F Doc ID 14733 Rev 9 37/103 Memory and register map Table 9. General hardware register map (continued) Block Register label SPI_CR1 SPI_CR2 SPI_ICR SPI_SR SPI 00 5204h 00 5205h 00 5206h 00 5207h 00 5208h to 00 520Fh 00 5210h 00 5211h 00 5212h 00 5213h 00 5214h 00 5215h 00 5216h 00 5217h 00 5218h 00 5219h 00 521Ah 00 521Bh 00 521Ch 00 521Dh 00 521Eh 00 521Fh to 00 522Fh I 2C STM8S207xx, STM8S208xx Address 00 5200h 00 5201h 00 5202h 00 5203h Register name SPI control register 1 SPI control register 2 SPI interrupt control register SPI status register SPI data register SPI CRC polynomial register SPI Rx CRC register SPI Tx CRC register Reserved area (8 bytes) Reset status 0x00 0x00 0x00 0x02 0x00 0x07 0xFF 0xFF SPI_DR SPI_CRCPR SPI_RXCRCR SPI_TXCRCR I2C_CR1 I2C_CR2 I2C_FREQR I2C_OARL I2C_OARH I 2C I2C control register 1 I 2C control register 2 0x00 0x00 0x00 0x00 0x00 I2C frequency register own address register low own address register high Reserved I2C I2C_DR I2C_SR1 I2C_SR2 I2C_SR3 I2C_ITR I2C_CCRL I2C_CCRH I2C_TRISER I2C_PECR I2C data register I 2C I I 2C 2C 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x02 0x00 status register 1 status register 2 status register 3 I2C interrupt control register I C clock control register low I 2C 2 clock control register high I2C TRISE register I2C packet error checking register Reserved area (17 bytes) 38/103 Doc ID 14733 Rev 9 STM8S207xx, STM8S208xx Table 9. General hardware register map (continued) Block Register label UART1_SR UART1_DR UART1_BRR1 UART1_BRR2 UART1_CR1 UART1 UART1_CR2 UART1_CR3 UART1_CR4 UART1_CR5 UART1_GTR UART1_PSCR Memory and register map Address 0x00 5230 0x00 5231 0x00 5232 0x00 5233 0x00 5234 0x00 5235 0x00 5236 0x00 5237 0x00 5238 0x00 5239 0x00 523A 0x00 523B to 0x00 523F 0x00 5240 0x00 5241 0x00 5242 0x00 5243 0x00 5244 Register name UART1 status register UART1 data register UART1 baud rate register 1 UART1 baud rate register 2 UART1 control register 1 UART1 control register 2 UART1 control register 3 UART1 control register 4 UART1 control register 5 UART1 guard time register UART1 prescaler register Reserved area (5 bytes) Reset status 0xC0 xx 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 UART3_SR UART3_DR UART3_BRR1 UART3_BRR2 UART3_CR1 UART3 UART3_CR2 UART3_CR3 UART3_CR4 UART3 status register UART3 data register UART3 baud rate register 1 UART3 baud rate register 2 UART3 control register 1 UART3 control register 2 UART3 control register 3 UART3 control register 4 Reserved C0h xx 0x00 0x00 0x00 0x00 0x00 0x00 0x00 5245 0x00 5246 005247 0x00 5248 0x00 5249 0x00 524A to 0x00 524F UART3_CR6 UART3 control register 6 Reserved area (6 bytes) 0x00 Doc ID 14733 Rev 9 39/103 Memory and register map Table 9. General hardware register map (continued) Block Register label TIM1_CR1 TIM1_CR2 TIM1_SMCR TIM1_ETR TIM1_IER TIM1_SR1 TIM1_SR2 TIM1_EGR TIM1_CCMR1 TIM1_CCMR2 TIM1_CCMR3 TIM1_CCMR4 TIM1_CCER1 TIM1_CCER2 TIM1_CNTRH TIM1_CNTRL TIM1 0x00 5260 0x00 5261 0x00 5262 0x00 5263 0x00 5264 0x00 5265 0x00 5266 0x00 5267 0x00 5268 0x00 5269 0x00 526A 0x00 526B 0x00 526C 0x00 526D 0x00 526E 0x00 526F 0x00 5270 to 0x00 52FF TIM1_PSCRH TIM1_PSCRL TIM1_ARRH TIM1_ARRL TIM1_RCR TIM1_CCR1H TIM1_CCR1L TIM1_CCR2H TIM1_CCR2L TIM1_CCR3H TIM1_CCR3L TIM1_CCR4H TIM1_CCR4L TIM1_BKR TIM1_DTR TIM1_OISR STM8S207xx, STM8S208xx Address 0x00 5250 0x00 5251 0x00 5252 0x00 5253 0x00 5254 0x00 5255 0x00 5256 0x00 5257 0x00 5258 0x00 5259 0x00 525A 0x00 525B 0x00 525C 0x00 525D 0x00 525E 0x00 525F Register name TIM1 control register 1 TIM1 control register 2 TIM1 slave mode control register TIM1 external trigger register TIM1 Interrupt enable register TIM1 status register 1 TIM1 status register 2 TIM1 event generation register TIM1 capture/compare mode register 1 TIM1 capture/compare mode register 2 TIM1 capture/compare mode register 3 TIM1 capture/compare mode register 4 TIM1 capture/compare enable register 1 TIM1 capture/compare enable register 2 TIM1 counter high TIM1 counter low TIM1 prescaler register high TIM1 prescaler register low TIM1 auto-reload register high TIM1 auto-reload register low TIM1 repetition counter register TIM1 capture/compare register 1 high TIM1 capture/compare register 1 low TIM1 capture/compare register 2 high TIM1 capture/compare register 2 low TIM1 capture/compare register 3 high TIM1 capture/compare register 3 low TIM1 capture/compare register 4 high TIM1 capture/compare register 4 low TIM1 break register TIM1 dead-time register TIM1 output idle state register Reserved area (147 bytes) Reset status 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xFF 0xFF 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 40/103 Doc ID 14733 Rev 9 STM8S207xx, STM8S208xx Table 9. General hardware register map (continued) Block Register label TIM2_CR1 TIM2_IER TIM2_SR1 TIM2_SR2 TIM2_EGR TIM2_CCMR1 TIM2_CCMR2 TIM2_CCMR3 TIM2_CCER1 TIM2_CCER2 TIM2 TIM2_CNTRH TIM2_CNTRL TIM2_PSCR TIM2_ARRH TIM2_ARRL TIM2_CCR1H TIM2_CCR1L TIM2_CCR2H TIM2_CCR2L TIM2_CCR3H TIM2_CCR3L Memory and register map Address 0x00 5300 0x00 5301 0x00 5302 0x00 5303 0x00 5304 0x00 5305 0x00 5306 0x00 5307 0x00 5308 0x00 5309 0x00 530A 0x00 530B 00 530C0x 0x00 530D 0x00 530E 0x00 530F 0x00 5310 0x00 5311 0x00 5312 0x00 5313 0x00 5314 0x00 5315 to 0x00 531F Register name TIM2 control register 1 TIM2 interrupt enable register TIM2 status register 1 TIM2 status register 2 TIM2 event generation register TIM2 capture/compare mode register 1 TIM2 capture/compare mode register 2 TIM2 capture/compare mode register 3 TIM2 capture/compare enable register 1 TIM2 capture/compare enable register 2 TIM2 counter high TIM2 counter low TIM2 prescaler register TIM2 auto-reload register high TIM2 auto-reload register low TIM2 capture/compare register 1 high TIM2 capture/compare register 1 low TIM2 capture/compare reg. 2 high TIM2 capture/compare register 2 low TIM2 capture/compare register 3 high TIM2 capture/compare register 3 low Reserved area (11 bytes) Reset status 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xFF 0xFF 0x00 0x00 0x00 0x00 0x00 0x00 Doc ID 14733 Rev 9 41/103 Memory and register map Table 9. General hardware register map (continued) Block Register label TIM3_CR1 TIM3_IER TIM3_SR1 TIM3_SR2 TIM3_EGR TIM3_CCMR1 TIM3_CCMR2 TIM3_CCER1 TIM3 TIM3_CNTRH TIM3_CNTRL TIM3_PSCR TIM3_ARRH TIM3_ARRL TIM3_CCR1H TIM3_CCR1L TIM3_CCR2H TIM3_CCR2L STM8S207xx, STM8S208xx Address 0x00 5320 0x00 5321 0x00 5322 0x00 5323 0x00 5324 0x00 5325 0x00 5326 0x00 5327 0x00 5328 0x00 5329 0x00 532A 0x00 532B 0x00 532C 0x00 532D 0x00 532E 0x00 532F 0x00 5330 0x00 5331 to 0x00 533F 0x00 5340 0x00 5341 0x00 5342 0x00 5343 0x00 5344 0x00 5345 0x00 5346 0x00 5347 to 0x00 53FF Register name TIM3 control register 1 TIM3 interrupt enable register TIM3 status register 1 TIM3 status register 2 TIM3 event generation register TIM3 capture/compare mode register 1 TIM3 capture/compare mode register 2 TIM3 capture/compare enable register 1 TIM3 counter high TIM3 counter low TIM3 prescaler register TIM3 auto-reload register high TIM3 auto-reload register low TIM3 capture/compare register 1 high TIM3 capture/compare register 1 low TIM3 capture/compare register 2 high TIM3 capture/compare register 2 low Reserved area (15 bytes) Reset status 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xFF 0xFF 0x00 0x00 0x00 0x00 TIM4_CR1 TIM4_IER TIM4_SR TIM4 TIM4_EGR TIM4_CNTR TIM4_PSCR TIM4_ARR TIM4 control register 1 TIM4 interrupt enable register TIM4 status register TIM4 event generation register TIM4 counter TIM4 prescaler register TIM4 auto-reload register Reserved area (185 bytes) 0x00 0x00 0x00 0x00 0x00 0x00 0xFF 42/103 Doc ID 14733 Rev 9 STM8S207xx, STM8S208xx Table 9. General hardware register map (continued) Block Register label ADC _CSR ADC_CR1 ADC_CR2 ADC_CR3 ADC2 0x00 5404 0x00 5405 0x00 5406 0x00 5407 0x00 5408 to 0x00 541F 0x00 5420 0x00 5421 0x00 5422 0x00 5423 0x00 5424 0x00 5425 0x00 5426 0x00 5427 0x00 5428 0x00 5429 0x00 542A 0x00 542B 0x00 542C 0x00 542D 0x00 542E 0x00 542F 0x00 5430 0x00 5431 0x00 5432 0x00 5433 0x00 5434 0x00 5435 0x00 5436 beCAN CAN_MCR CAN_MSR CAN_TSR CAN_TPR CAN_RFR CAN_IER CAN_DGR CAN_FPSR CAN_P0 CAN_P1 CAN_P2 CAN_P3 CAN_P4 CAN_P5 CAN_P6 CAN_P7 CAN_P8 CAN_P9 CAN_PA CAN_PB CAN_PC CAN_PD CAN_PE ADC_DRH ADC_DRL ADC_TDRH ADC_TDRL Memory and register map Address 0x00 5400 0x00 5401 0x00 5402 0x00 5403 Register name ADC control/status register ADC configuration register 1 ADC configuration register 2 ADC configuration register 3 ADC data register high ADC data register low ADC Schmitt trigger disable register high ADC Schmitt trigger disable register low Reserved area (24 bytes) CAN master control register CAN master status register CAN transmit status register CAN transmit priority register CAN receive FIFO register CAN interrupt enable register CAN diagnosis register CAN page selection register CAN paged register 0 CAN paged register 1 CAN paged register 2 CAN paged register 3 CAN paged register 4 CAN paged register 5 CAN paged register 6 CAN paged register 7 CAN paged register 8 CAN paged register 9 CAN paged register A CAN paged register B CAN paged register C CAN paged register D CAN paged register E Reset status 0x00 0x00 0x00 0x00 undefined undefined 0x00 0x00 0x02 0x02 0x00 0x0C 0x00 0x00 0x0C 0x00 Doc ID 14733 Rev 9 43/103 Memory and register map Table 9. General hardware register map (continued) Block beCAN cont’d Register label CAN_PF STM8S207xx, STM8S208xx Address 0x00 5437 0x00 5438 to 0x00 57FF Register name CAN paged register F Reserved area (968 bytes) Reset status Table 10. Address 0x00 7F00 0x00 7F01 0x00 7F02 0x00 7F03 0x00 7F04 0x00 7F05 0x00 7F06 0x00 7F07 0x00 7F08 0x00 7F09 0x00 7F0A CPU/SWIM/debug module/interrupt controller registers Block Register Label A PCE PCH PCL XH CPU(1) XL YH YL SPH SPL CCR Register Name Accumulator Program counter extended Program counter high Program counter low X index register high X index register low Y index register high Y index register low Stack pointer high Stack pointer low Condition code register Reserved area (85 bytes) CPU CFG_GCR ITC_SPR1 ITC_SPR2 ITC_SPR3 ITC_SPR4 ITC ITC_SPR5 ITC_SPR6 ITC_SPR7 ITC_SPR8 Global configuration register Interrupt software priority register 1 Interrupt software priority register 2 Interrupt software priority register 3 Interrupt software priority register 4 Interrupt software priority register 5 Interrupt software priority register 6 Interrupt software priority register 7 Interrupt software priority register 8 Reserved area (2 bytes) SWIM SWIM_CSR SWIM control status register Reserved area (15 bytes) 0x00 0x00 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF Reset Status 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x17(2) 0xFF 0x28 0x00 7F0B to 0x00 7F5F 0x00 7F60 0x00 7F70 0x00 7F71 0x00 7F72 0x00 7F73 0x00 7F74 0x00 7F75 0x00 7F76 0x00 7F77 0x00 7F78 to 0x00 7F79 0x00 7F80 0x00 7F81 to 0x00 7F8F 44/103 Doc ID 14733 Rev 9 STM8S207xx, STM8S208xx Table 10. Address 0x00 7F90 0x00 7F91 0x00 7F92 0x00 7F93 0x00 7F94 0x00 7F95 0x00 7F96 0x00 7F97 0x00 7F98 0x00 7F99 0x00 7F9A 0x00 7F9B to 0x00 7F9F 1. Accessible by debug module only 2. Product dependent value, see Figure 8: Memory map. Memory and register map CPU/SWIM/debug module/interrupt controller registers (continued) Block Register Label DM_BK1RE DM_BK1RH DM_BK1RL DM_BK2RE DM_BK2RH DM DM_BK2RL DM_CR1 DM_CR2 DM_CSR1 DM_CSR2 DM_ENFCTR Register Name DM breakpoint 1 register extended byte DM breakpoint 1 register high byte DM breakpoint 1 register low byte DM breakpoint 2 register extended byte DM breakpoint 2 register high byte DM breakpoint 2 register low byte DM debug module control register 1 DM debug module control register 2 DM debug module control/status register 1 DM debug module control/status register 2 DM enable function register Reserved area (5 bytes) Reset Status 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0x00 0x00 0x10 0x00 0xFF Doc ID 14733 Rev 9 45/103 Interrupt vector mapping STM8S207xx, STM8S208xx 7 Table 11. IRQ no. Interrupt vector mapping Interrupt mapping Description Reset Software interrupt External top level interrupt Auto wake up from halt Clock controller Port A external interrupts Port B external interrupts Port C external interrupts Port D external interrupts Port E external interrupts beCAN RX interrupt beCAN TX/ER/SC interrupt End of transfer TIM1 update/overflow/underflow/ trigger/break TIM1 capture/compare TIM2 update /overflow TIM2 capture/compare Update/overflow Capture/compare Tx complete Receive register DATA FULL I2C interrupt Tx complete Receive register DATA FULL ADC2 end of conversion TIM4 update/overflow EOP/WR_PG_DIS Reserved Wakeup from halt mode Yes Yes (1) Source block RESET TRAP Wakeup from active-halt mode Yes Yes Yes(1) Yes Yes Yes Yes Yes Yes Yes - Vector address 0x00 8000 0x00 8004 0x00 8008 0x00 800C 0x00 8010 0x00 8014 0x00 8018 0x00 801C 0x00 8020 0x00 8024 0x00 8028 0x00 802C 0x00 8030 0x00 8034 0x00 8038 0x00 803C 0x00 8040 0x00 8044 0x00 8048 0x00 804C 0x00 8050 0x00 8054 0x00 8058 0x00 805C 0x00 8060 0x00 8064 0x00 8068 0x00 806C to 0x00 807C 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 TLI AWU CLK EXTI0 EXTI1 EXTI2 EXTI3 EXTI4 beCAN beCAN SPI TIM1 TIM1 TIM2 TIM2 TIM3 TIM3 UART1 UART1 I2C UART3 UART3 ADC2 TIM4 Flash Yes Yes Yes Yes Yes Yes Yes - 1. Except PA1 46/103 Doc ID 14733 Rev 9 STM8S207xx, STM8S208xx Option bytes 8 Option bytes Option bytes contain configurations for device hardware features as well as the memory protection of the device. They are stored in a dedicated block of the memory. Except for the ROP (read-out protection) byte, each option byte has to be stored twice, in a regular form (OPTx) and a complemented one (NOPTx) for redundancy. Option bytes can be modified in ICP mode (via SWIM) by accessing the EEPROM address shown in Table 12: Option bytes below. Option bytes can also be modified ‘on the fly’ by the application in IAP mode, except the ROP option that can only be modified in ICP mode (via SWIM). Refer to the STM8S Flash programming manual (PM0051) and STM8 SWIM communication protocol and debug module user manual (UM0470) for information on SWIM programming procedures. Table 12. Addr. Option bytes Option name Option byte no. Option bits 7 6 5 4 3 2 1 0 Factory default setting Read-out 4800h protection (ROP) 4801h 4802h 4803h User boot code(UBC) Alternate function 4804h remapping (AFR) 4805h Watchdog option 4806h NOPT3 Reserved OPT3 Reserved LSI _EN NLSI _EN EXT CLK NEXT CLK HSECNT[7:0] NHSECNT[7:0] Reserved Reserved Reserved Reserved BL[7:0] NBL[7:0] Wait state Nwait state IWDG _HW NIWDG _HW CKAWU SEL NCKAWUS EL WWDG _HW NWWDG _HW PRS C1 NPR SC1 WWDG _HALT NWWDG _HALT PRS C0 NPR SC0 00h NOPT2 NAFR7 NAFR6 NAFR5 NAFR4 NAFR3 NAFR2 NAFR1 NAFR0 FFh OPT1 NOPT1 OPT2 AFR7 AFR6 AFR5 AFR4 UBC[7:0] NUBC[7:0] AFR3 AFR2 AFR1 AFR0 00h FFh 00h OPT0 ROP[7:0] 00h FFh 4807h Clock option 4808h 4809h 480Ah 480Bh Reserved 480Ch 480Dh 480Eh 487Eh Bootloader 487Fh Flash wait states OPT4 Reserved 00h NOPT4 OPT5 NOPT5 OPT6 NOPT6 OPT7 NOPT7 OPTBL NOPTBL Reserved FFh 00h FFh 00h FFh 00h FFh 00h FFh HSE clock startup Doc ID 14733 Rev 9 47/103 Option bytes Table 13. Option byte description STM8S207xx, STM8S208xx Option byte no. Description ROP[7:0] Memory readout protection (ROP) 0xAA: Enable readout protection (write access via SWIM protocol) Note: Refer to the family reference manual (RM0016) section on Flash/EEPROM memory readout protection for details. UBC[7:0] User boot code area 0x00: no UBC, no write-protection 0x01: Pages 0 to 1 defined as UBC, memory write-protected 0x02: Pages 0 to 3 defined as UBC, memory write-protected 0x03: Pages 0 to 4 defined as UBC, memory write-protected ... 0xFE: Pages 0 to 255 defined as UBC, memory write-protected 0xFF: Reserved Note: Refer to the family reference manual (RM0016) section on Flash/EEPROM write protection for more details. AFR7Alternate function remapping option 7 0: Port D4 alternate function = TIM2_CH1 1: Port D4 alternate function = BEEP AFR6 Alternate function remapping option 6 0: Port B5 alternate function = AIN5, port B4 alternate function = AIN4 1: Port B5 alternate function = I2C_SDA, port B4 alternate function = I2C_SCL AFR5 Alternate function remapping option 5 0: Port B3 alternate function = AIN3, port B2 alternate function = AIN2, port B1 alternate function = AIN1, port B0 alternate function = AIN0 1: Port B3 alternate function = TIM1_ETR, port B2 alternate function = TIM1_CH3N, port B1 alternate function = TIM1_CH2N, port B0 alternate function = TIM1_CH1N AFR4 Alternate function remapping option 4 0: Port D7 alternate function = TLI 1: Port D7 alternate function = TIM1_CH4 AFR3 Alternate function remapping option 3 0: Port D0 alternate function = TIM3_CH2 1: Port D0 alternate function = TIM1_BKIN AFR2 Alternate function remapping option 2 0: Port D0 alternate function = TIM3_CH2 1: Port D0 alternate function = CLK_CCO Note: AFR2 option has priority over AFR3 if both are activated AFR1 Alternate function remapping option 1 0: Port A3 alternate function = TIM2_CH3, port D2 alternate function TIM3_CH1 1: Port A3 alternate function = TIM3_CH1, port D2 alternate function TIM2_CH3 AFR0 Alternate function remapping option 0 0: Port D3 alternate function = TIM2_CH2 1: Port D3 alternate function = ADC_ETR OPT0 OPT1 OPT2 48/103 Doc ID 14733 Rev 9 STM8S207xx, STM8S208xx Table 13. Option byte description (continued) Description LSI_EN: Low speed internal clock enable 0: LSI clock is not available as CPU clock source 1: LSI clock is available as CPU clock source IWDG_HW: Independent watchdog 0: IWDG Independent watchdog activated by software 1: IWDG Independent watchdog activated by hardware OPT3 WWDG_HW: Window watchdog activation 0: WWDG window watchdog activated by software 1: WWDG window watchdog activated by hardware WWDG_HALT: Window watchdog reset on halt 0: No reset generated on halt if WWDG active 1: Reset generated on halt if WWDG active EXTCLK: External clock selection 0: External crystal connected to OSCIN/OSCOUT 1: External clock signal on OSCIN Option bytes Option byte no. OPT4 CKAWUSEL: Auto wakeup unit/clock 0: LSI clock source selected for AWU 1: HSE clock with prescaler selected as clock source for for AWU PRSC[1:0] AWU clock prescaler 00: 24 MHz to 128 kHz prescaler 01: 16 MHz to 128 kHz prescaler 10: 8 MHz to 128 kHz prescaler 11: 4 MHz to 128 kHz prescaler HSECNT[7:0]: HSE crystal oscillator stabilization time This configures the stabilisation time. 0x00: 2048 HSE cycles 0xB4: 128 HSE cycles 0xD2: 8 HSE cycles 0xE1: 0.5 HSE cycles Reserved WAITSTATE Wait state configuration This option configures the number of wait states inserted when reading from the Flash/data EEPROM memory. 1 wait state is required if fCPU > 16 MHz. 0: No wait state 1: 1 wait state OPT5 OPT6 OPT7 Doc ID 14733 Rev 9 49/103 Option bytes Table 13. Option byte description (continued) STM8S207xx, STM8S208xx Option byte no. Description BL[7:0] Bootloader option byte For STM8S products, this option is checked by the boot ROM code after reset. Depending on the content of addresses 0x487E, 0x487F, and 0x8000 (reset vector), the CPU jumps to the bootloader or to the reset vector. Refer to the UM0560 (STM8L/S bootloader manual) for more details. For STM8L products, the bootloader option bytes are on addresses 0xXXXX and 0xXXXX+1 (2 bytes). These option bytes control whether the bootloader is active or not. For more details, refer to the UM0560 (STM8L/S bootloader manual) for more details. OPTBL 50/103 Doc ID 14733 Rev 9 STM8S207xx, STM8S208xx Unique ID 9 Unique ID The devices feature a 96-bit unique device identifier which provides a reference number that is unique for any device and in any context. The 96 bits of the identifier can never be altered by the user. The unique device identifier can be read in single bytes and may then be concatenated using a custom algorithm. The unique device identifier is ideally suited: ● ● For use as serial numbers For use as security keys to increase the code security in the program memory while using and combining this unique ID with software crytograhic primitives and protocols before programming the internal memory. To activate secure boot processes Unique ID registers (96 bits) Content description X co-ordinate on the wafer Y co-ordinate on the wafer Wafer number Unique ID bits 7 6 5 4 3 U_ID[7:0] U_ID[15:8] U_ID[23:16] U_ID[31:24] U_ID[39:32] U_ID[47:40] U_ID[55:48] U_ID[63:56] Lot number U_ID[71:64] U_ID[79:72] U_ID[87:80] U_ID[95:88] 2 1 0 ● Table 14. Address 0x48CD 0x48CE 0x48CF 0x48D0 0x48D1 0x48D2 0x48D3 0x48D4 0x48D5 0x48D6 0x48D7 0x48D8 Doc ID 14733 Rev 9 51/103 Electrical characteristics STM8S207xx, STM8S208xx 10 10.1 Electrical characteristics Parameter conditions Unless otherwise specified, all voltages are referred to VSS. 10.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100 % of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean ± 3 Σ). 10.1.2 Typical values Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 5 V. They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean ± 2 Σ). 10.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 10.1.4 Typical current consumption For typical current consumption measurements, VDD, VDDIO and VDDA are connected together in the configuration shown in Figure 9. Figure 9. Supply current measurement conditions 5 V or 3.3 V VDD VDDA VDDIO VSS VSSA VSSIO A 52/103 Doc ID 14733 Rev 9 STM8S207xx, STM8S208xx Electrical characteristics 10.1.5 10.1.6 Pin loading conditions Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 10. Figure 10. Pin loading conditions STM8 pin 50 pF 10.1.7 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 11. Figure 11. Pin input voltage STM8 pin VIN Doc ID 14733 Rev 9 53/103 Electrical characteristics STM8S207xx, STM8S208xx 10.2 Absolute maximum ratings Stresses above those listed as ‘absolute maximum ratings’ may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 15. Symbol VDDx - VSS VIN Voltage characteristics Ratings Supply voltage (including VDDA and VDDIO)(1) Input voltage on true open drain pins (PE1, PE2) Input voltage on any other pin(2) (2) Min -0.3 VSS - 0.3 VSS - 0.3 Max 6.5 6.5 VDD + 0.3 50 Unit V |VDDx - VDD| Variations between different power pins |VSSx - VSS| Variations between all the different ground pins VESD Electrostatic discharge voltage mV 50 see Absolute maximum ratings (electrical sensitivity) on page 87 1. All power (VDD, VDDIO, VDDA) and ground (VSS, VSSIO, VSSA) pins must always be connected to the external power supply 2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN>VDD while a negative injection is induced by VINVDD while a negative injection is induced by VIN> gmcrit 66/103 Doc ID 14733 Rev 9 STM8S207xx, STM8S208xx Electrical characteristics 10.3.4 Internal clock sources and timing characteristics Subject to general operating conditions for VDD and TA. fHSE High speed internal RC oscillator (HSI) Table 33. Symbol fHSI HSI oscillator characteristics Parameter Frequency Trimmed by the CLK_HSITRIMR register Accuracy of HSI oscillator for given VDD and TA conditions VDD = 5 V, TA = 25 °C Conditions Min Typ 16 Max Unit MHz -1(1) 1(1) -1.5 -2.2 -3(2) 1.5 2.2 3(2) 1(1) 170 250(2) µs µA % ACCHSI Accuracy of HSI oscillator 2.95 V ≤ VDD ≤ 5.5 V, (factory calibrated) -40 °C ≤ TA ≤ 125 °C tsu(HSI) IDD(HSI) HSI oscillator wakeup time including calibration HSI oscillator power consumption VDD = 5 V, 25 °C ≤ TA ≤ 85 °C 1. Guaranteeed by design, not tested in production. 2. Data based on characterization results, not tested in production Figure 18. Typical HSI frequency variation vs VDD at 4 temperatures -40˚C 3% 2% 1% 0% -1% -2% -3% 2.5 3 3.5 4 4.5 5 5.5 6 25˚C 85˚C 125˚C % accuracy VDD (V) ai15067 Doc ID 14733 Rev 9 67/103 Electrical characteristics STM8S207xx, STM8S208xx Low speed internal RC oscillator (LSI) Subject to general operating conditions for VDD and TA. Table 34. Symbol fLSI tsu(LSI) IDD(LSI) Frequency LSI oscillator wakeup time LSI oscillator power consumption 5 LSI oscillator characteristics Parameter Conditions Min 110 Typ 128 Max 146 7(1) Unit kHz µs µA 1. Guaranteeed by design, not tested in production. Figure 19. Typical LSI frequency variation vs VDD @ 25 °C 3% 2% 1% 0% -1% -2% -3% 2.5 3 3.5 4 VDD [V] 4.5 5 5.5 6 % accuracy ai15070 68/103 Doc ID 14733 Rev 9 STM8S207xx, STM8S208xx Electrical characteristics 10.3.5 Memory characteristics RAM and hardware registers Table 35. Symbol VRM RAM and hardware registers Parameter Data retention mode(1) Conditions Halt mode (or reset) Min VIT-max(2) Unit V 1. Minimum supply voltage without losing data stored in RAM (in halt mode or under reset) or in hardware registers (only in halt mode). Guaranteed by design, not tested in production. 2. Refer to Table 19 on page 57 for the value of VIT-max. Flash program memory/data EEPROM memory General conditions: TA = -40 to 125 °C. Table 36. Symbol VDD Flash program memory/data EEPROM memory Parameter Conditions fCPU ≤ 24 MHz Min(1) Typ 2.95 Max 5.5 Unit V Operating voltage (all modes, execution/write/erase) Standard programming time (including erase) for byte/word/block (1 byte/4 bytes/128 bytes) Fast programming time for 1 block (128 bytes) 6 6.6 ms tprog 3 3 TA = 85 °C TA = 125 ° C TRET = 55° C 10 k 3.3 3.3 ms ms terase NRW Erase time for 1 block (128 bytes) Erase/write (program memory) cycles(2) cycles 300 k 20 1M Erase/write cycles (data memory)(2) Data retention (program memory) after 10 k erase/write cycles at TA = 85 °C tRET Data retention (data memory) after 10 k erase/write cycles at TA = 85 °C Data retention (data memory) after 300k erase/write cycles at TA = 125 °C IDD Supply current (Flash programming or erasing for 1 to 128 bytes) TRET = 55° C 20 years TRET = 85° C 1 2 mA 1. Data based on characterization results, not tested in production. 2. The physical granularity of the memory is 4 bytes, so cycling is performed on 4 bytes even when a write/erase operation addresses a single byte. Doc ID 14733 Rev 9 69/103 Electrical characteristics STM8S207xx, STM8S208xx 10.3.6 I/O port pin characteristics General characteristics Subject to general operating conditions for VDD and TA unless otherwise specified. All unused pins must be kept at a fixed voltage: using the output mode of the I/O for example or an external pull-up or pull-down resistor. Table 37. Symbol VIL VIH Vhys Rpu I/O static characteristics Parameter Input low level voltage Input high level voltage Hysteresis(1) Pull-up resistor VDD = 5 V, VIN = VSS Fast I/Os Load = 50 pF Standard and high sink I/Os Load = 50 pF VSS ≤ VIN ≤ VDD VSS ≤ VIN ≤ VDD Injection current ±4 mA 30 VDD = 5 V Conditions Min -0.3 0.7 x VDD 700 45 60 20 (2) 125 (2) Typ Max 0.3 x VDD VDD + 0.3 V Unit V V mV kΩ ns ns tR, tF Rise and fall time (10% - 90%) Ilkg Input leakage current, analog and digital Analog input leakage current Leakage current in adjacent I/O(2) ±1 µA Ilkg ana Ilkg(inj) ±250 (2) ±1(2) nA µA 1. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested in production. 2. Data based on characterization results, not tested in production. 70/103 Doc ID 14733 Rev 9 STM8S207xx, STM8S208xx Figure 20. Typical VIL and VIH vs VDD @ 4 temperatures Electrical characteristics -40˚C 6 5 4 3 2 1 0 2.5 3 3.5 4 4.5 5 5.5 6 25˚C 85˚C 125˚C VIL/VIH [V] VDD [V] Figure 21. Typical pull-up resistance vs VDD @ 4 temperatures -40˚C 60 25˚C 85˚C 125˚C Pull-up resistance [ΩW] 55 50 45 40 35 30 2.5 3 3.5 4 VDD [V] 4.5 5 5.5 6 Figure 22. Typical pull-up current vs VDD @ 4 temperatures 140 120 Pull-Up current [µA] 100 80 60 40 20 0 0 1 2 3 VDD [V] 4 5 6 -40˚C 25˚C 85˚C 125˚C ai15068 1. The pull-up is a pure resistor (slope goes through 0). Doc ID 14733 Rev 9 71/103 Electrical characteristics Table 38. Symbol VOL STM8S207xx, STM8S208xx Output driving current (standard ports) Parameter Output low level with 8 pins sunk Output low level with 4 pins sunk Output high level with 8 pins sourced Conditions IIO = 10 mA, VDD = 5 V IIO = 4 mA, VDD = 3.3 V IIO = 10 mA, VDD = 5 V IIO = 4 mA, VDD = 3.3 V 2.8 2.1(1) V Min Max 2 1(1) V Unit VOH Output high level with 4 pins sourced 1. Data based on characterization results, not tested in production Table 39. Symbol Output driving current (true open drain ports) Parameter Conditions IIO = 10 mA, VDD = 5 V Max 1 1.5(1) 2(1) V Unit VOL Output low level with 2 pins sunk IIO = 10 mA, VDD = 3.3 V IIO = 20 mA, VDD = 5 V 1. Data based on characterization results, not tested in production Table 40. Symbol Output driving current (high sink ports) Parameter Output low level with 8 pins sunk Conditions IIO = 10 mA,VDD = 5 V IIO = 10 mA,VDD = 3.3 V IIO = 20 mA,VDD = 5 V IIO = 10 mA, VDD = 5 V IIO = 10 mA, VDD = 3.3 V IIO = 20 mA, VDD = 5 V 4.0 2.1(1) 3.3(1) Min Max 0.8 1(1) 1.5(1) V Unit VOL Output low level with 4 pins sunk Output low level with 4 pins sunk Output high level with 8 pins sourced VOH Output high level with 4 pins sourced Output high level with 4 pins sourced 1. Data based on characterization results, not tested in production 72/103 Doc ID 14733 Rev 9 STM8S207xx, STM8S208xx Electrical characteristics Typical output level curves Figure 24 to Figure 31 show typical output level curves measured with output on a single pin. Figure 23. Typ. VOL @ VDD = 5 V (standard ports) 1.5 1.25 1 -40˚C 25˚C 85˚C 125˚C VOL [V] 0.75 0.5 0.25 0 0 2 4 6 8 10 12 IOL [mA] Figure 24. Typ. VOL @ VDD = 3.3 V (standard ports) 1.5 1.25 1 -40˚C 25˚C 85˚C 125˚C VOL [V] 0.75 0.5 0.25 0 0 1 2 3 4 5 6 7 VOL [V] IOL [mA] Figure 25. Typ. VOL @ VDD = 5 V (true open drain ports) 2 1.75 1.5 -40˚C 25˚C 85˚C 125˚C VOL [V] 1.25 1 0.75 0.5 0.25 0 0 5 10 15 20 25 IOL [mA] Doc ID 14733 Rev 9 73/103 Electrical characteristics Figure 26. Typ. VOL @ VDD = 3.3 V (true open drain ports) 2 1.75 1.5 STM8S207xx, STM8S208xx -40˚C 25˚C 85˚C 125˚C IOL [mA] 1.25 1 0.75 0.5 0.25 0 0 2 4 6 8 10 12 14 VOL [V] Figure 27. Typ. VOL @ VDD = 5 V (high sink ports) 1.5 1.25 1 -40˚C 25˚C 85˚C 125˚C VOL [V] 0.75 0.5 0.25 0 0 5 10 15 20 25 IOL [mA] Figure 28. Typ. VOL @ VDD = 3.3 V (high sink ports) 1.5 1.25 1 -40˚C 25˚C 85˚C 125˚C VOL [V] 0.75 0.5 0.25 0 0 2 4 6 8 10 12 14 IOL [mA] 74/103 Doc ID 14733 Rev 9 STM8S207xx, STM8S208xx Figure 29. Typ. VDD - VOH @ VDD = 5 V (standard ports) 2 1.75 1.5 Electrical characteristics -40˚C 25˚C 85˚C 125˚C VDD - VOH [V] 1.25 1 0.75 0.5 0.25 0 0 2 4 6 8 10 12 IOL [mA] Figure 30. Typ. VDD - VOH @ VDD = 3.3 V (standard ports) 2 1.75 1.5 -40˚C 25˚C 85˚C 125˚C VDD - VOH [V] 1.25 1 0.75 0.5 0.25 0 0 1 2 3 4 5 6 7 IOL [mA] Figure 31. Typ. VDD - VOH @ VDD = 5 V (high sink ports) 2 1.75 1.5 -40˚C 25˚C 85˚C 125˚C VDD - VOH [V] 1.25 1 0.75 0.5 0.25 0 0 5 10 15 20 25 IOL [mA] Doc ID 14733 Rev 9 75/103 Electrical characteristics Figure 32. Typ. VDD - VOH @ VDD = 3.3 V (high sink ports) 2 1.75 1.5 STM8S207xx, STM8S208xx -40˚C 25˚C 85˚C 125˚C VDD - VOH [V] 1.25 1 0.75 0.5 0.25 0 0 2 4 6 8 10 12 14 IOL [mA] 10.3.7 Reset pin characteristics Subject to general operating conditions for VDD and TA unless otherwise specified. Table 41. Symbol VIL(NRST) VIH(NRST) VOL(NRST) RPU(NRST) tIFP(NRST) tINFP(NRST) tOP(NRST) NRST pin characteristics Parameter NRST Input low level voltage (1) NRST Input high level voltage (1) (1) Conditions Min -0.3 V 0.7 x VDD Typ 1) Max 0.3 x VDD VDD + 0.3 0.5 Unit V NRST Output low level voltage NRST Pull-up resistor (2) IOL= 2 mA 30 40 60 75 kΩ ns ns µs NRST Input filtered pulse (3) NRST Input not filtered NRST output pulse (1) pulse (3) 500 15 1. Data based on characterization results, not tested in production. 2. The RPU pull-up equivalent resistor is based on a resistive transistor 3. Data guaranteed by design, not tested in production. Figure 33. Typical NRST VIL and VIH vs VDD @ 4 temperatures -40˚C 6 5 4 25˚C 85˚C 125˚C VIL/VIH [V] 3 2 1 0 2.5 3 3.5 4 4.5 5 5.5 6 VDD [V] 76/103 Doc ID 14733 Rev 9 STM8S207xx, STM8S208xx Electrical characteristics Figure 34. Typical NRST pull-up resistance vs VDD @ 4 temperatures -40˚C 60 25˚C 85˚C 125˚C NRESET pull-up resistance [ΩW] 55 50 45 40 35 30 2.5 3 3.5 4 4.5 5 5.5 6 VDD [V] Figure 35. Typical NRST pull-up current Ipu vs VDD @ 4 temperatures 140 120 NRESET Pull-Up current [µA] 100 80 60 40 20 0 0 1 2 3 VDD [V] 4 5 6 -40˚C 25˚C 85˚C 125˚C ai15069 The reset network shown in Figure 36 protects the device against parasitic resets. The user must ensure that the level on the NRST pin can go below the VIL max. level specified in Table 37. Otherwise the reset is not taken into account internally. Figure 36. Recommended reset pin protection VDD STM8 RPU External reset circuit NRST 0.01µF Filter Internal reset (optional) Doc ID 14733 Rev 9 77/103 Electrical characteristics STM8S207xx, STM8S208xx 10.3.8 SPI serial peripheral interface Unless otherwise specified, the parameters given in Table 42 are derived from tests performed under ambient temperature, fMASTER frequency and VDD supply voltage conditions. tMASTER = 1/fMASTER. Refer to I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO). Table 42. Symbol fSCK 1/tc(SCK) tr(SCK) tf(SCK) tsu(NSS)(1) th(NSS)(1) tw(SCKH) tw(SCKL)(1) tsu(MI) (1) tsu(SI)(1) th(MI) (1) th(SI)(1) ta(SO) (1)(2) (1) SPI characteristics Parameter SPI clock frequency Slave mode SPI clock rise and fall time NSS setup time NSS hold time SCK high and low time Capacitive load: C = 30 pF Slave mode Slave mode Master mode Master mode Data input setup time Slave mode Master mode Data input hold time Slave mode Data output access time Slave mode Slave mode Slave mode (after enable edge) Master mode (after enable edge) Slave mode (after enable edge) Data output hold time Master mode (after enable edge) 12 31 25 75 30 10 3 x tMASTER 5 7 ns 4 x tMASTER 70 tSCK/2 - 15 5 tSCK/2 + 15 0 6 25 Conditions Master mode Min 0 Max 10 MHz Unit tdis(SO)(1)(3) Data output disable time tv(SO) (1) Data output valid time Data output valid time tv(MO)(1) th(SO) (1) th(MO)(1) 1. Values based on design simulation and/or characterization results, and not tested in production. 2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. 3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z. 78/103 Doc ID 14733 Rev 9 STM8S207xx, STM8S208xx Figure 37. SPI timing diagram - slave mode and CPHA = 0 Electrical characteristics NSS input tSU(NSS) SCK Input CPHA= 0 CPOL=0 CPHA= 0 CPOL=1 tc(SCK) th(NSS) tw(SCKH) tw(SCKL) tv(SO) MS B O UT tsu(SI) tr(SCK) tf(SCK) LSB OUT ta(SO) MISO OUT P UT MOSI I NPUT th(SO) BI T6 OUT tdis(SO) M SB IN th(SI) B I T1 IN LSB IN ai14134 Figure 38. SPI timing diagram - slave mode and CPHA = 1(1) NSS input tSU(NSS) SCK Input CPHA=1 CPOL=0 CPHA=1 CPOL=1 tc(SCK) th(NSS) tw(SCKH) tw(SCKL) tr(SCK) tf(SCK) ta(SO) MISO OUT P UT tsu(SI) MOSI I NPUT M SB IN tv(SO) MS B O UT th(SI) th(SO) BI T6 OUT tdis(SO) LSB OUT B I T1 IN LSB IN ai14135 1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD. Doc ID 14733 Rev 9 79/103 Electrical characteristics Figure 39. SPI timing diagram - master mode(1) High NSS input tc(SCK) SCK Input CPHA= 0 CPOL=0 CPHA= 0 CPOL=1 STM8S207xx, STM8S208xx SCK Input CPHA=1 CPOL=0 CPHA=1 CPOL=1 tsu(MI) MISO INP UT MOSI OUTUT tw(SCKH) tw(SCKL) MS BIN th(MI) M SB OUT tv(MO) B I T1 OUT th(MO) ai14136 tr(SCK) tf(SCK) BI T6 IN LSB IN LSB OUT 1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD. 80/103 Doc ID 14733 Rev 9 STM8S207xx, STM8S208xx Electrical characteristics 10.3.9 I2C interface characteristics Table 43. Symbol tw(SCLL) tw(SCLH) tsu(SDA) th(SDA) tr(SDA) tr(SCL) tf(SDA) tf(SCL) th(STA) tsu(STA) tsu(STO) tw(STO:STA) Cb I2C characteristics Standard mode I2C Fast mode I2C(1) Parameter SCL clock low time SCL clock high time SDA setup time SDA data hold time SDA and SCL rise time SDA and SCL fall time START condition hold time Repeated START condition setup time STOP condition setup time STOP to START condition time (bus free) Capacitive load for each bus line I 2C Min(2) 4.7 4.0 250 0(3) Max(2) Min(2) 1.3 Max(2) Unit µs 0.6 100 0(4) 1000 300 4.0 4.7 4.0 4.7 400 speed (400kHz) 900(3) 300 300 ns 0.6 µs 0.6 0.6 1.3 400 µs µs pF 1. fMASTER, must be at least 8 MHz to achieve max fast 2. Data based on standard I2C protocol requirement, not tested in production 3. The maximum hold time of the start condition has only to be met if the interface does not stretch the low time 4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL Doc ID 14733 Rev 9 81/103 Electrical characteristics STM8S207xx, STM8S208xx Figure 40. Typical application with I2C bus and timing diagram(1) VDD VDD STM8S20xxx SDA I²C bus SCL S TART REPEATED S TART tsu(STA) SDA tf(SDA) th(STA) SCL tw(SCKH) S TART tr(SDA) tw(SCKL) tsu(SDA) th(SDA) S TOP tsu(STA:STO) tr(SCK) tf(SCK) tsu(STO) ai15385 1. Measurement points are done at CMOS levels: 0.3 x VDD and 0.7 x VDD 82/103 Doc ID 14733 Rev 9 STM8S207xx, STM8S208xx Electrical characteristics 10.3.10 10-bit ADC characteristics Subject to general operating conditions for VDDA, fMASTER, and TA unless otherwise specified. Table 44. Symbol ADC characteristics Parameter Conditions VDDA = 3 to 5.5 V Min 1 1 3 2.75(1) VSSA VSSA Typ Max 4 MHz VDDA = 4.5 to 5.5 V 6 5.5 VDDA 0.5(1) VDDA VREF+ 3 fADC = 4 MHz fADC = 6 MHz Wakeup time from standby fADC = 4 MHz Total conversion time (including sampling time, 10-bit resolution) 0.75 µs 0.5 7 3.5 2.33 14 µs µs µs 1/fADC V V V V V pF Unit fADC VDDA VREF+ VREF- ADC clock frequency Analog supply Positive reference voltage Negative reference voltage Conversion voltage range(2) VAIN Devices with external VREF+/VREF- pins VREF- CADC tS(2) tSTAB Internal sample and hold capacitor Sampling time tCONV fADC = 6 MHz 1. Data guaranteed by design, not tested in production.. 2. During the sample time the input capacitance CAIN (3 pF max) can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within tS. After the end of the sample time tS, changes of the analog input voltage have no effect on the conversion result. Values for the sample clock tS depend on programming. Doc ID 14733 Rev 9 83/103 Electrical characteristics Table 45. Symbol STM8S207xx, STM8S208xx ADC accuracy with RAIN < 10 kΩ , VDDA = 5 V Parameter Conditions fADC = 2 MHz. Typ 1 1.4 1.6 0.6 1.1 1.2 0.2 0.6 0.8 0.7 0.7 0.8 0.6 0.6 0.6 Max(1) 2.5 3 3.5 2 2.5 2.5 2 2.5 2.5 1.5 1.5 1.5 1.5 1.5 1.5 LSB Unit |ET| Total unadjusted error (2) fADC = 4 MHz. fADC = 6 MHz. fADC = 2 MHz. |EO| Offset error (2) fADC = 4 MHz. fADC = 6 MHz. fADC = 2 MHz. |EG| Gain error (2) fADC = 4 MHz. fADC = 6 MHz. fADC = 2 MHz. error (2) |ED| Differential linearity fADC = 4 MHz. fADC = 6 MHz. fADC = 2 MHz. |EL| Integral linearity error (2) fADC = 4 MHz. fADC = 6 MHz. 1. Data based on characterisation results for LQFP80 device with VREF+/VREF-, not tested in production. 2. ADC accuracy vs. negative injection current: Injecting negative current on any of the analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 10.3.6 does not affect the ADC accuracy. Table 46. Symbol |ET| ADC accuracy with RAIN < 10 kΩ RAIN, VDDA = 3.3 V Parameter Total unadjusted error(2) Conditions fADC = 2 MHz. fADC = 4 MHz. Offset error(2) fADC = 2 MHz. fADC = 4 MHz. Gain error(2) fADC = 2 MHz. fADC = 4 MHz. Differential linearity error(2) fADC = 2 MHz. fADC = 4 MHz. Integral linearity error(2) fADC = 2 MHz. fADC = 4 MHz. Typ 1.1 1.6 0.7 1.3 0.2 0.5 0.7 0.7 0.6 0.6 Max(1) 2 2.5 1.5 2 1.5 LSB 2 1 1 1.5 1.5 Unit |EO| |EG| |ED| |EL| 84/103 Doc ID 14733 Rev 9 STM8S207xx, STM8S208xx Figure 41. ADC accuracy characteristics 1023 1022 1021 1LSB IDEAL EG V –V DDA SSA = ---------------------------------------1024 (2) 7 6 5 4 3 2 1 0 1 VSSA 2 3 4 1 LSBIDEAL 5 6 7 EO EL ED ET (3) (1) Electrical characteristics 1021102210231024 VDDA 1. Example of an actual transfer curve. 2. The ideal transfer curve 3. End point correlation line ET = Total unadjusted error: maximum deviation between the actual and the ideal transfer curves. EO = Offset error: deviation between the first actual transition and the first ideal one. EG = Gain error: deviation between the last ideal transition and the last actual one. ED = Differential linearity error: maximum deviation between actual steps and the ideal one. EL = Integral linearity error: maximum deviation between any actual transition and the end point correlation line. Figure 42. Typical application with ADC VDD VT 0.6V AINx CAIN VT 0.6V 10-bit A/D conversion IL ±1µA CADC STM8 RAIN VAIN Doc ID 14733 Rev 9 85/103 Electrical characteristics STM8S207xx, STM8S208xx 10.3.11 EMC characteristics Susceptibility tests are performed on a sample basis during product characterization. Functional EMS (electromagnetic susceptibility) While executing a simple application (toggling 2 LEDs through I/O ports), the product is stressed by two electromagnetic events until a failure occurs (indicated by the LEDs). ● ESD: Electrostatic discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. This test conforms with the IEC 61000-4-2 standard. FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test conforms with the IEC 61000-4-4 standard. ● A device reset allows normal operations to be resumed. The test results are given in the table below based on the EMS levels and classes defined in application note AN1709. Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations The software flowchart must include the management of runaway conditions such as: ● ● ● Corrupted program counter Unexpected reset Critical data corruption (control registers...) Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be recovered by applying a low state on the NRST pin or the oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). Table 47. Symbol VFESD EMS data Parameter Conditions Level/class 2B VDD = 5 V, TA = 25 °C, Voltage limits to be applied on any I/O pin to fMASTER = 16 MHz, induce a functional disturbance conforming to IEC 61000-4-2 Fast transient voltage burst limits to be VDD = 5 V, TA = 25 °C, applied through 100pF on VDD and VSS pins fMASTER = 16 MHz, to induce a functional disturbance conforming to IEC 61000-4-4 VEFTB 4A 86/103 Doc ID 14733 Rev 9 STM8S207xx, STM8S208xx Electrical characteristics Electromagnetic interference (EMI) Emission tests conform to the SAE IEC 61967-2 standard for test software, board layout and pin loading. Table 48. EMI data Conditions Symbol Parameter General conditions Max fHSE/fCPU(1) Monitored frequency band 0.1MHz to 30 MHz 30 MHz to 130 MHz 130 MHz to 1 GHz SAE EMI level 8 MHz/ 8 MHz/ 8 MHz/ 8 MHz 16 MHz 24 MHz 15 18 -1 2 20 21 1 2.5 24 16 4 2.5 dBµV Unit Peak level SEMI SAE EMI level VDD = 5 V TA = 25 °C LQFP80 package conforming to SAE IEC 61967-2 1. Data based on characterization results, not tested in production. Absolute maximum ratings (electrical sensitivity) Based on two different tests (ESD and LU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. For more details, refer to the application note AN1181. Electrostatic discharge (ESD) Electrostatic discharges (3 positive then 3 negative pulses separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). This test conforms to the JESD22-A114A/A115A standard. For more details, refer to the application note AN1181. Table 49. Symbol VESD(HBM) VESD(CDM) ESD absolute maximum ratings Ratings Electrostatic discharge voltage (Human body model) Electrostatic discharge voltage (Charge device model) Conditions TA = 25°C, conforming to JESD22-A114 TA= 25°C, conforming to JESD22-C101 Class A IV Maximum Unit value(1) 2000 1000 V V 1. Data based on characterization results, not tested in production. Doc ID 14733 Rev 9 87/103 Electrical characteristics STM8S207xx, STM8S208xx Static latch-up Two complementary static tests are required on 10 parts to assess the latch-up performance: ● ● A supply overvoltage (applied to each power supply pin) A current injection (applied to each input, output and configurable I/O pin) is performed on each sample. This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the application note AN1181. Table 50. Symbol Electrical sensitivities Parameter TA = 25 °C Conditions Class(1) A A A LU Static latch-up class TA = 85 °C TA = 125 °C 1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC specifications, that means when a device belongs to class A it exceeds the JEDEC standard. B class strictly covers all the JEDEC criteria (international standard). 88/103 Doc ID 14733 Rev 9 STM8S207xx, STM8S208xx Package characteristics 11 Package characteristics To meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at www.st.com. ECOPACK® is an ST trademark. Doc ID 14733 Rev 9 89/103 Package characteristics STM8S207xx, STM8S208xx 11.1 11.1.1 Package mechanical data LQFP package mechanical data Figure 43. 80-pin low profile quad flat package (14 x 14) D D1 D3 60 61 b L1 E3 E1 E 41 40 ccc C A A2 A1 80 Pin 1 identification L K 1 c 1S_ME Table 51. Symbol 80-pin low profile quad flat package mechanical data mm Min Typ Max 1.600 0.050 1.350 0.220 0.090 15.800 13.800 16.000 14.000 12.350 15.800 13.800 16.000 14.000 12.350 0.650 0.450 0.600 1.000 0.0° 3.5° 7.0° 0.100 0.0° 0.750 0.0177 16.200 14.200 0.6220 0.5433 1.400 0.320 0.150 1.450 0.380 0.200 16.200 14.200 0.0020 0.0531 0.0087 0.0035 0.6220 0.5433 0.6299 0.5512 0.4862 0.6299 0.5512 0.4862 0.0256 0.0236 0.0394 3.5° 7.0° 0.0039 0.0295 0.6378 0.5591 0.0551 0.0126 Min inches(1) Typ Max 0.0630 0.0059 0.0571 0.0150 0.0079 0.6378 0.5591 A A1 A2 b c D D1 D3 E E1 E3 e L L1 k ccc 1. Values in inches are converted from mm and rounded to four decimal places. 90/103 Doc ID 14733 Rev 9 STM8S207xx, STM8S208xx Figure 44. 64-pin low profile quad flat package (14 x 14) D D1 D3 48 49 b 33 32 ccc C A A2 Package characteristics L1 E3 E1 E A1 64 17 Pin 1 identification 1 16 L K c 1R_ME Table 52. Symbol 64-pin low profile quad flat package mechanical data (14 x 14) mm Min Typ Max 1.600 0.050 1.350 0.300 0.090 15.800 13.800 16.000 14.000 12.000 15.800 13.800 16.000 14.000 12.000 0.800 0.450 0.600 1.000 0.0 ° 3.5 ° 7.0 ° 0.100 0.0 ° 0.750 0.0177 16.200 14.200 0.6220 0.5433 1.400 0.370 0.150 1.450 0.450 0.200 16.200 14.200 0.0020 0.0531 0.0118 0.0035 0.6220 0.5433 0.6299 0.5512 0.4724 0.6299 0.5512 0.4724 0.0315 0.0236 0.0394 3.5 ° 7.0 ° 0.0039 0.0295 0.6378 0.5591 0.0551 0.0146 Min inches(1) Typ Max 0.0630 0.0059 0.0571 0.0177 0.0079 0.6378 0.5591 A A1 A2 b C D D1 D3 E E1 E3 e L L1 k ccc 1. Values in inches are converted from mm and rounded to four decimal places. Doc ID 14733 Rev 9 91/103 Package characteristics Figure 45. 64-pin low profile quad flat package (10 x 10) D D1 D3 48 49 b 33 32 ccc C A A2 STM8S207xx, STM8S208xx L1 E3 E1 E A1 64 17 Pin 1 identification 1 16 L K c 5W_ME Table 53. Symbol 64-pin low profile quad flat package mechanical data (10 x 10) mm Min Typ Max 1.600 0.050 1.350 0.170 0.090 12.000 10.000 12.000 10.000 0.500 0.000° 0.450 3.500° 0.600 1.000 7.000° 0.750 0.0000° 0.0177 1.400 0.220 0.150 1.450 0.270 0.200 0.0020 0.0531 0.0067 0.0035 0.4724 0.3937 0.4724 0.3937 0.0197 3.5000° 0.0236 0.0394 7.0000° 0.0295 0.0551 0.0087 Min inches(1) Typ Max 0.0630 0.0059 0.0571 0.0106 0.0079 A A1 A2 b C D D1 E E1 e K L L1 1. Values in inches are converted from mm and rounded to four decimal places. 92/103 Doc ID 14733 Rev 9 STM8S207xx, STM8S208xx Figure 46. 48-pin low profile quad flat package (7 x 7) D D1 D3 36 37 b E3 E1 E 25 24 ccc C A A2 Package characteristics L1 48 Pin 1 identification 13 1 12 A1 L K c 5B_ME Table 54. Symbol 48-pin low profile quad flat package mechanical data mm Min Typ Max 1.600 0.050 1.350 0.170 0.090 8.800 6.800 9.000 7.000 5.500 8.800 6.800 9.000 7.000 5.500 0.500 0.450 0.600 1.000 0.0° 3.5° 7.0° 0.080 0.0° 0.750 0.0177 9.200 7.200 0.3465 0.2677 1.400 0.220 0.150 1.450 0.270 0.200 9.200 7.200 0.0020 0.0531 0.0067 0.0035 0.3465 0.2677 0.3543 0.2756 0.2165 0.3543 0.2756 0.2165 0.0197 0.0236 0.0394 3.5° 7.0° 0.0031 0.0295 0.3622 0.2835 0.0551 0.0087 Min inches(1) Typ Max 0.0630 0.0059 0.0571 0.0106 0.0079 0.3622 0.2835 A A1 A2 b c D D1 D3 E E1 E3 e L L1 k ccc 1. Values in inches are converted from mm and rounded to four decimal places. Doc ID 14733 Rev 9 93/103 Package characteristics Figure 47. 44-pin low profile quad flat package (10 x 10) D D1 D3 33 34 b E3 E1 E 23 22 ccc C A A2 STM8S207xx, STM8S208xx L1 44 Pin 1 identification 12 1 11 A1 L K c 4Y_ME Table 55. Symbol 44-pin low profile quad flat package mechanical data mm Min Typ Max 1.600 0.050 1.350 0.300 0.090 11.800 9.800 12.000 10.000 8.000 11.800 9.800 12.000 10.000 8.000 0.800 0.450 0.600 1.000 0.0° 3.5° 7.0° 0.100 0.0° 0.750 0.0177 12.200 10.200 0.4646 0.3858 1.400 0.370 0.150 1.450 0.450 0.200 12.200 10.200 0.0020 0.0531 0.0118 0.0035 0.4646 0.3858 0.4724 0.3937 0.3150 0.4724 0.3937 0.3150 0.0315 0.0236 0.0394 3.5° 7.0° 0.0039 0.0295 0.4803 0.4016 0.0551 0.0146 Min inches(1) Typ Max 0.0630 0.0059 0.0571 0.0177 0.0079 0.4803 0.4016 A A1 A2 b c D D1 D3 E E1 E3 e L L1 k ccc 1. Values in inches are converted from mm and rounded to four decimal places. 94/103 Doc ID 14733 Rev 9 STM8S207xx, STM8S208xx Figure 48. 32-pin low profile quad flat package (7 x 7) ccc C D D1 D3 24 25 b E3 32 Pin 1 identification E1 E 17 16 A A2 Package characteristics L1 9 A1 1 8 L K c Table 56. Symbol 32-pin low profile quad flat package mechanical data mm Min Typ Max 1.600 0.050 1.350 0.300 0.090 8.800 6.800 9.000 7.000 5.600 8.800 6.800 9.000 7.000 5.600 0.800 0.450 0.600 1.000 0.0° 3.5° 7.0° 0.100 0.0° 0.750 0.0177 9.200 7.200 0.3465 0.2677 1.400 0.370 0.150 1.450 0.450 0.200 9.200 7.200 0.0020 0.0531 0.0118 0.0035 0.3465 0.2677 0.3543 0.2756 0.2205 0.3543 0.2756 0.2205 0.0315 0.0236 0.0394 3.5° 7.0° 0.0039 0.0295 0.3622 0.2835 0.0551 0.0146 Min inches(1) Typ Max 0.0630 0.0059 0.0571 0.0177 0.0079 0.3622 0.2835 A A1 A2 b c D D1 D3 E E1 E3 e L L1 k ccc 1. Values in inches are converted from mm and rounded to four decimal places. Doc ID 14733 Rev 9 95/103 Package characteristics STM8S207xx, STM8S208xx 11.2 Thermal characteristics The maximum chip junction temperature (TJmax) must never exceed the values given in Table 18: General operating conditions on page 56. The maximum chip-junction temperature, TJmax, in degrees Celsius, may be calculated using the following equation: TJmax = TAmax + (PDmax x ΘJA) Where: ● ● ● ● ● TAmax is the maximum ambient temperature in ° C ΘJA is the package junction-to-ambient thermal resistance in ° C/W PDmax is the sum of PINTmax and PI/Omax (PDmax = PINTmax + PI/Omax) PINTmax is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power. PI/Omax represents the maximum power dissipation on output pins, where: PI/Omax = Σ (VOL*IOL) + Σ((VDD-VOH)*IOH), and taking account of the actual VOL/IOL and VOH/IOH of the I/Os at low and high level in the application. Thermal characteristics(1) Parameter Thermal resistance junction-ambient LQFP 80 - 14 x 14 mm Thermal resistance junction-ambient LQFP 64 - 14 x 14 mm Thermal resistance junction-ambient LQFP 64 - 10 x 10 mm Thermal resistance junction-ambient LQFP 48 - 7 x 7 mm Thermal resistance junction-ambient LQFP 44 - 10 x 10 mm Thermal resistance junction-ambient LQFP 32 - 7 x 7 mm Value 38 45 46 57 54 60 Unit °C/W °C/W °C/W °C/W °C/W °C/W Table 57. Symbol ΘJA ΘJA ΘJA ΘJA ΘJA ΘJA 1. Thermal resistances are based on JEDEC JESD51-2 with 4-layer PCB in a natural convection environment. 11.2.1 Reference document JESD51-2 integrated circuits thermal test method environment conditions - natural convection (still air). Available from www.jedec.org. 96/103 Doc ID 14733 Rev 9 STM8S207xx, STM8S208xx Package characteristics 11.2.2 Selecting the product temperature range When ordering the microcontroller, the temperature range is specified in the order code (see Figure 49: STM8S207xx/208xx performance line ordering information scheme(1) on page 100). The following example shows how to calculate the temperature range needed for a given application. Assuming the following application conditions: ● ● ● ● ● Maximum ambient temperature TAmax= 82 °C (measured according to JESD51-2) IDDmax = 15 mA, VDD = 5.5 V Maximum eight standard I/Os used at the same time in output at low level with IOL = 10 mA, VOL= 2 V Maximum four high sink I/Os used at the same time in output at low level with IOL = 20 mA, VOL= 1.5 V Maximum two true open drain I/Os used at the same time in output at low level with IOL = 20 mA, VOL= 2 V PINTmax = 15 mA x 5.5 V = 82.5 mW PIOmax = (10 mA x 2 V x 8 ) + (20 mA x 2 V x 2) + (20 mA x 1.5 V x 4) = 360 mW This gives: PINTmax = 82.5 mW and PIOmax 360 mW: PDmax = 82.5 mW + 360 mW Thus: PDmax = 443 mW Using the values obtained in Table 57: Thermal characteristics on page 96 TJmax is calculated as follows for LQFP64 10 x 10 mm = 46 °C/W: TJmax = 82 °C + (46 °C/W x 443 mW) = 82 °C + 20 °C = 102 °C This is within the range of the suffix 6 version parts (-40 < TJ < 105 °C). In this case, parts must be ordered at least with the temperature range suffix 6. Doc ID 14733 Rev 9 97/103 STM8 development tools STM8S207xx, STM8S208xx 12 STM8 development tools Development tools for the STM8 microcontrollers include the full-featured STice emulation system supported by a complete software tool package including C compiler, assembler and integrated development environment with high-level language debugger. In addition, the STM8 is to be supported by a complete range of tools including starter kits, evaluation boards and a low-cost in-circuit debugger/programmer. 12.1 Emulation and in-circuit debugging tools The STice emulation system offers a complete range of emulation and in-circuit debugging features on a platform that is designed for versatility and cost-effectiveness. In addition, STM8 application development is supported by a low-cost in-circuit debugger/programmer. The STice is the fourth generation of full featured emulators from STMicroelectronics. It offers new advanced debugging capabilities including profiling and coverage to help detect and eliminate bottlenecks in application execution and dead code when fine tuning an application. In addition, STice offers in-circuit debugging and programming of STM8 microcontrollers via the STM8 single wire interface module (SWIM), which allows non-intrusive debugging of an application while it runs on the target microcontroller. For improved cost effectiveness, STice is based on a modular design that allows you to order exactly what you need to meet your development requirements and to adapt your emulation system to support existing and future ST microcontrollers. STice key features ● ● ● ● ● ● ● ● ● ● ● Occurrence and time profiling and code coverage (new features) Advanced breakpoints with up to 4 levels of conditions Data breakpoints Program and data trace recording up to 128 KB records Read/write on the fly of memory during emulation In-circuit debugging/programming via SWIM protocol 8-bit probe analyzer 1 input and 2 output triggers Power supply follower managing application voltages between 1.62 to 5.5 V Modularity that allows you to specify the components you need to meet your development requirements and adapt to future requirements Supported by free software tools that include integrated development environment (IDE), programming software interface and assembler for STM8. 98/103 Doc ID 14733 Rev 9 STM8S207xx, STM8S208xx STM8 development tools 12.2 Software tools STM8 development tools are supported by a complete, free software package from STMicroelectronics that includes ST Visual Develop (STVD) IDE and the ST Visual Programmer (STVP) software interface. STVD provides seamless integration of the Cosmic and Raisonance C compilers for STM8, which are available in a free version that outputs up to 16 Kbytes of code. 12.2.1 STM8 toolset STM8 toolset with STVD integrated development environment and STVP programming software is available for free download at www.st.com/mcu. This package includes: ST Visual Develop – Full-featured integrated development environment from ST, featuring ● ● ● ● ● ● Seamless integration of C and ASM toolsets Full-featured debugger Project management Syntax highlighting editor Integrated programming interface Support of advanced emulation features for STice such as code profiling and coverage ST Visual Programmer (STVP) – Easy-to-use, unlimited graphical interface allowing read, write and verify of your STM8 microcontroller’s Flash program memory, data EEPROM and option bytes. STVP also offers project mode for saving programming configurations and automating programming sequences. 12.2.2 C and assembly toolchains Control of C and assembly toolchains is seamlessly integrated into the STVD integrated development environment, making it possible to configure and control the building of your application directly from an easy-to-use graphical interface. Available toolchains include: ● ● ● Cosmic C compiler for STM8 – Available in a free version that outputs up to 16 Kbytes of code. For more information, see www.cosmic-software.com. Raisonance C compiler for STM8 – Available in a free version that outputs up to 16 Kbytes of code. For more information, see www.raisonance.com. STM8 assembler linker – Free assembly toolchain included in the STVD toolset, which allows you to assemble and link your application source code. 12.3 Programming tools During the development cycle, STice provides in-circuit programming of the STM8 Flash microcontroller on your application board via the SWIM protocol. Additional tools are to include a low-cost in-circuit programmer as well as ST socket boards, which provide dedicated programming platforms with sockets for programming your STM8. For production environments, programmers will include a complete range of gang and automated programming solutions from third-party tool developers already supplying programmers for the STM8 family. Doc ID 14733 Rev 9 99/103 Ordering information STM8S207xx, STM8S208xx 13 Ordering information Figure 49. STM8S207xx/208xx performance line ordering information scheme(1) Example: Product class STM8 microcontroller Family type S = Standard Sub-family type(2) 208 = Full peripheral set 207 = Intermediate peripheral set Pin count K = 32 pins S = 44 pins C = 48 pins R = 64 pins M = 80 pins Program memory size 6 = 32 Kbyte 8 = 64 Kbyte B = 128 Kbyte Package type T = LQFP Temperature range 3 = -40 °C to 125 °C 6 = -40 °C to 85 °C Package pitch No character = 0.5 mm B = 0.65 mm C = 0.8 mm Packing No character = Tray or tube TR = Tape and reel 1. For a list of available options (e.g. memory size, package) and orderable part numbers or for further information on any aspect of this device, please go to www.st.com or contact the ST Sales Office nearest to you. 2. Refer to Table 2: STM8S20xxx performance line features for detailed description. STM8 S 208 M B T 6 B TR 100/103 Doc ID 14733 Rev 9 STM8S207xx, STM8S208xx Revision history 14 Revision history Table 58. Date 23-May-2008 05-Jun-2008 22-Jun-2008 Document revision history Revision 1 2 3 Initial release. Added part numbers on page 1 and in Table 2 on page 11. Updated Section 4: Product overview. Updated Section 10: Electrical characteristics. Added part numbers on page 1 and in Table 2 on page 11. Added 32 pin device pinout and ordering information. Updated UBC option description in Table 13 on page 48. USART renamed UART1, LINUART renamed UART3. Max. ADC frequency increased to 6 MHz. Removed STM8S207K4 part number. Removed LQFP64 14 x 14 mm package. Added medium and high density Flash memory categories. Added Section 6: Memory and register map on page 33. Replaced beCAN3 by beCAN in Section 4.14.5: beCAN. Updated Section 10: Electrical characteristics on page 52. Updated LQFP44 (Figure 47 and Table 55), and LQFP32 outline and mechanical data (Figure 48, and Table 56). Changed VDD minimum value from 3.0 to 2.95 V. Updated number of High Sink I/Os in pinout. Removed FLASH _NFPR and FLASH _FPR registers in Table 9: General hardware register map. Removed preliminary status. Removed VQFN32 package. Added STM8S207C6, STM8S207S6. Updated external interrupts in Table 2 on page 11. Updated Section 10: Electrical characteristics. Document status changed from “preliminary data” to “datasheet”. Added LQFP64 14 x 14 mm package. Added STM8S207M8, STM8S207SB, STM8S208R8, STM8S208R6, STM8S208C8, and STM8S208C6, STM8S208SB, STM8S208S8, and STM8S208S6. Replaced “CAN” with “beCAN”. Added Table 3 to Section 4.5: Clock controller. Updated Section 4.8: Auto wakeup counter. Added beCAN peripheral (impacting Table 1 and Figure 6). Added footnote about CAN_RX/TX to pinout figures 3, 4, and 6. Table 6: Removed ‘X’ from wpu column of I2C pins (no wpu available). Added Table 11: Interrupt mapping. Changes 12-Aug-2008 4 20-Oct-2008 5 08-Dec-2008 6 30-Jan-2009 7 10-Jul-2009 8 Doc ID 14733 Rev 9 101/103 Revision history Table 58. Date STM8S207xx, STM8S208xx Document revision history (continued) Revision Changes Section 10: Electrical characteristics: Added data for TBD values; updated Table 15: Voltage characteristics and Table 18: General operating conditions; updated VCAP specifications in Table 18 and in Section 10.3.1: VCAP external capacitor; updated Figure 18; replaced Figure 19; updated Table 35: RAM and hardware registers; updated Figure 22 and Figure 35; added Figure 40: Typical application with I2C bus and timing diagram(1). Removed Table 56: Junction temperature range. Added link between ordering information Figure 49 and STM8S20xx features Table 2. Document status changed from “preliminary data” to “datasheet”. Table 2: STM8S20xxx performance line features: high sink I/O for STM8S207C8 is 16 (not 13). Table 3: Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers: updated bit positions for TIM2 and TIM3. Figure 5: LQFP 48-pin pinout: added CAN_TX and CAN_RX to pins 35 and 36; noted that these pins are available only in STM8S208xx devices. Figure 7: LQFP 32-pin pinout: replaced uart2 with uart3. Table 6: Pin description: added footnotes concerning beCAN availability and UART1_RX and UART3_RX pins. Table 13: Option byte description: added description of STM8L bootloader option bytes to the option byte description table. Added Section 9: Unique ID (and listed this attribute in Features). Section 10.3: Operating conditions: added introductory text. Table 18: General operating conditions: replaced “CEXT” with “VCAP” and added data for ESR and ESL; removed “low power dissipation” condition for TA. Table 26: Total current consumption in halt mode at VDD = 5 V, TA -40 to 85° C: replaced max value of IDD(H) at 85 °C from 30 µA to 35 µA for the condition “Flash in powerdown mode, HSI clock after wakeup”. Table 33: HSI oscillator characteristics: updated the ACCHSI factory calibrated values. Functional EMS (electromagnetic susceptibility) and Table 47: replaced “IEC 1000” with “IEC 61000”. Electromagnetic interference (EMI) and Table 48: replaced “SAE J1752/3” with “IEC 61967-2”. Table 57: Thermal characteristics: changed the thermal resistance junction-ambient value of LQFP32 (7x7 mm) from 59 °C/W to 60 °C/W. 10-Jul-2009 8 cont’d 13-Apr-2010 9 102/103 Doc ID 14733 Rev 9 STM8S207xx, STM8S208xx Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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