STM8SPLNB1
DiSEqC™ slave microcontroller for SaTCR based LNBs and
switchers
Datasheet - production data
Features
Clock, reset and supply management
– Reduced power consumption,
– Safe power on/off management
by low voltage detector (LVD),
– 2.95 to 5.5 V operating voltage,
– Internal 16MHz oscillator.
TSSOP20
4.40 mm body
Communication interface
– Two DiSEqCTM communication interfaces,
– Four I2C communication interfaces I/O
ports.
4 output pins for control of a legacy matrix.
SO20W
300 mils
UFQFPN20
3 x 3 mm
It is a complete hardware and firmware solution
for system designers who require an
implementation overview of the LNB device
control according to DiSEqC standard (Digital
Satellite Equipment Control).
Description
The STM8SPLNB1 is an 8-bit microcontroller
dedicated to DiSEqC slave operation in SaTCR
based LNBs (Low Noise Block) and switchers.
Figure 1. Functional block diagram
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December 2014
This is information on a product in full production.
DocID018831 Rev 5
1/44
www.st.com
Contents
STM8SPLNB1
Contents
1
Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1
Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1.1
2
3
STM8SPLNB1 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1
Supported DiSEqC commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2
DiSEqC commands details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2/44
Command signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2.2
Command 0x0F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2.3
Command 0x0D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2.4
Command 0x38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2.5
Command 0x5A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2.6
Command 0x5B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Configuration parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.1
5
2.2.1
Configuration parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1
4
Pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.1.1
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.1.2
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.1.3
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.1.4
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.3
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.3.1
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.3.2
VCAP external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.3.3
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.3.4
Reset pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.3.5
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.1
ECOPACK® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.2
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
DocID018831 Rev 5
STM8SPLNB1
5.3
Contents
5.2.1
TSSOP package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.2.2
SO20W package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.2.3
UFQFPN package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.3.1
6
Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.1
STM8SPLNB1 DiSEqC™ SLAVE microcontroller option list . . . . . . . . . . 37
Appendix A DiSEqC™ protocol basics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
A.1
A.2
7
Physical layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
A.1.1
DC voltage on coaxial cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
A.1.2
22 kHz signal on coaxial cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
A.1.3
Data transfer on coaxial cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Protocol layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
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3
List of tables
STM8SPLNB1
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
4/44
STM8SPLNB1 pins description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
SaTCRs implementation - ST7LNB1 compatible mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SaTCRs implementation - incremental order mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
STM8SPLNB1 DiSEqC™ supported commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Command 0x0F format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Command 0x0D format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Reply to command 0x0D format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Command 0x38 format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Command 0x5A format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Subcommands 0x5A format - ODU_SaTCR_Op . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Feeds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Command 0x5B format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Subcommands 0x5B format - ODU_SaTCR_Inst. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
STM8SPLNB1 EEPROM parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Truth table for support of 8 RF inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Application types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
DiSEqC Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Local oscillator frequencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Operating conditions at power-up/power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Total current consumption at VDD = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
RESET pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
EMS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
EMI data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
20-pin, 4.40 mm body, 0.65 mm pitch mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
20-pin, plastic small outline (300 mils) mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . 32
20-lead, ultra thin, fine pitch quad flat no-lead package (3 x 3) package
mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
DiSEqC™ frame byte definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
DocID018831 Rev 5
STM8SPLNB1
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
STM8SPLNB1 typical configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
TSSOP20/SO20W pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
UFQFPN20 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Signaling of the DiSEqC-ST command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
SaTCR control configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
SaTCR control and legacy configuration (standard RF band) . . . . . . . . . . . . . . . . . . . . . . 18
SaTCR control and legacy configuration (wide RF band). . . . . . . . . . . . . . . . . . . . . . . . . . 19
Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
External capacitor CEXT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Recommended reset pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
20-pin, 4.40 mm body, 0.65 mm pitch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
TSSOP20 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
20-pin, plastic small outline (300 mils) package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
20-lead, ultra thin, fine pitch quad flat no-lead package outline (3 x 3). . . . . . . . . . . . . . . . 33
Recommended footprint for on-board emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Recommended footprint without on-board emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Timing diagram for Tone Burst control signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
DiSEqC™ bit modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Timing diagram for typical DiSEqC™ (1.0 version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
DiSEqC™ message format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Microcontroller answer format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
DocID018831 Rev 5
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5
Device description
STM8SPLNB1
1
Device description
1.1
Implementation
STM8SPLNB1 device is receiving DiSEqC signal on the coaxial cable, decoding and
processing the DiSEqC commands. As a result, legacy matrix or I2C lines are controlled.
The STM8SPLNB1 device can also send DiSEqC answer back to master through coaxial
cable.
STM8SPLNB1 is designed for usage with LNB devices with I2C bus control and/or direct
pins control (see Figure 2: STM8SPLNB1 typical configuration). SaTCR1 device is typically
used in LNB application (see www.st.com for more SaTCR1 information).
Behavior of STM8SPLNB1 devices can be modified through a set of configuration
parameters which are stored in device data EEPROM memory. Configuration is done also
through specific DiSEqC commands. After final configuring the device can be locked to
given configuration (vendor configuration).
Figure 2: STM8SPLNB1 typical configuration shows the recommended configuration for the
hardware connections for LNB control with STM8SPLNB1 devices.
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Figure 2. STM8SPLNB1 typical configuration
,EGACYMATRIXCONTROL
ORNEXT)#CHANNELS
34-3,."
,
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1. Power supply must have level 5V +/- 10% for correct operation.
6/44
DocID018831 Rev 5
STM8SPLNB1
Pins description
Figure 3. TSSOP20/SO20W pinout
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Figure 4. UFQFPN20 pinout
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1.1.1
Device description
!)
Table 1. STM8SPLNB1 pins description
pin no.
pin no.
TSSOP20
UFQFPN20
/SO20W
pin
name
description
note
9
6
VDD
+5 V power supply
+/- 10 % tolerance
7
4
VSS
ground
_
4
1
8
5
VCAP
filtering capacitor
1 wF capacitor to ground
3
20
DRX1
DiSEqC receive data
input 2
HF signal after low pass filtering
2
19
DRX2
DiSEqC receive data
input 2
HF signal after low pass filtering secondary channel (less priority - see
later description)
RESET device reset
DocID018831 Rev 5
0.1 wF capacitor to ground (active low)
7/44
43
Device description
STM8SPLNB1
Table 1. STM8SPLNB1 pins description (continued)
pin no.
pin no.
TSSOP20
UFQFPN20
/SO20W
description
note
1
18
DTX
DiSEqC transmit data
output
22 kHz modulation signal - need
coupling to HF signal
20
17
SCL1
I2C clock output
I2C master channel 1 clock output
19
16
SDA1
I2C data input/output
I2C master channel 1 data input/output
12
9
SCL2
I2C clock output
I2C master channel 2 clock output
11
8
SDA2
I2C data input/output
I2C master channel 2 data input/output
17
14
SCL3
I2C clock output
I2C master channel 3 clock output
16
13
SDA3
I2C data input/output
I2C master channel 3 data input/output
15
12
SCL4
I2C clock output
I2C master channel 4 clock output
14
11
SDA4
I2C data input/output
I2C master channel 4 data input/output
5
8/44
pin
name
2
MODE
I2C addressing mode
select
DocID018831 Rev 5
Selection of I2C addressing mode see note (2) under Table 2: SaTCRs
implementation - ST7LNB1
compatible mode (pin has internal
pull-up)
STM8SPLNB1
2
STM8SPLNB1 operation
STM8SPLNB1 operation
STM8SPLNB1 has 8 output pins which can work as 4 I2C master channels. Each I2C
channel can address 2 LNB devices (2 different I2C addresses: 0xC8 and 0xCA) - see
Table 2: SaTCRs implementation - ST7LNB1 compatible mode and Table 3: SaTCRs
implementation - incremental order mode for assignment of given SaTCR to given I2C bus
and address.
Assignment depends from I2C addressing mode EEPROM parameter - see Table 14:
STM8SPLNB1 EEPROM parameters. As a convention, SaTCR1 must be associated to the
BPF having the lowest center frequency of the application, SaTCR2 to the BPF having the
next higher center frequency and so on.
Table 2. SaTCRs implementation - ST7LNB1 compatible mode
SatCR
number
SaTCR(1)
SaTCR address
0
SaTCR1
0xC8
1
SaTCR2
0xCA
2
SaTCR3
0xC8
3
SaTCR4
0xCA
4
SaTCR5
0xC8
5
SaTCR6
0xCA
6
SaTCR7
0xC8
7
SaTCR8/ legacy SaTCR
(for wide RF band
applications)
0xCA
I2C number
I2C1
I2C2
I2C3
I2C4
1. Selection of ST7LNB1 compatible mode: pin MODE (see Table 1: STM8SPLNB1 pins description) must be
grounded and I2C addressing mode EEPROM parameter (see Table 14: STM8SPLNB1 EEPROM
parameters) must be set to 0. Otherwise (e.g. pin MODE is left open or I2C addressing mode EEPROM
parameter is set to 1) is used incremental order mode.
Table 3. SaTCRs implementation - incremental order mode
SatCR
number
SaTCR(1)
SaTCR address
I2C number
0
SaTCR1
0xC8
I2C1
1
SaTCR2
0xCA
I2C2
2
SaTCR3
0xC8
I2C3
3
SaTCR4
0xCA
I2C4
4
SaTCR5
0xCA
I2C1
5
SaTCR6
0xC8
I2C2
6
SaTCR7
0xCA
I2C3
7
SaTCR8/ legacy SaTCR (for
wide RF band applications)
0xC8
I2C4
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STM8SPLNB1 operation
STM8SPLNB1
1. Selection of incremental order mode: pin MODE (see Table 1: STM8SPLNB1 pins description) is left open
or I2C addressing mode EEPROM parameter (see Table 14: STM8SPLNB1 EEPROM parameters) is set
to 1.
Another option is to decrease number of I2C channels and use the remaining pins for legacy
matrix LNB control - e.g. to have 2 I2C channels (4 pins) and 4 legacy matrix output pins see Table 16: Application types.
Operation mode and device behavior depends from final hardware configuration. This
behavior is selected through configuration parameters - see Table 14: STM8SPLNB1
EEPROM parameters.
Note:
Advantage of using incremental order mode is in applications with up to 4 SaTCRs - which
is common in practice. Then each SaTCR owns one I2C bus. I2C communication with
another SaTCRs is running on different I2C bus - so it does not disturb HF signal on given
SaTCR (SaTCR is sensitive to I2C bus signal transients).
Advantage of using ST7LNB1 compatible mode is in applications where is used SaTCRs
control together with legacy matrix outputs (MAT1-MAT4) - see Section 1.1.1: Pins
description. In this case there remains free only 2 I2C buses for SaTCRs control (MAT1MAT4 pins occupy I2C3 and I2C4 bus). In ST7LNB1 compatible mode 2 I2C buses can
address up to 4 SaTCRs - 2 SaTCRs per I2C bus. Disadvantage is the I2C bus disturbance
to SaTCR which is not addressed - shared I2C bus (HF filters on I2C buses is
recommended).
2.1
Supported DiSEqC commands
In the following Table 4: STM8SPLNB1 DiSEqC™ supported commands are listed DiSEqC
commands supported by STM8SPLNB1. For more details about commands, refer to the
DiSEqC™ slave microcontroller specifications at www.eutelsat.com.
Table 4. STM8SPLNB1 DiSEqC™ supported commands
10/44
command
number
command
name
0x00
RESET
0x0D
config read
Read configuration parameters from EEPROM
0x0F
config write
Write configuration parameters to EEPROM
0x38
write to port
DiSEqC 1.0: Write to port group command - Legacy commands
0x5A
operation
command
DiSEqC-ST normal operation commands:
ODU_Changechannel or ODU_SatCROFF
0x5B
installation
command
DiSEqC-ST installation commands:
ODU_Config, ODU_EEPvar.LOFREQ or ODU_SatCRxON
function
Reset DiSEqC™ microcontroller
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STM8SPLNB1
STM8SPLNB1 operation
2.2
DiSEqC commands details
2.2.1
Command signaling
To be detected, the DiSEqC-ST commands must be sent after a voltage change from 13 to
18 V. A delay time between 4 ms and 24 ms must be respected before sending the DiSEqCST commands (see Figure 5: Signaling of the DiSEqC-ST command).
Figure 5. Signaling of the DiSEqC-ST command
6
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^MS
MS T MS
6
!)
2.2.2
Command 0x0F
STM8SPLNB1 devices are shipped to customers with a default parameter values. These
parameters can be updated using a dedicated 0x0F DiSEqC command. This command has
the following format where “[data]” is the parameter value to be programmed at the “[index]”
location as described in Table 14: STM8SPLNB1 EEPROM parameters.
Table 5. Command 0x0F format
frame
DiSEqC™
address
command
data1
data2
0xE0/0xE2
[device address]
0x0F
[index]
[data]
Note:
The special command E0 xx 0F FF FF protects the EEPROM data from any subsequent
write access (where xx is the corresponding DiSEqC slave address).
2.2.3
Command 0x0D
This command is dedicated for reading configuration parameters. This command has the
following format where the “[index]” is location to be read as shown in Table 14:
STM8SPLNB1 EEPROM parameters.
Table 6. Command 0x0D format
frame
DiSEqC™ address
command
data1
0xE2
[device address]
0x0D
[index]
The format of the reply frame from slave has format according Table 7: Reply to command
0x0D format where “[data]” is the byte read from EEPROM.
Table 7. Reply to command 0x0D format
frame
data1
0xE4
[data]
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STM8SPLNB1 operation
2.2.4
STM8SPLNB1
Command 0x38
This command is used to write to port group command - legacy support.
For application supporting the legacy (except for application number 1), the backwards
signaling (13/18 V, 22 kHz tone) is recognized until a valid DiSEqC 1.0 command is
detected.
The following Table 8: Command 0x38 format presents the truth table for the legacy
commands.
.
2.2.5
Table 8. Command 0x38 format
command
equivalent
backward signalling
selected
feed
band
polarity
satellite
E0 xx 38 F0
13V / 0kHz
0
Low
Vertical
A
E0 xx 38 F1
13V / 22kHz
1
High
Vertical
A
E0 xx 38 F2
18V / 0kHz
2
Low
Horizontal
A
E0 xx 38 F3
18V / 22kHz
3
High
Horizontal
A
Command 0x5A
This command is used during LNB (or switched) normal operation (default operation after
configuration). Command 0x5A is DiSEqC command (see Table 9: Command 0x5A format)
with two data bytes. In dependence from those data bytes are performed two subcommands
which descriptions are in Table 10: Subcommands 0x5A format - ODU_SaTCR_Op.
Table 9. Command 0x5A format
frame
DiSEqC™
address
command
data1
data2
0xE0/0xE2
[device address]
0x5A
[data1](1)
[data2](1)
1. See Table 10: Subcommands 0x5A format - ODU_SaTCR_Op for details.
.
Table 10. Subcommands 0x5A format - ODU_SaTCR_Op
data1
data2
subcommand
description
[7:5]
[4:2]
[1:0]
[7:0]
ODU_ChangeChannel SaTCR(1) Feed(2) Tun[9:8](3) Tun[7:0](3)
ODU_PowerOff
SaTCR(1)
0
0x00
This command is used for the
channel selection.
This command is used to put
a SaTCR in low power mode.
1. SaTCR number - see Table 2: SaTCRs implementation - ST7LNB1 compatible mode.
2. Feed parameter - see Table 11: Feeds and Table 15: Truth table for support of 8 RF inputs.
3. Tuning word - see notes in Table 14: STM8SPLNB1 EEPROM parameters for description.
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STM8SPLNB1
STM8SPLNB1 operation
Table 11. Feeds(1)
.
RF input
Feed
Band
Polarization
Satellite
0
Low
Vertical
A
1
High
Vertical
A
2
Low
Horizontal
A
3
High
Horizontal
A
4
Low
Vertical
B
5
High
Vertical
B
6
Low
Horizontal
B
7
High
Horizontal
B
1. Applications supporting legacy are limited to one satellite only (satellite A - see Table 8: Command 0x38
format).
2.2.6
Command 0x5B
This command is used only during LNB (or switched) installation/configuration. Command
0x5B is DiSEqC command (see Table 12: Command 0x5B format) with two data bytes. In
dependence from those data bytes are performed three subcommands which descriptions
are in Table 13: Subcommands 0x5B format - ODU_SaTCR_Inst.
Table 12. Command 0x5B format
frame
DiSEqC™
address
command
data1
data2
0xE0/0xE2
[device address]
0x5B
[data1](1)
[data2](1)
1. See Table 13.: Subcommands 0x5B format - ODU_SaTCR_Inst for details.
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STM8SPLNB1 operation
.
STM8SPLNB1
Table 13. Subcommands 0x5B format - ODU_SaTCR_Inst
data1
data2
Subcommand
description
[7:5]
ODU_Config
ODU_Lofreq
ODU_SaTCRxSignalOn
SaTCR(1)
SaTCR(1)
xxh
[4:2] [1:0]
0
1
0
2
[7:0]
AppliNum(2)
This command is sent by the
STB in order to set the
STM8SPLNB1 application
number. If the data2 value
corresponds to the
STM8SPLNB1 AppliNum, then
the STM8SPLNB1 commands
SaTCR indicated in data1 to
send a tone having frequency:
F = BPF(4), else: F = (BPF +
20 MHz).
This command is sent by the
STB in order to set the L.O.
frequencies present in the LNB. If
the data2 value corresponds to
the STM8SPLNB1 LOfreqNum,
(3)
LOfreqNum
then the STM8SPLNB1
commands SaTCR indicated in
data1 to send a tone having
frequency: F = BPF(4), else:
F = (BPF + 20 MHz).
0
xxh
When receiving this command
the STM8SPLNB1 commands all
connected SaTCRs to send a
tone in order to indicate their
respective BPF(4) center
frequencies.
1. SaTCR number - see Table 2: SaTCRs implementation - ST7LNB1 compatible mode
2. See Table 17: DiSEqC Applications for details.
3. See Table 18: Local oscillator frequencies for details.
4. BPF is bandpass center frequency for a given SaTCR - see Table 14: STM8SPLNB1 EEPROM
parameters for details.
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STM8SPLNB1
3
Configuration parameters
Configuration parameters
STM8SPLNB1 devices are compliant with the Eutelsat DiSEqC slave microcontroller
specifications version 1.0, but they are not scanning the control pins to determine the slave
configuration. Instead this are the slave configuration parameters stored in EEPROM
memory and must be programmed for each specific application through programming
parameters in STM8SPLNB1 data EEPROM memory.
The EEPROM parameters described are the default configurations in our firmware. Custom
configurations can be programmed at factory on request according customer requirements
(FastROM process available). Customer can reprogram all EEPROM parameters through
DiSEqC command - see Section 2.2.2: Command 0x0F.
3.1
Configuration parameters
The slave configuration parameters for STM8SPLNB1 are listed in Table 14: STM8SPLNB1
EEPROM parameters:
Table 14. STM8SPLNB1 EEPROM parameters
description
default
value
index
parameter
00
Slave Address
01
SaTCR1 BPF (lsb)
0x5D
02
SaTCR1 BPF (msb)
0x02
03
SaTCR2 BPF (lsb)
0xC6
04
SaTCR2BPF (msb)
0x02
05
SaTCR3 BPF (lsb)
0x48
06
SaTCR3 BPF (msb)
07
SaTCR4 BPF (lsb)
0xFC
08
SaTCR4 BPF (msb)
0x03
09
SaTCR5 BPF (lsb)
0xFF
0A
SaTCR5BPF (msb)
0xFF
0B
SaTCR6 BPF (lsb)
0xFF
0C
SaTCR6 BPF (msb)
0xFF
0D
SaTCR7 BPF(lsb) / legacy
SaTCR Low band (msb)
0xFF
0E
SaTCR7 BPF(msb) / legacy
SaTCR Low band (lsb)
DiSEqC slave address(1)
(2)
0x11
0x03
0xFF
(3)
0F
SaTCR8 BPF(lsb) / legacy
SaTCR High band (msb)
0xFF
10
SaTCR8 BPF(msb) / legacy
SaTCR High band (lsb)
0xFF
11
Applitype
Application type number (refer to Table 16.)
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0x00
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Configuration parameters
STM8SPLNB1
Table 14. STM8SPLNB1 EEPROM parameters (continued)
index
parameter
description
default
value
12
AppliNum
Application number (refer to Table 17: DiSEqC
Applications)
0x04
13
High L.O freq Number
Refer to Table 18: Local oscillator frequencies
0x04
14
Low L.O freq Number
Refer to Table 18: Local oscillator frequencies
0x02
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
0xAC
SaTCR1 matrix truth table
0x35
0x59
SaTCR2 matrix truth table
0x6A
0x56
SaTCR3 matrix truth table
0x9A
0x95
SaTCR4 matrix truth table
0xFF
SaTCR5 matrix truth table
0xFF
0xFF
SaTCR6 matrix truth table
0xFF
0xFF
SaTCR7 matrix truth table
0xFF
0xFF
SaTCR8 matrix truth table /
legacy matrix
25
0xFF
SaTCRs GAIN(5)
26
27
SaTCRs 1 to 4 Gain
0xFF
SaTCRs 5 to 8 Gain
0xFF
(6)
SaTCRs number
2
0x04
2
28
I C addressing mode
29
Software Version Number
version number identification
Reserved
(8)
2A
2B
(7)
defines SaTCRs assignment to I C bus
0x00
0x15
0x00
0x00
1. Address 0x00 is also recognized as valid address.
2. SaTCRx BPF = BPFx center frequency [MHz]/2.
16/44
0xA6
(4)
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STM8SPLNB1
Configuration parameters
3. When an application supports the wide RF band only one local oscillator with a frequency FLO is present
in the LNB. In this case the selection of the high or the low band for the legacy output is performed by a
dedicated SaTCR.
Two parameters are needed for the band selection:
- The tuning word for the low band selection = [(FLO (MHz) - FLow (MHz))/4] - 350: where FLow
corresponds to the Low LO frequency.
- The tuning word for the high band selection = [(FLO (MHz) - FHigh (MHz))/4] - 350: where FHigh
corresponds to the High band LO frequency.
Example: in a wide band application with FLO= 13250 MHz, for emulating a low band local oscillator at
9750 MHz, index 0x0D and index 0x0E must be loaded with the decimal value dec [0D:0E] = round
((13250-9750)/4) - 350 = 525.
4. Matrix truth table for SaTCRx or legacy:
1) If 4 RF inputs are implemented then the matrix truth table has coding on 2 bytes: “aaaabbbbccccdddd”
where:
aaaa = selection of Feed1 on SaTCRx, aaaa = [MAT4, MAT3, MAT2, MAT1]
bbbb = selection of Feed0 on SaTCRx, bbbb = [MAT4, MAT3, MAT2, MAT1]
cccc = selection of Feed3 on SaTCRx, cccc = [MAT4, MAT3, MAT2, MAT1]
dddd = selection of Feed2 on SaTCRx,dddd = [MAT4, MAT3, MAT2, MAT1]
2) If 8 RF inputs are implemented then the truth table given in Table 15: Truth table for support of 8 RF
inputs is used.
5. To enable the support of 8 RF inputs: the value ‘0x0000’ has to be programmed in index 15h and 16h.
SaTCRs gain value: it has the following format on two bytes: “AaBbCcDd EeFfGgHh” where Aa= gain for
SaTCR1, Bb = gain for SaTCR2, Cc= gain for SaTCR3, Dd=gain for SaTCR4, Ee= gain for SaTCR5, Ff=
gain for SaTCR6, Gg= gain for SaTCR7, Hh=gain for SaTCR8 or legacy SaTCR. Upper case letters and
upper case letters indicate LNA and IF gain, respectively.
6. SaTCRs number does not include the legacy SaTCR for the wide RF band applications.
7. Defines assignment of SaTCR to I2C bus. 1 = incremental order mode, 0 = ST7LNB1 compatible mode or
incremental order mode in dependency from MODE pin (see Table 1: STM8SPLNB1 pins description)
state. See notes under Table 2: SaTCRs implementation - ST7LNB1 compatible mode and Table 3:
SaTCRs implementation - incremental order mode for details in assignment.
8. Reserved bytes: do not write to this location.
Table 15. Truth table for support of 8 RF inputs
Feed
MAT1
MAT2
MAT3
MAT4
0
0
0
0
0
1
1
0
0
0
2
0
1
0
0
3
1
1
0
0
4
0
0
1
0
5
1
0
1
0
6
0
1
1
0
7
1
1
1
0
Table 16. Application types
number
0
application type
SaTCR control(1) (see Figure 6:
SaTCR control configuration)
description
– Control through I2C of up to 8 SaTCRs
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Configuration parameters
STM8SPLNB1
Table 16. Application types (continued)
number
application type
description
1
SaTCR and legacy (standard RF band)
– Control through I2C up to 4 SaTCRs
(see Figure 7: SaTCR control and
legacy configuration (standard RF
– Control of a legacy matrix using up to 4 pins
band))
2
SaTCR and legacy (wide RF band)
(see Figure 8: SaTCR control and
legacy configuration (wide RF band))
– Control though I2C of up to 6 SaTCRs + legacy
– Control of a dedicated SaTCR for the legacy
support
1. This application could support up to 8 RF feeds. (applications 1 and 2 are limited to 4 RF feeds).
Figure 6. SaTCR control configuration
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Figure 7. SaTCR control and legacy configuration (standard RF band)
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34
-ATRIX
3A4#2
)#
-!4;TO=
$28$I3%Q#
34
34-30,."
!)
18/44
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STM8SPLNB1
Configuration parameters
Figure 8. SaTCR control and legacy configuration (wide RF band)
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3A4#2
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3A4#2
!)
Table 17. DiSEqC Applications
Application number
Application description
0x01
Single SatCR and legacy (standard RF band)
0x02
Twin SatCR (standard RF band)
0x03
Twin SatCR and legacy (standard RF band)
0x04
Quad SatCR (standard RF band)
0x05
Double Twin SatCR (standard RF band)
0x06
Twin SatCR (wide RF band)
0x07
Twin SatCR and legacy (wide RF band)
0x08
Quad SatCR (wide RF band)
0x09
8 SatCR (standard RF band)
0x0A
6 SatCR (standard RF band)
0x0B
Quad SatCR and legacy (standard RF band)
0x0C - 0xFF
reserved
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43
Configuration parameters
STM8SPLNB1
Table 18. Local oscillator frequencies
Wide RF band
Standard RF band
LofreqNum (hex)
20/44
Local oscillator frequency
0x00
none
0x01
not known
0x02
9.750 GHz
0x03
10.000 GHz
0x04
10.600 GHz
0x05
10.750 GHz
0x06
11.000 GHz
0x07
11.250 GHz
0x08
11.475 GHz
0x09
20.250 GHz
0x0A
5.150 GHz
0x0B
1.585 GHz
0x0C
13.850 GHz
0x0D
not allocated
0x0E
not allocated
0x0F
not allocated
0x10
not allocated
0x11
10.000 GHz
0x12
10.200 GHz
0x13
13.250 GHz
0x14
13.450 GHz
0x15 - 0x1F
not allocated
DocID018831 Rev 5
STM8SPLNB1
Electrical characteristics
4
Electrical characteristics
4.1
Parameter conditions
Unless otherwise specified, all voltages are referred to VSS.
4.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean ± 3 ū).
4.1.2
Typical values
Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 5 V. They are given
only as design guidelines and are not tested.
4.1.3
Loading capacitor
The loading conditions used for pin parameter measurement are shown in the following
figure.
Figure 9. Pin loading conditions
34- PIN
P&
4.1.4
Pin input voltage
The input voltage measurement on a pin of the device is described in the following figure.
Figure 10. Pin input voltage
34-PIN
6).
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43
Electrical characteristics
4.2
STM8SPLNB1
Absolute maximum ratings
Stresses above those listed as ‘absolute maximum ratings’ may cause permanent damage
to the device. This is a stress rating only and functional operation of the device under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
Table 19. Voltage characteristics
Symbol
VDDx - VSS
VIN
VESD
Ratings
Min
Max
-0.3
6.5
Input voltage on any pin
VSS - 0.3
VDD + 0.3
Electrostatic discharge voltage
See : Absolute
maximum ratings
(electrical sensitivity)
Supply voltage
Unit
V
Table 20. Current characteristics
Symbol
Max.(1)
Ratings
IVDD
Total current into VDD power lines
(source)(2)
100
IVSS
Total current out of VSS ground lines (sink)(2)
80
Output current sunk by any I/O and control pin
20
IIO
IINJ(PIN)(3)(4)
ūIINJ(PIN)
(3)
Output current source by any I/Os and control pin
- 20
Injected current on NRST pin
±4
Injected current on any other pin(5)
Total injected current (sum of all I/O and control
Unit
mA
±4
pins)(5)
± 20
1. Data based on characterization results, not tested in production.
2. All power (VDD) and ground (VSS) pins must always be connected to the external supply.
3. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN>VDD while a negative injection is induced by VIN
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