STMPE1601TBR

STMPE1601 16-bit enhanced port expander with keypad and PWM controller Xpander Logic Features ■ 16 GPIOs (8 operate at core supply VCC , 8 operate at IO supply Vio) Operating voltage 1.8 − 3.3 V Hardware keypad controller (8*8 matrix with 4 optional dedicated keys max) Keypad controller capable of detecting keypress in hibernation mode 4 basic PWM controller for LED brightness control Interrupt output (open drain) pin Optional 32 kHz clock input 8-channel programmable level translator Advanced power management system Ultra-low standby-mode current Package TFBGA25 (3 x 3 mm) ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ TFBGA25 Description The STMPE1601 is a GPIO (general purpose input/output) port expander able to interface a main digital ASIC via the two-line bidirectional bus (I2C). A separate GPIO expander IC is often used in mobile multimedia platforms to solve the problems of the limited number of GPIOs typically available on the digital engine. The STMPE1601 offers great flexibility, as each I/O can be configured as input, output or specific functions. The device is able to scan a keyboard, also provides PWM outputs for brightness control in backlight, and GPIO. This device has been designed to include very low quiescent current, and a wake-up feature for each I/O, to optimize the power consumption of the IC. Potential applications of the STMPE1601 include portable media players, game consoles, mobile and smart phones. Table 1. Device summary Order code STMPE1601TBR Package TFBGA25 Packaging Tape and reel June 2008 Rev 4 1/61 www.st.com 61 Contents STMPE1601 Contents 1 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 2.2 2.3 2.4 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin assignment and TFBGA ball location . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin mapping to TFBGA (top through view) . . . . . . . . . . . . . . . . . . . . . . . . . 6 GPIO pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1 3.2 Absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.1 4.2 DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Input/Output DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 10 5 6 Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 Minimizing current drain on I2C address lines . . . . . . . . . . . . . . . . . . . . . 13 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Acknowledge bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Slave device address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Memory addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 General call address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7 System controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.1 7.2 7.3 States of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Autosleep . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Keypress detect in the hibernate mode . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2/61 STMPE1601 Contents 8 Clocking system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8.1 8.2 Clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Power mode programming sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9 Interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 9.1 9.2 Interrupt system register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 9.1.1 Interrupt latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Programming sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 10 GPIO controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 10.1 10.2 10.3 GPIO control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 GPIO alternate function registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Hotkey feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 10.3.1 10.3.2 Programming sequence for Hotkey . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Minimum pulse width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 10.4 Level translator feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 11 Basic PWM controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 11.1 11.2 Interrupt on basic PWM controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Trigger feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 12 Keypad controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 12.1 12.2 Keypad configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Registers in keypad controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 13 14 15 Data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Keypad combination key registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Miscellaneous features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 15.1 15.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Under voltage lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 16 17 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 3/61 Block diagram STMPE1601 1 Block diagram Figure 1. STMPE1601 block diagram Keypad controller MUX Keypad input (column x0-x7) /GPIO 0-7 /PWM 0-3 (Powered by VCC) Main FSM PWM GPIO control MUX CLK_IN INT Keypad output (row y0-y7) /ADDR 0-2 /GPIO 8-15 (Powered by Vio) A0 A1 A2 SCLK SDAT I2C Interface GND1 GND2 POR VCC VIO CS00024 4/61 STMPE1601 Pin settings 2 2.1 Pin settings Pin connection Figure 2. Pin connection (bottom view) 1 2 3 4 5 TFBGA25 2.2 Pin assignment and TFBGA ball location Table 2. Pin assignment Name GPIO_0 GPIO_1 GPIO_2 GPIO_3 GPIO_4 GPIO_5 GPIO_6 GPIO_7 GPIO_8 GPIO_9 GPIO_10 Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Description GPIO 0/ KP_X0/ PWM_0 GPIO 1/ KP_X1/ PWM_1 GPIO 2/ KP_X2/ PWM_2 GPIO 3/ KP_X3/ PWM_3 GPIO 4/ KP_X4 GPIO 5/ KP_X5 GPIO 6/ KP_X6 GPIO 7/ KP_X7 GPIO 8/ KP_Y0 GPIO 9/ KP_Y1 GPIO 10/ KP_Y2 Ball name E5 D4 D5 C4 A5 A4 B3 A3 A2 A1 B2 5/61 Pin settings Table 2. Pin assignment (continued) Name GPIO_11 GPIO_12 GPIO_13 GPIO_14 GPIO_15 INT Reset_N SDATA SCLK CLK_IN VCC VIO GND GND Type IO IO IO IO IO O I A A A GPIO 11/ KP_Y3 GPIO 12/ KP_Y4 GPIO 13/ KP_Y5/ ADDR0 GPIO 14/ KP_Y6/ ADDR1 GPIO 15/ KP_Y7/ ADDR2 Open drain interrupt output pin Description STMPE1601 Ball Name B1 D1 D2 E1 E2 B5 E4 E3 D3 B4 C5 C1 C2 C3 External reset input, active LOW. Reset_N pulse width must be ≥ 20 μs. I2C DATA I2C clock 32 kHz input 1.8 − 3.3 V input for I2C module and digital core 1.8 − 3.3 V input for GPIO. The VIO must be ≥ VCC. Ground Ground 2.3 Pin mapping to TFBGA (top through view) Table 3. Pin mapping 1 A B C D E GPIO_9 GPIO_11 VIO GPIO_12 GPIO_14 2 GPIO_8 GPIO_10 GND GPIO_13 GPIO_15 3 GPIO_7 GPIO_6 GND SCLK SDATA 4 GPIO_5 CLK_IN GPIO_3 GPIO_1 RESET_N 5 GPIO_4 INT VCC GPIO_2 GPIO_0 6/61 STMPE1601 Pin settings 2.4 GPIO pin functions Table 4. Name GPIO_0 GPIO_1 GPIO_2 GPIO_3 GPIO_4 GPIO_5 GPIO_6 GPIO_7 GPIO_8 GPIO_9 GPIO_10 GPIO_11 GPIO_12 GPIO_13 GPIO_14 GPIO_15 GPIO pin functions Primary function GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO Alternate function 1 Keypad Keypad Keypad Keypad Keypad Keypad Keypad Keypad Keypad Keypad Keypad Keypad Keypad Keypad Keypad Keypad I2C ADDR during RESET I2C ADDR during RESET I2C ADDR during RESET Alternate function 2 PWM PWM PWM PWM Note 7/61 Maximum rating STMPE1601 3 Maximum rating Stressing the device above the rating listed in the “Absolute maximum ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. 3.1 Absolute maximum rating Table 5. Symbol VCC VIN VESD (HBM) Supply voltage Input voltage on GPIO pin ESD protection on each GPIO pin Absolute maximum rating Parameter Value 4.5 4.5 2 Unit V V kV 3.2 Thermal data Table 6. Symbol RthJA Thermal data Parameter Thermal resistance junction-ambient Operating ambient temperature Operating junction temperature -40 -40 Min Typ 100 25 25 85 125 Max Unit °C/W °C °C TA TJ 8/61 STMPE1601 Electrical specification 4 4.1 Electrical specification DC electrical characteristics Table 7. Symbol VCC VIO ICC ISLEEP IHIBERNATE ICC ISLEEP IHIBERNATE ICC ISLEEP IHIBERNATE ICC ISLEEP IHIBERNATE INT DC electrical characteristics Value Parameter 1.8 V supply voltage IO supply voltage Active current Sleep current Hibernate current Active current Sleep current Hibernate current(1) Active current Sleep current Hibernate current Active current Sleep current Hibernate current(1) 4 VIO VCC = 3.3 V T= 85 °C VIO VCC = 1.8 V T= 85 °C VIO VCC = 3.3 V T= 25 °C VIO VCC = 1.8 V T= 25 °C Test conditions Min 1.65 1.65 1.2 18 0.5 3.0 50 1.2 Typ Max 3.6 3.6 1.6 25 1.5 3.8 60 3 2 32 2 4.8 75 5 V V mA μA μA mA μA μA mA μA μA mA μA μA mA Unit Open drain output current 1. If only the basic GPIO function is required, the STMPE1601 could be designed to work mostly in hibernate mode. Active mode is used only when there are any changes in the I/O status. 9/61 Electrical specification STMPE1601 4.2 Input/Output DC electrical characteristics The 1.8 V I/O complies to the EIA/JEDEC standard JESD8-7. Table 8. Symbol Vil Vih Vhyst Vil Vih Vhyst I/O DC electrical characteristic Value Parameter Min Low level input voltage High level input voltage Schmitt trigger hysteresis Low level input voltage High level input voltage Schmidt trigger hysteresis VIO = 1.8 V VIO = 1.8 V VIO = 1.8 V VIO = 3.3 V VIO = 3.3 V VIO = 3.3 V 2.14 0.20 1.17 0.10 1.15 Typ Max 0.63 V V V V V V Unit Table 9. Symbol DC input specification (1.55 V < VCC < 1.95 V) Parameter Test conditions Iol = 4 mA VIO = 1.8 V Ioh = 4 mA VIO = 1.8 V Iol = 4 mA VIO = 3.3 V Ioh = 4 mA VIO = 3.3 V 2.48 1.35 0.83 Value Unit Min Typ Max 0.45 V V V V Vol Voh Vol Voh Low level output voltage High level output voltage Low level output voltage High level output voltage Table 10. Symbol Ipu Rup(1) Rup(2) DC output specification (1.55 V < VCC < 1.95 V) Value Parameter Pull-up current Equivalent pull-up resistance Equivalent pull-up resistance Test conditions Min Vi = 0 V VCC = 3.3 V VCC = 1.8 V VIO = 3.3 V VIO = 1.8 V 15 30 50 30 50 Typ 35 60 100 60 100 Max 65 90 150 90 150 μA KΩ KΩ KΩ KΩ Unit 1. Applicable to GPIO_0 to GPIO_7. 2. Applicable to GPIO_8 to GPIO_15. 10/61 STMPE1601 Register map 5 Register map All the registers have the size of 8-bit. For each of the module, their registers are residing within the given address range. Table 11. Address 0x00 – 0x07 0x80 – 0x81 0x10 – 0x1F 0x30 – 0x37 0x38 – 0x3F 0x60 – 0x6F 0x70 – 0x77 0x82 – 0xBF Register map summary table Module register Clock and power manager module Interrupt controller module Description Clock and power manager register range Interrupt controller register range Auto-increment (during read/write) Yes Yes Yes No Yes Yes Yes PWM controller module PWM controller register range PWM controller module PWM controller register range Keypad controller module Rotator controller module Keypad controller register range Rotator controller register range GPIO controller module GPIO controller register range 11/61 I2C interface STMPE1601 6 I2C interface The features that are supported by the I2C interface are listed below: ● ● ● ● ● ● ● ● I2C slave device Operates at VCC (1.8 - 3.3 V) Compliant to Philips I2C specification version 2.1 Supports standard (up to 100kbps) and fast (up to 400 kbps) modes 7-bit and 10-bit device addressing modes General Call Start/Restart/Stop Address up to 8 STMPE1601 devices via the I2C interface The address is selected by the state of 3 pins. The state of the pins is read upon reset and then the pins can be configured for normal operation. The pins have a pull-up or down to set the address. The I2C interface module allows the connected host system to access the registers in the STMPE1601. Table 12. A2 0 0 0 0 1 1 1 1 I2C addresses A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 7-bit address 40h 41h 42h 43h 44h 45h 46h 47h 12/61 STMPE1601 I2C interface 6.1 Minimizing current drain on I2C address lines The GPIOs 13-15 are used as I2C address input during POR. Pull-up/down resistor of 500 K-1.5 M is recommended for these address lines. In the case that these pins are driven to an opposite logic level during device operation, there would be a current drain of VIO/R. This amounts to a significant current for portable devices. To minimize the current drain on I2C lines, a few methods are recommended. 1. 2. If maximum keypad size is not required, these shared lines should not be used for keypad operation. If the maximum keypad size is required, choose I2C address 0x40, as this requires that all 3 address lines to be pulled to ground, minimizing the current drain in keypad operation. In this mode of operation, the pull up/down resistors on the I2C lines should be: Recommended pull up/down resistors on the I2C lines 1.8 V 2.5 V 3.3 V Reset RC or pulse width(1) Note Table 13. VIO RPU/RPD 1.5 M 1.2 M 1M 270 K/0.47 μF 120 ms All 3 address lines are used for keypad controller 2 address lines are used for keypad controller 1 address line is used for keypad controller RPU/RPD 1.0 M 800 K 660 K 180 K/0.47 μF 80 ms RPU/RPD 500 K 400 K 330 K 90K/0.47 μF 40 ms 1. Recommended values are chosen to minimize leakage current. A reset circuit with longer RC is used to ensure enough time for the address lines to settle to the final values. 3. In system-controlled idle state, all keypad pins to be configured as hotkey with interrupt enabled. If any key is pressed, system initiates keypad controller for scanning operation. 13/61 I2C interface STMPE1601 6.2 Start condition A Start condition is identified by a falling edge of SDATA while SCLK is stable at high state. A Start condition must precede any data/command transfer. The device continuously monitors for a Start condition and does not respond to any transaction unless one is encountered. 6.3 Stop condition A Stop condition is identified by a rising edge of SDATA while SCLK is stable at high state. A Stop condition terminates the communication between the slave device and bus master. A read command that is followed by NoAck can be followed by a Stop condition to force the slave device into idle mode. When the slave device is in idle mode, it is ready to receive the next I2C transaction. A Stop condition at the end of a write command stops the write operation to the registers. 6.4 Acknowledge bit (ACK) The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter releases the SDATA after sending eight bits of data. During the ninth bit, the receiver pulls the SDATA low to acknowledge the receipt of the eight bits of data. The receiver may leave the SDATA in high state if it would to not acknowledge the receipt of the data. 6.5 Data input The device samples the data input on SDATA on the rising edge of the SCLK. The SDATA signal must be stable during the rising edge of SCLK and the SDATA signal must change only when SCLK is driven low. 6.6 Slave device address The slave device address is a 7 or 10-bit address, where the least significant 3-bit are programmable. These 3-bit values will be loaded in once upon reset and after that these 3 pins no longer be needed with the exception during General Call. Up to 8 STMPE1601 devices can be connected on a single I2C bus. 6.7 Memory addressing For the bus master to communicate to the slave device, the bus master must initiate a Start condition and followed by the slave device address. Accompanying the slave device address, there is a Read/Write bit (R/W). The bit is set to 1 for Read and 0 for Write operation. If a match occurs on the slave device address, the corresponding device gives an acknowledgement on the SDA during the 9th bit time. If there is no match, it deselects itself from the bus by not responding to the transaction. 14/61 STMPE1601 I2C interface 6.8 Operating modes Table 14. Mode Operating modes Bytes Programming sequence START, Device address, R/W = 0, Register address to be read reSTART, Device address, R/W = 1, Data Read, STOP If no STOP is issued, the Data Read can be continuously performed. If the register address falls within the range that allows address autoincrement, then register address auto-increments internally after every byte of data being read. For register address that falls within a nonincremental address range, the address will be kept static throughout the entire read operations. Refer to the Memory Map table for the address ranges that are auto and non-increment. An example of such a non-increment address is FIFO. START, Device address, R/W = 0, Register address to be written, Data Write, STOP. If no STOP is issued, the Data Write can be continuously performed. If the register address falls within the range that allows address autoincrement, then register address auto-increments internally after every byte of data being written. For those register addresses that fall within a non-incremental address range, the address will be kept static throughout the all write operations. Refer to the memory map table for the address ranges that are auto and non-increment. An example of a non-increment address is Data Port for initializing the PWM commands. Read ≥1 Write ≥1 Figure 3. I2C transaction Ack Restart R/W=0 R/W=1 Device Address Reg Address No Ack One byte Read Device Address Data Read Start Stop Ack Ack Ack Restart More than one byte Read Device Address Reg Address Device Address Data Read Data Read + 1 No Ack R/W=0 R/W=1 Data Read + 2 Start Ack One byte Write Device Address Reg Address Data to be written Ack Restart R/W=0 Start Device Address Reg Address Ack Restart R/W=0 Data to Write + 1 Start Data to Write + 2 Master Slave Ack Stop Ack Ack Ack More than one byte Read Data to Write Ack Stop Ack Ack Ack 15/61 Stop Ack I2C interface STMPE1601 6.9 General call address A general call address is a transaction with the slave address of 0x00 and R/W = 0. When a general call address is made, STMPE1601 responds to this transaction with an acknowledgement and behaves as a slave-receiver mode. The meaning of a general call address is defined in the second byte sent by the master-transmitter. Table 15. R/W 0 General call address Definition A 2-byte transaction in which the second byte tells the slave device to reset and write (or latch in) the 2-bit programmable part of the slave address. A 2-byte transaction in which the second byte tells the slave device not to reset and write (or latch in) the 2-bit programmable part of the slave address. Not allowed as second byte. Second byte value 0x06 0 0 0x04 0x00 Note: All other second byte values will be ignored. 16/61 STMPE1601 System controller 7 System controller The system controller is the heart of the STMPE1601. It contains the registers for power control, and the registers for chip identification. The system registers are: Table 16. System registers Address 0x80 0x81 0x02 0x03 Register_Name CHIP_ID VERSION_ID SYS_CTRL SYS_CTRL_2 CHIP_ID 7 6 5 Chip identification register 4 3 2 1 0 8-bit MSB of CHIP_ID R 0 R 0 R 0 R 0 R 0 R 0 R 1 R 0 VERSION_ID 7 6 5 Version identification register 4 3 2 1 0 8-bit VERSION_ID R 0 R 0 R 0 R 1 R 0 R 0 R 0 R 0 17/61 System controller STMPE1601 SYS_CTRL 7 SOFT_RESET W RW 0 6 CLOCK SOURCE RW R 0 5 DIS_32KHz RW R 0 System control register 4 SLEEP RW RW 0 3 EN_GPIO RW R 1 2 RESERVED RW R 0 1 EN_KPC RW R 1 0 EN_SPWM RW R 1 Address: Type: Reset: Description: 0x02 R/W 0x0B System control register. [7] SOFT_RESET Writing a ‘1’ to this bit will do a soft reset of the device. Once the reset is done, this bit will be cleared to ‘0’ by the HW. [6] CLOCK_SOURCE Set to ‘1’ if external 32 kHz clock were to be used. ‘0’ by default. [5] DIS_32 kHz: Set this bit to disable the 32 kHz OSC, thus putting the device in hibernate mode. [4] SLEEP: Writing a ‘1’ to this bit will put the device in sleep mode. On going to sleep mode, this mode is reset internally. When in sleep mode, the internal RC oscillator will output a slower sleep clock which will be used in the device. [3] EN_GPIO: Writing a ‘0’ to this bit will gate off the clock to the GPIO module, thus stopping its operation [2] RESERVED [1] EN_KPC: Writing a ‘0’ to this bit will gate off the clock to the Keypad Controller module, thus stopping its operation [0] EN_SPWM Writing a ‘0’ to this bit will gate off the clock to the Simple PWM Controller module, thus stopping its operation 18/61 STMPE1601 System controller SYS_CTRL_2 7 6 RESERVED R 0 5 System control register 2 4 VIO_OFF R 0 3 AUTOSLEEP_EN RW 0 2 SLEEP_2 RW 0 1 SLEEP_1 RW 0 0 SLEEP_0 RW 0 Address: Type: Reset: Description: 0x03 R/W 0x00 System control register [7] RESERVED [6] RESERVED [5] RESERVED [4] VIO_OFF: Writing a ‘1’ to this bit is mandatory before shuting off the VIO supply while maintaining the VCC supply. This ensure that the level shifters for GPIOs 15-8 are properly powered down so as not to induce high current and also not to affect the integrity of any external signals that are on the bus where these GPIOs are connected. [3] AUTOSLEEP_EN: “1” to enable auto-sleep feature. “0” to disable auto-sleep. [2:0] SLEEP: 000 for 4 mS delay 001 for 16 mS delay 010 for 32 mS delay 011: for 64 mS delay 100: for 128 mS delay 101: for 256 mS delay 110: for 512 mS delay 111: for 1024 mS delay 19/61 System controller STMPE1601 7.1 States of operation Figure 4. Modes of operation OPERATIONAL 32K: ON RC: OFF Set Sleep bit or autosleep Keypad, Interrupts & I2 C transaction SLEEP 32K: ON RC: OFF 2 I C transaction HIBERNATE 32K: OFF RC: OFF Set Disable_32K bit Reset Valid Keypress detect The device has three main modes of operation: ● Operational mode: This is the mode, whereby normal operation of the device takes place. In this mode, the RC clock is available and the main FSM unit routes this clock and the 32 KHz clock to all the device blocks that are enabled. In this mode, individual blocks that need not to be working can be turned off by the master by programming the bits 3 to 0 of the SYS_CTRL register. Sleep mode: In this low-power mode, the RC oscillator is powered down. All the blocks which need clocks derived from the 32KHz clock will continue getting a 32 KHz clock. In this mode also, iindividual blocks can be turned off by the master by programming the bits 3 to 0 of the SYS_CTRL register. However, the master needs to program the SYS_CTRL register before coming into this mode, as in the sleep mode, the IIC interface is not active except to detect traffic for wakeup. Any activity on the I2C port (intended I2C transaction for the device) or Wakeup pin or Hotkey activity will cause the device to leave this mode and go into the Operational mode. When leaving this mode, the I2C will need to hold the SCLK till the RC clock is ready. Hibernate mode: This mode is entered when the system writes a ‘1’ to bit 5 of the SYS_CTRL register. In this mode, the device is completely inactive as there is absolutely no clock. Only a Reset or a wakeup on IIC will bring back the System to operational mode. A keypress detect will bring the system to Sleep mode, in which the debounce of the key will take place. ● ● Note: The 32 kHz clock mentioned in this section can be (1) an externally fed 32 KHz clock, or (2) an internally generated (from RC OSC) clock. In case the internal clock is used, the clock has a range of 25 to 45 KHz. 20/61 STMPE1601 System controller 7.2 Autosleep The host system may configure the STMPE1601 to go into sleep mode automatically whenever there is a period of inactivity following a complete I2C transaction with the STMPE1601. This inactivity means there is no intended I2C transaction for the device. For example, if there is an I2C transaction sent by the host to other slave devices, the STMPE1601 device will still be counting down for the auto-sleep. The STMPE1601 device resets the autosleep time-out counter only when it receives an I2C transaction meant for the device itself. This autosleep feature is controlled by the SYS_CTRL_2 (system control register 2). All those events that trigger an interrupt (KPC, hot-key) would result in a transition from Sleep state to Operational state automatically. The wakeup can also be performed through the I2C transaction intended for the device. 7.3 Keypress detect in the hibernate mode When in Hibernate mode, a keypress detect causes the system to go into sleep mode. The sleep clock (32 kHz) is then used to debounce the key to detect a valid key. If the keypress is detected to be valid, the system stays in sleep mode. If the key is detected to be invalid, the system goes back into Hibernate mode. 21/61 Clocking system STMPE1601 8 Clocking system Figure 5. Clocking system Internal RC OSC System clock Clock control CLK_IN SCLK Pin System control register The decision on clocks is based on the bits written into the SYS_CTRL registers. Bits 0 to 4 of the SYS_CTRL register allow to control the gating of clocks to the Rotator, Keypad controller, PWM and GPIO respectively in the operational mode. 8.1 Clock source By default, when the STMPE1601 powers up, it derives a 32 KHz clock from the internal RC oscillator for its operation. If an external clock source is available, it must be configured to accept an external clock through the SYS_CTRL register. Reset control: There are 4 sources of reset: ● ● ● ● Reset_N pin LVD reset Soft reset bit of the SYS_CTRL register I2C reset from the I2C block. 22/61 STMPE1601 Clocking system 8.2 Power mode programming sequence To put the device in sleep mode, the following needs to be done by the host: – – Write a '1' to bit 4 of the SYS_CTRL register. Assert a wakeup routine on the I2C bus by sending the Start bit, followed by the device address and the Write bit. Subsequently, proceed with sending the Base Register address and continue with a normal I2C transaction. The device wakes up upon receiving the correct device address and in Write direction. In other words, the procedure of waking up the device is performed by just sending an I2C transaction to the device. This procedure can be extended to wake up the device that is in hibernate mode. Write a '1' to bit 7 of the SYS_CTRL register. This bit is automatically cleared upon reset. Set the Disable_32K bit to '1' Assert a system reset or put a wakeup on the I2C To wake up the device, the host is required to: To do a soft reset to the device, the host needs to do the following: – To go into Hibernate mode, the following needs to be done by the host: – – – To come out of the Hibernate mode, the following needs to be done by the host: 23/61 Interrupt system STMPE1601 9 Interrupt system The STMPE1601 uses a highly flexible interrupt system. It allows the host system to configure the type of system events that should result in an interrupt, and pinpoints the source of interrupt by status register. The INT pin can be configured as ACTIVE HIGH, or ACTIVE LOW. Once asserted, the INT pin would de-assert only if the corresponding bit in the interrupt status register is cleared. Figure 6. Interrupt system Keypad controller PWM controller Interrupt status register Interrupt enable register Interrupt generation GPIO controller Interrupt polarity control (System control register) 9.1 Interrupt system register map Table 17. Address 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 Register map Register name INT_CTRL_MSB Interrupt control register INT__CTRL_LSB INT_EN_MASK_MSB Interrupt enable mask register INT_EN_MASK_LSB INT_STA_MSB Interrupt status register INT_STA_LSB INT_EN_GPIO_MASK _MSB Interrupt enable GPIO mask register INT_EN_GPIO_MASK _LSB INT_STA_GPIO_MSB Interrupt status GPIO register INT_STA_GPIO_LSB Yes Yes Yes Yes Yes Yes Yes Yes Yes Description Auto-increment (during sequential R/W) Yes 24/61 STMPE1601 Interrupt system 9.1.1 Interrupt latency When the generation of interrupts by the GPIO as input is enabled, the latency (time taken from actual transition at GPIO to time of INT pin assertion) is shown in the following table: Table 18. Interrupt latency State of operation Hibernation Sleep Active Interrupt latency 10 uS max 5 uS max 2 uS max INT_CTRL 15 14 13 12 11 10 Interrupt control register 9 8 7 6 5 4 3 2 1 0 INT_CTRL_msb Reserved R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 INT_CTRL_lsb IC2 R 0 R 0 RW 0 IC1 RW 0 IC0 RW 0 Address: Type: Reset: Description: 0x10, 0x11 R, R/W 0x00 The interrupt control register is used to configure the interrupt controller. It has a global enable interrupt mask bit that controls the interruption to the host. [2] IC2: Output Interrupt polarity ‘0’ = Active low/falling edge ‘1’ = Active high/rising edge [1] IC1: Output Interrupt Type ‘0’ = Level interrupt ‘1’ = Edge interrupt [0] IC0: Global Interrupt Mask bit When this bit is written a ‘1’, it will allow interruption to the host. If it is written with a ‘0’, then, it disables all interruption to the host. Writing to this bit does not affect the INT_EN_MASK value. [15:3] RESERVED 25/61 Interrupt system STMPE1601 INT_EN_MASK 15 14 13 12 11 10 9 INT_EN_MASK_msb Interrupt enable mask register 8 IE8 7 IE7 R/W 0 6 IE6 R/W 0 5 IE5 RW 0 4 IE4 RW 0 3 IE3 RW 0 2 IE2 RW 0 1 IE1 RW 0 0 IE0 RW 0 INT_EN_MASK_lsb R 0 R 0 RW 0 R 0 R 0 R 0 R 0 R 0 Address: Type: Reset: Description: 0x12, 0x13 R, R/W 0x00 The interrupt enable mask register is used to enable the interruption from a particular interrupt source to the host. [8] IE[x]: Interrupt Enable Mask (where x = 8 to 0) IE0: Wake-up interrupt mask IE1: Keypad controller interrupt mask IE2: Keypad controller FIFO overflow interrupt mask IE3: Reserved IE4: Basic PWM controller 0 interrupt mask IE5: Basic PWM controller 1 interrupt mask IE6: Basic PWM controller 2 interrupt mask IE7: Basic PWM controller 3 interrupt mask IE8: GPIO controller interrupt mask Writing a ‘1’ to the IE[x] bit enables the interruption to the host. [15:9] RESERVED 26/61 STMPE1601 Interrupt system INT_STA 15 14 13 12 ISR_msb 11 10 Interrupt status register 9 8 7 6 5 4 3 2 1 0 ISR_lsb IS8 IS8 RW 0 IS8 RW 0 IS5 RW 0 IS4 RW 0 IS3 RW 0 IS2 RW 0 IS1 RW 0 IS0 RW 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 RW 0 Address: Type: Reset: Description: 0x14, 0x15 R, R/W 0x00 The interrupt status register monitors the status of the interruption from a particular interrupt source to the host. Regardless whether the INT_EN bits are enabled or not, the INT_STA bits are still updated. [8:0] IS[x]: Interrupt status (where x = 8 to 0) Read: IE0: Wake-up Interrupt Status IE1: Keypad controller interrupt status IE2: Keypad controller FIFO overflow interrupt status IE3: Reserved IE4: Basic PWM controller 0 interrupt status IE5: Basic PWM controller 1 interrupt status IE6: Basic PWM controller 2 Interrupt status IE7: Basic PWM controller 3 interrupt status IE8: GPIO Controller Interrupt Status Write: a write to a IS[x] bit with a value of ‘1’ will clear the interrupt and a write with a value of ‘0’ has no effect on the IS[x] bit. [15:9] RESERVED 27/61 Interrupt system STMPE1601 INT_EN_GPIO_MASK 15 14 13 12 11 INT_EN_GPIO_MASK_msb IEG15 RW 0 IEG14 RW 0 IEG13 RW 0 IEG12 RW 0 IEG11 RW 0 Interrupt enable GPIO mask register 10 9 8 7 6 5 4 3 2 1 0 INT_EN_GPIO_MASK _lsb IEG9 RW 0 IEG8 RW 0 IEG7 RW 0 IEG6 RW 0 IEG5 RW 0 IEG4 RW 0 IEG3 RW 0 IEG2 RW 0 IEG1 RW 0 IEG0 RW 0 IEG10 RW 0 Address: Type: Reset: Description: 0x16, 0x17 R/W 0x00 The interrupt enable GPIO mask register is used to enable the interruption from a particular GPIO interrupt source to the host. The IEG[15:0] bits are the interrupt enable mask bits correspond to the GPIO[15:0] pins . [15:0] IEG[x]: interrupt enable GPIO mask (where x = 15 to 0) Writing a ‘1’ to the IE[x] bit will enable the interruption to the host. INT_STA_GPIO 15 14 13 12 11 Interrupt status GPIO register 10 9 8 7 6 5 4 3 2 1 0 INT_STA_GPIOR_msb ISG15 RW 0 ISG14 RW 0 ISG13 RW 0 ISG12 RW 0 ISG11 RW 0 ISG10 RW 0 ISG9 RW 0 ISG8 RW 0 ISG7 RW 0 ISG6 RW 0 INT_STA_GPIOR _lsb ISG5 RW 0 ISG4 RW 0 ISG3 RW 0 ISG2 RW 0 ISG1 RW 0 ISG0 RW 0 Address: Type: Reset: Description: 0x18, 0x19 R/W 0x00 The interrupt status GPIO register monitors the status of the interruption from a particular GPIO pin interrupt source to the host. Regardless whether the INT_EN_GPIO_MASK bits are enabled or not, the INT_STA_GPIO bits are still updated. The INT_STA_G[15:0] bits are the interrupt status bits correspond to the GPIO[15:0] pins. [15:0] ISG[x] Interrupt status GPIO (where x = 15 to 0) Read: Interrupt status of the GPIO[x]. Write: A write to a ISG[x] bit with a value of ‘1’ will clear the interrupt and a write with a value of ‘0’ has no effect on the ISG[x] bit. 28/61 STMPE1601 Interrupt system 9.2 Programming sequence To configure and initialize the Interrupt Controller to allow interruption to host, observe the following steps: ● ● ● ● ● ● Set the INT_EN_MASK and INT_EN_GPIO_MASK registers to the desired values to enable the interrupt sources that are to be expected to receive from. Configure the output interrupt type and polarity and enable the global interrupt mask by writing to the INT_CTRL. Wait for interrupt. Upon receiving an interrupt, the INT pin is asserted. The host comes to read the INT_STA register through the I2C interface. A ‘1’ in the INT_STA bits indicates that the corresponding interrupt source is triggered. If the IS8 bit in INT_STA register is set, the interrupt is coming from the GPIO controller. Then, a subsequent read is performed on the INT_STA_GPIO register to obtain the interrupt status of all 16 GPIOs to locate the GPIO that triggers the interrupt. This is a feature so-called ‘Hot Key’. After obtaining the interrupt source that triggers the interrupt, the host performs the necessary processing and operations related to the interrupt source. If the interrupt source is from the GPIO Controller, two write operations with value of ‘1’ are performed to the ISG[x] bit (INT_STA_GPIO) and the IS[8] (ISR) to clear the corresponding GPIO interrupt. If the interrupt source is from other module, a write operation with value of ‘1’ is performed to the IS[x] (ISR) to clear the corresponding interrupt. Once the interrupt is being cleared, the INT pin will also be de-asserted if the interrupt type is level interrupt. An edge interrupt will only assert a pulse width of 250ns. When the interrupt is no longer required, the IC0 bit in INT_CTRL may be set to ‘0’ to disable the global interrupt mask bit. ● ● ● ● ● 29/61 GPIO controller STMPE1601 10 GPIO controller A total of 16 GPIOs are available in the STMPE1601 port expander IC. Most of the GPIOs are sharing physical pins with some alternate functions. The GPIO controller contains the registers that allow the host system to configure each of the pins into either a GPIO, or one of the alternate functions. Unused GPIOs should be configured as outputs to minimize the power consumption. Table 19. GPIO controller Register name GPIO_SET_MSB GPIO set pin state register 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18-1F GPIO_SET_LSB GPIO_CLR_msb GPIO clear pin state register GPIO_CLR_LSB GP_MP_MSB GPIO monitor pin state register GPIO_MP_LSB GPIO_SET_DIR_MSB GPIO set pin direction register GPIO_SET_DIR_LSB GPIO_ED_MSB GPIO_ED_LSB GPIO_RE_MSB GPIO rising edge register GPIO_RE_LSB GPIO_FE_MSB GPIO falling edge register GPIO_FE_LSB GPIO_PULL_UP_MS B GPIO_PULL_UP_LSB GPIO_AF_U_MSB GPIO_AF_U_MSB GPIO_AF_L_MSB GPIO_AF_L_LSB GPIO_LT_EN GPIO_LT_DIR RESERVED GPIO alternate function register (upper word) GPIO alternate function register (lower word) GPIO level translator enable GPIO level translator direction Reserved Yes Yes GPIO pull up register Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes GPIO edge detect status register Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Description Auto-increment (during sequential R/W) Yes Offset address 0x02 30/61 STMPE1601 GPIO controller 10.1 GPIO control registers A group of registers is used to control the exact function of each of the 16 GPIOs. All the GPIO registers are named as GPxxx_yyy, where: – – – – Table 20. Xxx represents the functional group Yyy represents the byte position of the GPIO Lsb registers control GPIO[7:0] Msb registers control GPIO[8:15] Bit description 7 GPxxx_msb GPxxx_lsb IO-15 IO-7 6 IO-14 IO-6 5 IO-13 IO-5 4 IO-12 IO-4 3 IO-11 IO-3 2 IO-10 IO-2 1 IO-9 IO-1 0 IO-8 IO-0 The function of each bit is shown in the following table: Table 21. Register description Function Reading this bit yields the current state of the bit. Writing has no effect. Writing ‘1’ to this bit causes the corresponding GPIO to go to ‘1’ state. Writing ‘0’ has no effect. Writing ‘1’ to this bit causes the corresponding GPIO to go to ‘0’ state. Writing ‘0’ has no effect. ‘0’ sets the corresponding GPIO to input state, and ‘1’ sets it to output state Set to ‘1’ by hardware when there is a rising/falling edge on the corresponding GPIO. Writing ‘1’ clears the bit. Writing ‘0’ has no effect. Set to ‘1’ to enable rising edge detection on the corresponding GPIO. Set to ‘1’ to enable falling edge detection on the corresponding GPIO. Set to ‘1’ to enable internal pull-up resistor Register name GPIO monitor pin state GPIO set pin state GPIO clear pin state GPIO set pin direction GPIO edge detect status GPIO rising edge GPIO falling edge GPIO pull up 31/61 GPIO controller STMPE1601 10.2 GPIO alternate function registers Each GPIO may be configured to one or more functions. A 2-bit field for each GPIO is used for the configuration. Table 22. GPIO alternate function registers ‘00’ for primary function ‘01’ for Alternate Function 1 ‘10’ for Alternate Function 2 ‘11’ - Reserved GPIO alternate function (upper word) GPIO alternate function (lower word) GPIO alternate function registers (upper) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AF[1:0] GPIO-15 AF[1:0] GPIO-14 AF[1:0] GPIO-13 AF[1:0] GPIO-12 AF[1:0] GPIO-11 AF[1:0] GPIO-10 AF[1:0] GPIO-9 AF[1:0] GPIO-8 GPIO alternate function registers (lower) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AF[1:0] GPIO-7 AF[1:0] GPIO-6 AF[1:0] GPIO-5 AF[1:0] GPIO-4 AF[1:0] GPIO-3 AF[1:0] GPIO-2 AF[1:0] GPIO-1 AF[1:0] GPIO-0 32/61 STMPE1601 GPIO controller 10.3 Hotkey feature A GPIO is known as ‘Hotkey’ when it is configured to trigger an interruption to the host whenever the GPIO input is being asserted. This feature is applicable in Operational mode (4 MHz clock is present) as well as Sleep mode (32 kHz clock is present). 10.3.1 Programming sequence for Hotkey 1. 2. 3. 4. 5. 6. Configure the GPIO pin into GPIO mode by setting the corresponding bits in the GPAFR. Configure the GPIO pin into input direction by setting the corresponding bit in GPDR. Set the GPRER and GPFER to the desired values to enable the rising edge or falling edge detection. Configure and enable the interrupt controller to allow the interruption to the host. Now, the GPIO expander may be put into Sleep mode if it is desired. Upon any hot-key being asserted, the device will wake up and issue an interrupt to the host. The pin is configured into GPIO mode and as input pin. The global interrupt mask bit is enabled. The corresponding GPIO interrupt mask bit is enabled. Below are the conditions to be fulfilled in order to configure a Hot Key: 1. 2. 3. 10.3.2 Minimum pulse width The minimum pulse width of the assertion of the Hotkey must be at least 62.5 us. Any pulse width less than the stated value may not be registered. 33/61 GPIO controller STMPE1601 10.4 Level translator feature Figure 7. Level translator feature GPIO 0-7 Direction & enable GPIO 8-15 When enabled, the GPIO 0-7 bits are internally mapped to GPIO 8-15 bits. The STMPE1601 becomes an 8-channel level translator where each of the channels may have its direction set individually. As GPIO 0-7 operates from Vcc, and GPIO 8-15 operates from Vio, this allows the 2 groups of GPIO to work as a level translator. Warning: When the level translator feature is enabled, the “Set pin”, “Clear pin” and “Set direction” bits in the corresponding registers will be ignored. However, the “Monitor pin”, “Edge detect”, “Pull-up” features are still available in the GPIOs used as level translator. 34/61 STMPE1601 Basic PWM controller 11 Basic PWM controller The advanced PWM allows complex brightness and blinking control of an LED. The basic PWM controller allows simpler brightness control and basic blinking patterns. The STMPE1601 is fitted with a 4-channel basic PWM controller. Table 23. Address Basic PWM controller Register name Description Set the output level when PWM is disabled Enable/disable individual basic PWM channels PWM_0 brightness and timing setting PWM_0 blinking control Enable use trigger on PWM 0 PWM_1 brightness and timing setting PWM_1 blinking control Enable use trigger on PWM 1 PWM_2 brightness and timing setting PWM_2 blinking control Enable use trigger on PWM 2 PWM_3 brightness and timing setting PWM_3 blinking control Enable use trigger on PWM 3 Auto-increment (during sequential R/W) Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 0x40 0x41 0x50 0x51 0x52 0x54 0x55 0x56 0x58 0x59 0x5A 0x5C 0x5D 0x5E PWM_OFF_OUT CHANNEL_FUNCT_EN PWM_0_SET PWM_0_CTRL PWM_0_TRIGGER PWM_1_SET PWM_1_CTRL PWM_1_TRIGGER PWM_2_SET PWM_2_CTRL PWM_2_TRIGGER PWM_3_SET PWM_3_CTRL PWM_3_TRIGGER 35/61 Basic PWM controller STMPE1601 PWM_OFF_OUTPUT 7 RW 0 6 RW 0 5 RW 0 PWM off output 4 RW 0 3 OUT3 RW 0 2 OUT2 RW 0 1 OUT1 RW 0 0 OUT0 RW 0 Address: Type: Reset: Description: 0x40 R/W 0x00 Set the output level when the PWM is disabled [3:0] OUTPUT3~0: Default is ‘0’ 1: PWM channel outputs ‘1’ when disabled 0: PWM channel outputs ‘0’ when disabled CHANNEL_FUNCT_EN 7 ALT_3 RW 0 6 ALT_2 RW 0 5 ALT_1 RW 0 Channel function enabling 4 ALT_0 RW 0 3 EN_3 RW 0 2 EN_2 RW 0 1 EN_1 RW 0 0 EN_0 RW 0 Address: Type: Reset: Description: 0x41 R/W 0x00 Enable/disable individual basic PWM channels. [7:4] ALT [3:0]: Alternate mode Default is ‘0’ HW writes to ‘1’ if alternate operating feature (one-shot/WDT) is required [3:0] EN [3:0]: PWM channel enable Default is ‘0’ SW writes ‘1’ to start PWM channel HW writes ‘0’ when PWM blinking is completed. SW writes ‘0’ to stop the PWM channel. 36/61 STMPE1601 Basic PWM controller PWM_n_TRIGGER_n = 0 - 3 7 RESET RW 0 6 Edge RW 0 5 RW 0 PWM trigger register n = 0 - 3 4 MODE RW 0 3 RELOAD RW 0 2 GS2 RW 0 1 GS1 RW 0 0 GS0 RW 0 Address: Type: Reset: Description: 0x52, 0x56, 0x5A, 0x5E 0x00 Enable use of trigger on PWM_n. [7] RESET: Always read ‘0’ S/W writes ‘1’ to reset counter in WDT mode Writing ‘1’ in PWM/one-shot has no effect. Writing ‘0’ has no effect in all modes. [6] EDGE:type of logic transition to be detected for trigger source. 0: low-to-high 1: hi-to-low [5] RESERVED [4] MODE: 0: one-shot trigger mode 1: watch-dog timer mode This bit is only valid if the ALT bits in the Channel_function_En register is set to ‘1’. ‘1’ for Manual Reload [3] RELOAD: ‘0’ for Auto-Reload ‘1’ for Manual Reload [2:0] GS2:0: Trigger source select 000: GPIO-4 001: GPIO-5 010: GPIO-6 011: GPIO-7 100: GPIO-9 101: GPIO-10 110: GPIO-11 111: GPIO-12 37/61 Basic PWM controller STMPE1601 PWM_n_SET n=0-3 7 6 Brightness R/W 0 R/W 0 R/W 0 5 PWM_n_Setup n=0-3 4 3 2 Timing R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 1 0 Address: Type: Reset: Description: 0x50, 0x54, 0x58, 0x5C RW 0x00 PWM blinking control and brightness setting. [7:4] BRIGTHNESS: Duty cycle of PWM output during period 0 0000: duty cycle ratio 1:15 ( 6.25%, minimum brightness) 0001: duty cycle ratio 2:14 (12.50%) 0010: duty cycle ratio 3:13 (18.75%) 0011: duty cycle ratio 4:12 (25.00%) 0100: duty cycle ratio 5:11 (31.25%) 0101: duty cycle ratio 6:10 (37.50%) 0110: duty cycle ratio 7: 9 (43.75%) 0111: duty cycle ratio 8: 8 (50.00%) 1000: duty cycle ratio 9: 7 (56.25%) 1001: duty cycle ratio 10: 6 (62.50%) 1010: duty cycle ratio 11: 5 (68.75%) 1011: duty cycle ratio 12: 4 (75.00%) 1100: duty cycle ratio 13: 3 (81.25%) 1101: duty cycle ratio 14: 2 (87.50%) 1110: duty cycle ratio 15: 1 (93.75%) 1111: duty cycle ratio 16: 0 (100.00%, maximum brightness) 38/61 STMPE1601 Basic PWM controller [3:0] TIMING: In PWM mode: time unit of each ON or OFF period In WDT mode: Wait time In one-short mode: pulse width 0000 = 5 mS 0001 = 10 mS 0010 = 20 mS 0011 = 40 mS 0100 = 80 mS 0101 = 160 mS 0110 = 320 mS 0111 = 640 mS 1000 = 1001 = 1010 = 1011 = 1100 = 1101 = 1110 = 1111 = 1280 mS 2560 mS 5120 mS 10 S 20 S 40 S 80 S 160 S 39/61 Basic PWM controller STMPE1601 PWM_n_CTRL_n=0-3 7 Period 0 RW 0 RW 0 RW 0 6 5 PWMn control register n=0-3 4 Period 1 RW 0 RW 0 3 Repetition RW 0 2 1 INT_EN RW 0 0 FRAME RW 0 Address: Type: Reset: Description: 0x51, 0x55, 0x59, 0x5D R/W 0x00 PWM blinking control register [7:6] Period 0: 1-4 time units of period 0 Total length of period 0: (period 0 [1:0] + 1) * TIMING [5:4] Period 1: 0-3 time units of period 1 Total length of period 1: (period 0 [1:0]) * TIMING [3:2] Repetition: Number of repetition 0 for Infinite repetition [1] INT_EN: “0” to disable interrupt generation on completion of sequence “1” to enable interrupt generation on completion of sequence [0] FRAME: ‘0’ will output period 0 first ‘1’ will output period 1 first 40/61 STMPE1601 Basic PWM controller 11.1 Interrupt on basic PWM controller A basic PWM controller can be programmed to generate interrupts at the completion of a blinking sequence. However, there are some limitations: a) b) c) d) Each basic PWM controller has its own bit in the interrupt enable/status registers. If enabled, completion in any of the PWM controller triggers interrupts. No interrupt will be generated if infinite repetition is set. In WDT mode, an interrupt is generated when timeout occurs In One-shot mode If Auto-reload, interrupt is generated every time a valid trigger is detected If Non-auto-reload, an interrupt is generated just once 11.2 Trigger feature The basic PWM controller can be programmed to be controlled by an external “trigger” signal. This feature can be used to implement: – – One-shot trigger circuit Watchdog timer In one-shot trigger mode, a single pulse which the length is defined by TIMING[3:0] is sent to the PWM output, when a level transition is detected at the trigger source. In watchdog mode, a 120 μS pulse is generated at PWM output when the programmed timer has elapsed without getting any trigger for the trigger source. 41/61 Keypad controller STMPE1601 12 Keypad controller The keypad controller consists of: – – – 4 dedicated key controllers that support up to 4 simultaneous dedicated key presses; a keyscan controller support a maximum of 8 x 8 key matrix with detection of three simultaneous key presses; 8 special function key controllers that support up to 8 simultaneous “special function” key presses. Four of the column inputs can be configured as dedicated keys through the setting of Dkey0~3 bits of the KPC_CTRL register. The normal key matrix size can be configured through the setting of KPC_ROW and KPC_COL registers. The scanning of each individual row output and column input can be enabled or masked to support a key matrix of variable size from 1 x 1 to 8 x 8. It is allowed to have other 8 special function keys incorporated in the key matrix. The operation of the keypad controller is enabled by the SCAN bit of KPC_CTRL register. Every key activity detected will be de-bounced for a period set by the DB_0~7 bits of KPC_CTRL register before a key press or key release is confirmed and updated into the output FIFO. The key data, indicating the key coordinates and its status (up or down), is loaded into the FIFO at the end of a specified number of scanning cycles (set by SCAN_COUNT0~3 bits of KPC_ROW_MSB register). An interrupt will be generated when a new set of key data is loaded. The FIFO has a capacity for ten sets of key data. Each set of key data consists of 5 bytes of information when any of the four dedicated keys is enabled. It is reduced to 4 bytes when no dedicated key is involved. When the FIFO is full before its content is read, an overflow signal will be generated while the FIFO will continue to hold its content but forbid loading of new key data set. Figure 8. Keypad controller Input 0-7 Keypad Matrix Output 0-7 The keypad column inputs enabled by the KPC_col register are normally 'high', with the corresponding input pins pulled up by resistors internally. After reset, all the keypad row outputs enabled by the KPC_row register are driven 'low'. If a key is pressed, its 42/61 STMPE1601 Keypad controller corresponding column input will become 'low' after making contact with the 'low' voltage on its corresponding row output. Once the keyscan controller senses a 'low' input on any of the column inputs, the scanning cycles will then start to determine the exact key that has been pressed. The twelve row outputs will be driven 'low' one by one during each scanning cycle. While one row is driven 'low', all other rows are in tri-state and pulled up. If there is any column input sensed as 'low' when a row is driven 'low', the key scan controller will then decode the key coordinates (its corresponding row number and column number), save the key data into a de-bounce buffer if available, confirm if it is a valid key press after de-bouncing, and update the key data into output data FIFO if valid. 12.1 Keypad configurations The keypad controller supports the following types of keys: ● ● ● Up to 8 input * 8 output matrix keys Up to 8 special function keys Up to 4 dedicated keys Maximum configuration Figure 9. S TMPE1601 O utput 0-7 M atrix Keypad (8*8) Input 0-7 S pecial Function Keys 8*8 (64) Matrix Keys 8 Special Function Keys 0 Dedicated Key s 43/61 Keypad controller Figure 10. Maximum configuration STMPE1601 Output 0-7 Matrix Keypad (4*8) STMPE1601 Input 0-3 Input 4-7 Dedicated Keys 4*8 (32) Matrix Keys 4 Special Function Keys 4 Dedicated Keys Special Function Keys 44/61 STMPE1601 Keypad controller 12.2 Registers in keypad controller Table 24. Address 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C Registers in keypad controller Register name KPC_COL KPC_ROW_MSB Keypad row scanning register KPC_ROW_LSB KPC_CTRL_MSB Keypad control register KPC_CTRL_LSB KPC_COMBI_KEY_0 KPC_COMBI_KEY_1 KPC_COMBI_KEY_2 KPC_DATA_BYTE0 KPC_DATA_BYTE1 KPC_DATA_BYTE2 KPC_DATA_BYTE3 KPC_DATA_BYTE4 Keypad data register Keypad combination key mask 0 Keypad combination key mask 1 Keypad combination key mask 2 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Description Keypad column scanning register Auto-increment (during sequential R/W) Yes Yes 45/61 Keypad controller STMPE1601 KPC_COL 7 6 5 Keypad colum register 4 Input Column 0 ~ 7 3 2 1 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Address: Type: Reset: Description: 0x60 R/W 0x00 Keypad column scanning [7] INPUT COLUMN: 1: turn on scanning of column 7 0: turn off [6] INPUT COLUMN: 1: turn on scanning of column 6 0: turn off [5] INPUT COLUMN: 1: turn on scanning of column 5 0: turn off [4] INPUT COLUMN: 1: turn on scanning of column 4 0: turn off [3] INPUT COLUMN: 1: turn on scanning of column 3 0: turn off [2] INPUT COLUMN: 1: turn on scanning of column 2 0: turn off [1] INPUT COLUMN: 1: turn on scanning of column 1 0: turn off [0] INPUT COLUMN: 1: turn on scanning of column 0 0: turn off 46/61 STMPE1601 Keypad controller KPC_ROW_MSB 7 SCAN_PW1 R/W 1 6 SCAN_PW0 R/W 1 5 HIB_WK R/W 0 Keypad row MSB 4 R 0 R 0 R 0 3 2 RESERVED R 0 R 0 1 0 Address: Type: Reset: Description: 0x61 R/W, R Keypad row scanning register [7:6] SCAN_PW[1:0]: Row output scanning pulse width setting: 00: 1x period of internal clock 01: 16x period of internal clock 10: 64x period of internal clock 11: 128x period of internal clock (default) (This setting is only applicable during normal operation mode. The scanning pulse width is 1x period of 32 kHz clock during sleep mode.) [5] HIB_WK: 1: to enable the keypad wake-up from hibernate mode 0: to disable [4:0] RESERVED 47/61 Keypad controller STMPE1601 KPC_ROW_lsb 7 6 5 Keypad controller row (LSB) 4 3 2 1 0 OUTPUT ROW 0 ~ 7 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Address: Type: Reset: Description: 0x62 0x00 Keypad row scanning register. [7:0] OUTPUT ROW 0 ~ 7: ‘1’ to turn on scanning of the corresponding row; ‘0’ to turn off KPC_CTRL_msb 7 6 5 SCAN_COUNT_0 ~ 3 RW 0 RW 0 RW 0 Keypad controller control (MSB) 4 3 2 DKEYy_0 ~ 3 RW 0 RW 0 RW 0 RW 0 RW 0 1 0 Address: Type: Reset: Description: 0x63 R/W 0x00 Keypad control register. [7:4] SCAN_COUNT_0~ 3: Number of key scanning cycles elapsed before a confirmed key data is updated into output data FIFO (0 ~ 15 cycles) [3] DKEY_3: Set ‘1’ to use input column 3 as dedicated key [2] DKEY_2: Set ‘1’ to use input column 2 as dedicated key [1] DKEY_1: Set ‘1’ to use input column 1 as dedicated key [0] DKEY_0: Set ‘1’ to use input column 0 as dedicated key 48/61 STMPE1601 Keypad controller KPC_CTRL_lsb 7 6 5 Keypad controller control (LSB) 4 DB[6:0] 3 2 1 0 SCAN R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Address: Type: Reset: Description: 0x64 R/W 0x00 Keypad control register. [7:1] DB_6:0: 0-128 ms of de-bounce time [0] SCAN: 1: to start scanning 0: to stop 49/61 Data registers STMPE1601 13 Data registers The KPC_DATA register contains three bytes of information. The first two bytes store the key coordinates and status of any two keys from the normal key matrix, while the third byte store the status of dedicated keys. KPC_DATA_BYTE0 7 UP/DOWN R 1 6 R3 R 1 5 R2 R 1 Keypad data byte 0 4 R1 R 1 3 R0 R 1 2 C2 R 0 1 C1 R 0 0 C0 R 0 Address: Type: Reset: Description: 0x68 R 0xF8 Keypad data register. [7] UP/DOWN: 0: key-down 1: key-up [6:3] R[3:0] Row number of key 1 (valid range: 0-7) 0x1111: No Key [2:0] C[2:0}: Column number of key 1 (valid range: 0-7) 50/61 STMPE1601 Data registers KPC_DATA_BYTE1 7 Up/Down R 1 6 R3 R 1 5 R2 R 1 Keypad data byte 1 4 R1 R 1 3 R0 R 1 2 C2 R 0 1 C1 R 0 0 C0 R 0 Address: Type: Reset: Description: 0x69 R 0xF8 Keypad data register. [7] UP/DOWN: 0: key-down 1: key-up [6:3] R[3:0] Row number of key 2 (valid range: 0-7) 0x1111: No key [2:0] C[2:0}: Column number of key 1 (valid range: 0-7) 51/61 Data registers STMPE1601 KPC_DATA_BYTE2 7 UP/DOWN R 1 6 R3 R 1 5 R2 R 1 Keypad data byte 2 4 R1 R 1 3 R0 R 1 2 C2 R 0 1 C1 R 0 0 C0 R 0 Address: Type: Reset: Description: 0x6A R 0xF8 Keypad data register. [7] UP/DOWN: 0: key-down 1: key-up [6:3] R[3:0] Row number of key 3 (valid range: 0 - 7) 0x1111: No key [2:0] C[2:0}: column number of key 3 (valid range: 0 -7) 52/61 STMPE1601 Data registers KPC_DATA_BYTE3 7 SF7 R 1 6 SF6 R 1 5 SF5 R 1 Keypad data byte 3 4 SF4 R 1 3 SF3 R 1 2 SF2 R 1 1 SF1 R 1 0 SF0 R 1 Address: Type: Reset: Description: 0x6B R 0xFF Keypad data register. [7:0] SF[7:0]: 0: key-down 1: key-up KPC_DATA_BYTE4 7 6 RESERVED R 0 R 0 R 0 5 Keypad data byte 4 4 3 2 1 0 Dedicated Key 0 ~ 3 R 0 R 1 R 1 R 1 R 1 Address: Type: Reset: Description: 0x6C R Keypad data register. [7:4] RESERVED: [3:0] Dedicated key [3:0]: 0: key-down 1 key-up 53/61 Keypad combination key registers STMPE1601 14 Keypad combination key registers The 3 KPC mask registers contains the key combination to be used to wake up the KPC and send an interrupt to the host system. KPC_COMB_KEY_0-2 7 ACTIVE R/W 1 6 ACTIVE R/W 1 5 R2 R/W 1 Keypad combination 0-2 4 R1 R/W 1 3 R0 R/W 1 2 C2 R/W 0 1 C1 R/W 0 0 C0 R/W 0 Address: Type: Reset: Description: 0x65, 0x66, 0x67 R/W 0xF8 Keypad combination key mask registers. [7:6] ACTIVE: 00: key defined by bits 5:0 to be used for combination key wakeup But [7:0] must be “F8” for No key from this register to be used for combination key wakeup [5:3] R[2:0]: Row number of key 1 (valid range: 0 -7) [2:0] C[2:0]: Column number of key 1 (valid range : 0-7) 54/61 STMPE1601 Keypad combination key registers Resistance The maximum resistance between keypad outputs and inputs, inclusive of switch resistance, protection circuit resistance and connection, must be less than 3.2 KΩ Using the keypad controller It is not necessary to explicitly enable the internal pull-up and direction by configuring the GPIO control registers. Once a GPIO is enabled for the keypad function, its internal pull-up and direction is controlled automatically. The scanning of column inputs should then be enabled for those GPIO ports that are configured as keypad inputs by writing '1's to the corresponding bits in the KPC_COL register. If any of the first three column inputs is to be used as dedicated key input, the corresponding bits in the KPC_CTRL_MSB register should be set to '1'. The bits in the KPC_ROW_MSB and KPC_ROW_LSB registers should also be set correctly to enable the row output scanning for the corresponding GPIO ports programmed as keypad outputs. The scan count and de-bounce count should also be programmed into the keypad control registers before enabling the keypad controller operation. To enable the keypad controller operation, the EN_KPC bit in the system control register must be set to '1' to provide the required clock signals. The keypad controller will then start its operation by setting the SCAN bit in the KPC_CTRL_LSB register to '1'. The keypad controller operation can be disabled by setting the SCAN bit back to '0'. To further reduce the power consumption, the clock signals can be cut off from the keypad controller by setting the EN_KPC bit to '0'. As long as there is any un-read key-press in the keypad controller buffer, the KPC interrupt will always be asserted. Ghost key handling The ghost key is an inherent in keypad matrix that is not equipped with a diode at each of the keys. While it is not possible to avoid ghost key occurrence, the STMPE1601 allows the detection of possible ghost keys by the capability of detecting 3 simultaneous key-presses in the key matrix. The ghost key is only possible if 3 keys are pressed and held down together in a keypad matrix. If 3 keys are reported by the STMPE1601 keypad controller, it indicates a potential ghost key situation. The system may check for the possibility of a ghost key by analyzing the coordinates of the 3 keys. If the 3 keys form 3 corners of a rectangle, it could be a ghost key situation. A ghost key may also occur in the “special function keys”. The keypad controller does not attempt to avoid the occurrence of ghost keys. However, the system should be aware that if more than one special function key is reported, then there is a possibility of ghost keys. Key detection priority A dedicated key is always detected, if this is enabled. When a special function key is detected, the matrix key scanning on the same input line is disabled. Up to 3 matrix keys can be detected. Matrix keys that fall on activated special function keys will not be counted. As a result of these priority rules, a matrix key is ignored by the keypad controller when the special function key on the same input line is detected, even if the matrix key is being 55/61 Keypad combination key registers STMPE1601 pressed down before the special function key. Hence, when a matrix is reported "key-down" and it is being held down while the corresponding special function is being pressed, a "nokey" status will be reported for the matrix key when the special function key is reported "keydown". If the matrix key is released while the special function key is still being held down, no "key-up" will be reported for the matrix key. On the other hand, if the matrix key is released after the special function key is reported "key-up", then a new "key-down" will be reported for the matrix key, followed by "key-up". Keypad wakeup from sleep and hibernate modes The keypad controller is functional in sleep mode as long as it is enabled before entering the sleep mode. It will then wake the system up into operational mode if a valid key press is detected. In the case of hibernate mode, the 'HIB_WK' bit in 'KPC_ROW_msb' register must be set to '1' in order to enable the system wakeup by means of a valid key press. When this is enabled, an asynchronous detection of the keypad column input activity is turned on during the hibernate mode. If any key activity is detected, the system is expected to enter the sleep mode temporarily to allow a debouncing of key press to take place. If a valid key is detected, the system will then wake up into operational mode; otherwise, the device will go back into hibernate mode. Keypad controller combination-Key interrupt The keypad controller (KPC) can be programmed to wake up from sleep mode if a unique combination keys is detected. This combination keys of up to 3 keys is specified in the KPC combination set 0-2 registers. Note that the sequence of the key press is not relevant, as long as the 1-3 keys specified in the KPC_CombiKey are detected, the KPC will wake up and interrupt the host. If any other keys (beside those specified in the KPC_CombiKey registers) are pressed, it would be considered invalid combination and interrupt will NOT be generated. All the "active" keys must be pressed and held together, for the combi-key interrupt to be generated. 56/61 STMPE1601 Miscellaneous features 15 15.1 Miscellaneous features Reset The STMPE1601 is equipped with an internal POR circuit that holds the device in reset state, until the clock is steady and VCC input is valid. The host system may choose to reset the STMPE1601 by asserting the RESET_N pin. 15.2 Under voltage lockout The STMPE1601 is equipped with an internal UVLO (under voltage lockout) circuit that generates a RESET signal, when the main supply voltage falls below the allowed threshold. 57/61 Package mechanical data STMPE1601 16 Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com Figure 11. TFBGA25 package outline Table 25. Dim. TFBGA25 mechanical data mm. Min Typ 1.1 Max 1.16 0.25 0.78 0.25 2.9 2.9 0.30 3.0 2 3.0 2 0.5 0.25 3.1 114.2 0.86 0.35 3.1 30.7 9.8 114.2 11.8 118.1 78.8 118.1 78.8 19.7 9.8 122.0 Min 39.4 inch Typ 43.3 Max 45.7 9.8 33.9 13.8 122.0 A A1 A2 b D D1 E E1 e SE 1.0 58/61 STMPE1601 Figure 12. Tape and reel dimension Package mechanical data Table 26. Symbol TFBGA25 tape and reel mechanical data millimeters Min Typ Max 330 12.8 20.2 60 14.4 3.3 3.3 1.60 3.9 7.9 4.1 8.1 0.153 0.311 0.130 0.130 0.063 0.161 0.319 13.2 0.504 0.795 2.362 0.567 Min inches Typ Max 12.992 0.519 A C D N T Ao Bo Ko Po P 59/61 Revision history STMPE1601 17 Revision history Table 27. Date 10-Jan-2008 Document revision history Revision 1 Initial release. Modified Figure 1 on page 4, added info on register Description: on page 40 and Section 6.1: Minimizing current drain on I2C address lines on page 13, updated Table 7: DC electrical characteristics on page 9, minor text changes. Updated Table 7: DC electrical characteristics on page 9 Document status promoted from preliminary data to datasheet. Modified: Figure 1 on page 4, Rup values in Table 10, Channel function enabling and PWM trigger register n = 0 - 3 registers. Updated: Section 6: I2C interface, Section 7: System controller, Section 9: Interrupt system, Section 10: GPIO controller, Section 11: Basic PWM controller, Section 12: Keypad controller Changes 15-Feb-2008 2 14-Mar-2008 3 02-June-2008 4 60/61 STMPE1601 Please Read Carefully: Information in this document is provided solely in connection with ST products. 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