STP315N10F7

STP315N10F7 Automotive-grade N-channel 100 V, 2.3 mΩ typ., 180 A STripFET™ F7 Power MOSFET in a TO-220 package Datasheet - production data Features Order code VDS RDS(on)max ID STP315N10F7 100 V 2.7 mΩ 180 A Features      Designed for automotive applications and AEC-Q101 qualified Among the lowest RDS(on) on the market Excellent FoM (figure of merit) Low Crss/Ciss ratio for EMI immunity High avalanche ruggedness Figure 1: Internal schematic diagram Applications  D(2, TAB) Switching applications Description This N-channel Power MOSFET utilizes STripFET™ F7 technology with an enhanced trench gate structure that results in very low onstate resistance, while also reducing internal capacitance and gate charge for faster and more efficient switching. G(1) S(3) AM01475v1_Tab Table 1: Device summary Order code Marking Package Packaging STP315N10F7 315N10F7 TO-220 Tube August 2016 DocID025348 Rev 4 This is information on a product in full production. 1/13 www.st.com Contents STP315N10F7 Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ..................................................................................... 8 4 Package information data ............................................................... 9 4.1 5 2/13 TO-220 type A package information................................................ 10 Revision history ............................................................................ 12 DocID025348 Rev 4 STP315N10F7 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage 100 V VGS Gate-source voltage ±20 V ID(1) Drain current (continuous) at TC = 25 °C 180 A ID(1) Drain current (continuous) at TC = 100 °C 120 A IDM(2) Drain current (pulsed) 720 A PTOT Total dissipation at TC = 25 °C 315 W EAS(3) Single pulse avalanche energy (TJ = 25 °C, L=0.55 mH, IAS=65 A) 1 J -55 to 175 °C TJ Operating junction temperature range Tstg Storage temperature range Notes: (1)Current (2)Pulse limited by package. width limited by safe operating area. (3)Starting TJ=25°C, ID=60 A, VDD=50 V. Table 3: Thermal data Symbol Parameter Value Unit Rthj-case Thermal resistance junction-case 0.48 °C/W Rthj-amb Thermal resistance junction-ambient 62.5 °C/W DocID025348 Rev 4 3/13 Electrical characteristics 2 STP315N10F7 Electrical characteristics (TC = 25 °C unless otherwise specified) Table 4: On /off states Symbol V(BR)DSS Parameter Test conditions VGS = 0 V, ID= 250 μA Drain-source breakdown voltage Min. Typ. Max. Unit V 100 VGS= 0 V, VDS= 100 V 1 µA VGS= 0 V, VDS= 100 V, TC= 125 °C (1) 100 µA Gate-body leakage current VDS = 0 V, VGS = 20 V 100 nA VGS(th) Gate threshold voltage VDS = VGS, ID = 250 μA 3.5 4.5 V RDS(on) Static drain-source on-resistance VGS = 10 V, ID = 60 A 2.3 2.7 mΩ Min. Typ. Max. Unit - 12800 - pF - 3500 - pF - 170 - pF - 180 - nC - 78 - nC - 34 - nC Min. Typ. Max. Unit - 62 - ns - 108 - ns - 148 - ns - 40 - ns IDSS IGSS Zero gate voltage drain current 2.5 Notes: (1)Defined by design, not subject to production test. Table 5: Dynamic Symbol Parameter Test conditions Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Qg Total gate charge Qgs Gate-source charge Qgd Gate-drain charge VGS = 0 V, VDS= 25 V, f = 1 MHz VDD = 50 V, ID = 180 A, VGS = 10 V (see Figure 14: "Test circuit for gate charge behavior") Table 6: Switching times Symbol td(on) Turn-on delay time tr Rise time td(off) Turn-off delay time tf 4/13 Parameter Test conditions VDD = 50V, ID = 90 A, RG = 4.7 Ω, VGS = 10 V (see Figure 13: "Test circuit for resistive load switching times" and Figure 18: "Switching time waveform") Fall time DocID025348 Rev 4 STP315N10F7 Electrical characteristics Table 7: Source-drain diode Symbol Parameter Test conditions Min. Typ. Max. Unit Source-drain current - 180 A ISDM(1) Source-drain current (pulsed) - 720 A VSD(2) Forward on voltage VGS = 0 V, ISD= 60 A - 1.5 V ISD = 180 A, di/dt = 100 A/µs VDD = 80 V, TJ= 150 °C (see Figure 15: "Test circuit for inductive load switching and diode recovery times") - 85 ns - 200 nC - 4.7 A ISD trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current Notes: (1)Pulse width limited by safe operating area. (2)Pulse duration = 300μs, duty cycle 1.5% DocID025348 Rev 4 5/13 Electrical characteristics 2.2 STP315N10F7 Electrical characteristics (curves) Figure 3: Thermal impedance Figure 2: Safe operating area 280tok K ᵟ =0.5 0.2 0.1 10 0.05 -1 0.02 Zth=k Rthj-c ᵟ =tp/ t 0.01 Single pulse tp t -2 10 -5 10 Figure 4: Output characteristics 10 10 -2 10 -1 tp (s) AM14735v1 ID (A) V GS=10V V DS = 2V 350 300 -3 Figure 5: Transfer characteristics AM14734v1 ID (A) 10 -4 8V 7V 250 300 250 200 200 150 150 100 100 6V 50 50 5V 0 0 2 4 6 8 0 V DS(V) Figure 6: Gate charge vs gate-source voltage 0 V DD=50V ID=180 A 10 8 6 4 2 0 0 6/13 50 100 150 2 3 4 5 6 7 8 V GS(V) Figure 7: Static drain-source on-resistance AM14736v1 V GS (V) 1 Q g(nC) DocID025348 Rev 4 STP315N10F7 Electrical characteristics Figure 8: Capacitance variations Figure 9: Normalized on-resistance vs temperature AM14738v1 C (pF) AM14740v1 R DS(on) (norm) 2.0 14000 ID = 60A Ciss 12000 1.6 10000 8000 1.2 6000 4000 0.8 Crss 2000 Coss 0 0 20 60 40 80 0.4 -75 100 V DS(V) Figure 10: Normalized V(BR)DSS vs temperature 0 25 75 125 T J(°C) Figure 11: Normalized gate threshold voltage vs temperature AM14742v1 V (BR)DSS (norm) -25 AM14741v1 V GS(th) (norm) ID = 1m A ID = 250µ A 1.04 1.0 1.02 0.90 1.00 0.80 0.98 0.70 0.96 0.94 -75 -25 25 75 125 0.60 -75 T J(°C) -25 0 25 75 125 T J(°C) Figure 12: Source-drain diode forward characteristics AM14739v1 V SD (V) 1.05 T J=-50°C 0.95 0.85 T J=25°C 0.75 0.65 T J=150°C 0.55 0.45 0 40 80 DocID025348 Rev 4 120 160 ISD(A) 7/13 Test circuits 3 8/13 STP315N10F7 Test circuits Figure 13: Test circuit for resistive load switching times Figure 14: Test circuit for gate charge behavior Figure 15: Test circuit for inductive load switching and diode recovery times Figure 16: Unclamped inductive load test circuit Figure 17: Unclamped inductive waveform Figure 18: Switching time waveform DocID025348 Rev 4 STP315N10F7 4 Package information data Package information data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. DocID025348 Rev 4 9/13 Package information data 4.1 STP315N10F7 TO-220 type A package information Figure 19: TO-220 type A package outline 10/13 DocID025348 Rev 4 STP315N10F7 Package information data Table 8: TO-220 type A mechanical data mm Dim. Min. Typ. Max. A 4.40 4.60 b 0.61 0.88 b1 1.14 1.55 c 0.48 0.70 D 15.25 15.75 D1 1.27 E 10.00 10.40 e 2.40 2.70 e1 4.95 5.15 F 1.23 1.32 H1 6.20 6.60 J1 2.40 2.72 L 13.00 14.00 L1 3.50 3.93 L20 16.40 L30 28.90 øP 3.75 3.85 Q 2.65 2.95 DocID025348 Rev 4 11/13 Revision history 5 STP315N10F7 Revision history Table 9: Document revision history Date Revision 07-Oct-2013 1 First release. 27-May-2014 2 – Modified: title and Features in cover page – Minor text changes 12-Sep-2014 3 – Modified: title, features and description in cover page. 4 Modified: Table 2: "Absolute maximum ratings" and Table 4: "On /off states" Updated: Section 7.1: "TO-220 type A package information" Minor text changes 29-Aug-2016 12/13 Changes DocID025348 Rev 4 STP315N10F7 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2016 STMicroelectronics – All rights reserved DocID025348 Rev 4 13/13