STP75NS04Z

STP75NS04Z N-channel Clamped - 7mΩ - 80A - TO-220 Fully protected MESH Overlay™ III Power MOSFET General features Type VDSS RDS(on) ID STP75NS04Z Clamped < 11mΩ 80A ■ Low capacitance and gate charge ■ 100% avalanche tested ■ 175°C maximum junction temperature 3 1 2 TO-220 Description This fully clamped MOSFET is produced by using the latest advanced Company’s Mesh Overlay process which is based on a novel strip layout. The inherent benefits of a new technology coupled with the extra clamping capabilities make this product particularly suitable for the harshest operation conditions such as those encoured in power tools. Any other application requiring extra ruggedness is also recommended. Internal schematic diagram Applications ■ Switching application ■ Power tools Order codes Part number Marking Package Packaging STP75NS04Z P75NS04Z TO-220 Tube June 2006 Rev 1 1/12 www.st.com 12 Contents STP75NS04Z Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) ............................. 6 3 Test circuit 4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2/12 ................................................ 8 STP75NS04Z 1 Electrical ratings Electrical ratings Table 1. Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage (VGS = 0) Clamped V VDG Drain-gate voltage (VGS = 0) Clamped V VGS Gate-source voltage Clamped V ID(1) Drain current (continuous) at TC = 25°C 80 A ID Drain current (continuous) at TC = 100°C 63 A IDG Drain gate current (continuos) ±50 mA IGS Gate source current (continuos) ±50 mA IDM(2) Drain current (pulsed) 320 A PTOT Total dissipation at TC = 25°C 110 W Derating factor 0.73 W/°C ±8 kV -55 to 175 °C VESD Tj Tstg Gate-source ESD (HBM-C=100pF, R=1.5KΩ) Operating junction temperature Storage temperature 1. Current limited by wire bonding 2. Pulse with limited by safe operating area Table 2. Thermal data Symbol Parameter Value Unit Rthj-case Thermal resistance junction-case Max 1.36 °C/W Rthj-amb Thermal resistance junction-ambient Max 62.5 °C/W Maximum lead temperature for soldering purpose 300 °C Tl Table 3. Avalanche data Symbol Parameter Value Unit EAS Single pulse avalanche energy (starting Tj=25°C, ID=IAR, VDD=25V) 470 mJ 3/12 Electrical characteristics 2 STP75NS04Z Electrical characteristics (TCASE=25°C unless otherwise specified) Table 4. Symbol On/off states Parameter Test condictions Typ. Max. Unit Drain-source breakdown voltage ID = 1mA, VGS= 0 IDSS Zero gate voltage drain current (VGS = 0) VDS = 16V 1 µA IGSS Gate body leakage current (VDS = 0) VGS = ±10V 2 µA VGSS Gate threshold breakdown voltage IGS= ±100µA 18 VGS(th) Gate threshold voltage VDS= VGS, ID = 250µA 2 RDS(on) Static drain-source on resistance VGS= 10V, ID= 40A V(BR)DSS Table 5. Symbol gfs (1) Ciss Coss Crss Qg Qgs Qgd 33 V V 3 4 V 7 11 mΩ Typ. Max. Unit Dynamic Parameter Forward transconductance Input capacitance Output capacitance Reverse transfer capacitance Total gate charge Gate-source charge Gate-drain charge Test condictions VDS =15V, ID = 15A VDS = 25V, f = 1 MHz, VGS =0 VDD= 20V, ID= 80 A, VGS= 10 V (see Figure 13) 1. Pulsed: pulse duration=300µs, duty cycle 1.5% 4/12 Min. Min. 50 S 1860 628 196 pF pF pF 50 14 16 nC nC nC STP75NS04Z Electrical characteristics Table 6. Symbol td(on) tr td(off) tf Table 7. Symbol ISD ISDM (1) VSD(2) trr Qrr IRRM Switching on/off Parameter Turn-on delay time Rise time Turn-off delay time Fall time Test condictions Min. VDD= 20V, ID = 40A RG= 4.7 Ω, VGS= 10V, (see Figure 12) VDD= 20V, ID = 40A RG= 4.7 Ω, VGS= 10V, (see Figure 12) Typ. Max. Unit 16 248 ns ns 53 85 ns ns Source drain diode Parameter Test condictions Min. Typ. Source-drain current Source-drain current (pulsed) Forward on Voltage ISD=80A, VGS=0 Reverse recovery time Reverse recovery charge Reverse recovery current ISD=80A, di/dt = 100A/µs, VDD=30V, Tj=150°C (see Figure 17) 53 91 3.4 Max. Unit 80 320 A A 1.5 V ns nC A 1. Pulse width limited by safe operating area 2. Pulsed: pulse duration=300µs, duty cycle 1.5% 5/12 Electrical characteristics STP75NS04Z 2.1 Electrical characteristics (curves) Figure 1. Safe operating area Figure 2. Thermal impedance Figure 3. Output characterisics Figure 4. Transfer characteristics Figure 5. Normalized BVDSS vs temperature Figure 6. Static drain-source on resistance 6/12 STP75NS04Z Electrical characteristics Figure 7. Gate charge vs gate-source voltage Figure 8. Figure 9. Normalized gate threshold voltage vs temperature Capacitance variations Figure 10. Normalized on resistance vs temperature Figure 11. Source-drain diode forward characteristics 7/12 Test circuit 3 STP75NS04Z Test circuit Figure 12. Switching times test circuit for resistive load Figure 13. Gate charge test circuit Figure 14. Test circuit for inductive load Figure 15. Unclamped inductive load test switching and diode recovery times circuit Figure 16. Unclamped inductive waveform 8/12 Figure 17. Switching time waveform STP75NS04Z 4 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com 9/12 Package mechanical data STP75NS04Z TO-220 MECHANICAL DATA DIM. mm. MIN. inch MAX. MIN. TYP. MAX. A 4.40 4.60 0.173 0.181 b 0.61 0.88 0.024 0.034 b1 1.15 1.70 0.045 0.066 c 0.49 0.70 0.019 0.027 D 15.25 15.75 0.60 0.620 E 10 10.40 0.393 0.409 e 2.40 2.70 0.094 0.106 e1 4.95 5.15 0.194 0.202 F 1.23 1.32 0.048 0.052 H1 6.20 6.60 0.244 0.256 J1 2.40 2.72 0.094 0.107 0.551 L 13 14 0.511 L1 3.50 3.93 0.137 L20 16.40 L30 10/12 TYP 0.154 0.645 28.90 1.137 øP 3.75 3.85 0.147 0.151 Q 2.65 2.95 0.104 0.116 STP75NS04Z 5 Revision history Revision history Table 8. Revision history Date Revision 06-Jun-2006 1 Changes First release 11/12 STP75NS04Z Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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