STPC® ATLAS
X86 CORE PC COMPATIBLE
SYSTEM-ON-CHIP FOR TERMINALS
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POWERFUL x86 PROCESSOR
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64-BIT SDRAM UMA CONTROLLER
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GRAPHICS CONTROLLER
- VGA & SVGA CRT CONTROLLER
- 135MHz RAMDAC
- ENHANCED 2D GRAPHICS ENGINE
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VIDEO INPUT PORT
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VIDEO PIPELINE
- UP-SCALER
- VIDEO COLOUR SPACE CONVERTER
- CHROMA & COLOUR KEY SUPPORT
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TFT DISPLAY CONTROLLER
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PCI 2.1 MASTER / SLAVE / ARBITER
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ISA MASTER / SLAVE CONTROLLER
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16-BIT LOCAL BUS INTERFACE
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PCMCIA INTERFACE CONTROLLER
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EIDE CONTROLLER
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2 USB HOST HUB INTERFACES
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I/O FEATURES
- PC/AT+ KEYBOARD CONTROLLER
- PS/2 MOUSE CONTROLLER
- 2 SERIAL PORTS
- 1 PARALLEL PORT
- 16 GENERAL PURPOSE I/Os
- I²C INTERFACE
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Logic Diagram
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POWER MANAGEMENT UNIT
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WATCHDOG
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JTAG IEEE1149.1
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Core
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INTEGRATED PERIPHERAL CONTROLLER
- DMA CONTROLLER
- INTERRUPT CONTROLLER
- TIMER / COUNTERS
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Host
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USB
PCI Bus
PMU
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I/Os
PCI
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IDE
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ISA Bus
PCMCIA
LB
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Video
Pipeline
SVGA
CRTC
Local Bus
C Key
K Key
LUT
Cursor
GE I/F
VIP
Monitor
TFT I/F
TFT
Video In
SDRAM
CTRL
Rev. 3
January 2005
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STPC® ATLAS
DESCRIPTION
The STPC Atlas integrates a standard 5th
generation x86 core along with a powerful UMA
graphics/video chipset, support logic including
PCI, ISA, Local Bus, USB, EIDE controllers and
combines them with standard I/O interfaces to
provide a single PC compatible subsystem on a
single device, suitable for all kinds of terminal and
industrial appliances.
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X86 Processor core
Fully static 32-bit 5-stage pipeline, x86
processor fully PC compatible.
Can access up to 4GB of external memory.
8Kbyte unified instruction and data cache
with write back and write through capability.
Parallel processing integral floating point unit,
with automatic power down.
Runs up to 133 MHz (X2).
Fully static design for dynamic clock control.
Low power and system management modes.
Optimized design for 2.5V operation.
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SDRAM Controller
64-bit data bus.
Up to 90MHz SDRAM clock speed.
Integrated system memory, graphic frame
memory and video frame memory.
Supports 8MB up to 128 MB system memory.
Supports 16-Mbit, 64-Mbit and 128-Mbit
SDRAMs.
Supports 8, 16, 32, 64, and 128 MB DIMMs.
Supports buffered, non buffered, and
registered DIMMs
4-line write buffers for CPU to DRAM and PCI
to DRAM cycles.
4-line read prefetch buffers for PCI masters.
Programmable latency
Programmable timing for SDRAM
parameters.
Supports -8, -10, -12, -13, -15 memory parts
Supports memory hole between 1MB and
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8MB for PCI/ISA busses.
32-bit access, Autoprecharge & Power-down
are not supported.
Enhanced 2D Graphics Controller
Supports pixel depths of 8, 16, 24 and 32 bit.
Full BitBLT implementation for all 256 raster
operations defined for Windows.
Supports 4 transparent BLT modes - Bitmap
Transparency, Pattern Transparency, Source
Transparency and Destination Transparency.
Hardware clipping
Fast line draw engine with anti-aliasing.
Supports 4-bit alpha blended font for antialiased text display.
Complete double buffered registers for
pipelined operation.
64-bit wide pipelined architecture running at
90 MHz. Hardware clipping
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CRT Controller
Integrated 135MHz triple RAMDAC allowing
for 1280 x 1024 x 75Hz display.
8-, 16-, 24-bit pixels.
Interlaced or non-interlaced output.
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Video Input port
Accepts video inputs in CCIR 601/656 mode.
Optional 2:1 decimator
Stores captured video in off setting area of
the onboard frame buffer.
HSYNC and B/T generation or lock onto
external video timing source.
Video Pipeline
Two-tap interpolative horizontal filter.
Two-tap interpolative vertical filter.
Color space conversion (RGB to YUV and
YUV to RGB).
Programmable window size.
Chroma and color keying for integrated video
overlay.
STPC® ATLAS
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PCI Controller
Compatible with PCI 2.1 specification.
Integrated PCI arbitration interface. Up to 3
masters can connect directly. External logic
allows for greater than 3 masters.
Translation of PCI cycles to ISA bus.
Translation of ISA master initiated cycle to
PCI.
Support for burst read/write from PCI master.
PCI clock is 1/2, 1/3 or 1/4 Host bus clock.
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ISA master/slave
Generates the ISA clock from either
14.318MHz oscillator clock or PCI clock
Supports programmable extra wait state for
ISA cycles
Supports I/O recovery time for back to back
I/O cycles.
Fast Gate A20 and Fast reset.
Supports the single ROM that C, D, or E.
blocks shares with F block BIOS ROM.
Supports flash ROM.
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TFT Interface
Programmable panel size up to 1024 by 1024
pixels.
Support for VGA and SVGA active matrix TFT
flat panels with 9, 12, 18-bit interface (1 pixel
per clock).
Support for XGA and SXGA active matrix
TFT flat panels with 2 x 9-bit interface (2
pixels per clock).
Programmable image positionning.
Programmable blank space insertion in text
mode.
Programmable horizontal and vertical image
expansion in graphic mode.
One fully programmable PWM (Pulse Width
Modulator) signals to adjust the flat panel
brightness and contrast.
Supports PanelLinkTM high speed serial
transmitter externally for high resolution
panel interface.
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Supports ISA hidden refresh.
Buffered DMA & ISA master cycles to reduce
bandwidth utilization of the PCI and Host
bus.
Local Bus interface
Multiplexed with ISA/DMA interface.
Low latency asynchronous bus
16-bit data bus with word steering capability.
Programmable timing (Host clock granularity)
4 Programmable Flash Chip Select.
8 Programmable I/O Chip Select.
I/O device timing (setup & recovery time)
programmable
Supports 32-bit Flash burst.
2-level hardware key protection for Flash boot
block protection.
Supports 2 banks of 32MB flash devices with
boot block shadowed to 0x000F0000.
Reallocatable Memory space Windows
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EIDE Interface
Supports PIO
Transfer Rates to 22 MBytes/sec
Supports up to 4 IDE devices
Concurrent channel operation (PIO modes) 4 x 32-Bit Buffer FIFOs per channel
Support for PIO mode 3 & 4.
Individual drive timing for all four IDE devices
Supports both legacy & native IDE modes
Supports hard drives larger than 528MB
Support for CD-ROM and tape peripherals
Backward compatibility with IDE (ATA-1).
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Integrated Peripheral Controller
2X8237/AT compatible 7-channel DMA
controller.
2X8259/AT compatible interrupt Controller. 16
interrupt inputs - ISA and PCI.
Three 8254 compatible Timer/Counters.
Co-processor error support logic.
Supports external RTC (Not in Local Bus
Mode).
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STPC® ATLAS
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PCMCIA interface
Support one PCMCIA 68-pin standard PC
Card Socket.
Power Management support.
Support PCMCIA/ATA specifications.
Support I/O PC Card with pulse-mode
interrupts.
USB Interface
USB 1.1 compatible.
Open HCI 1.0 compliant.
User configurable RootHub.
Support for both LowSpeed and HighSpeed
USB devices.
No bi-directionnal or Tri-state busses.
No level sensitive latches.
System Management Interrupt pin support
Hooks for legacy device support.
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Keyboard interface
Fully PC/AT+ compatible
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Mouse interface
Fully PS/2 compatible
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Power Management
Four power saving modes: On, Doze,
Standby, Suspend.
Programmable system activity detector
Supports Intel & Cyrix SMM and APM.
Supports STOPCLK.
Supports IO trap & restart.
Independent peripheral time-out timer to
monitor hard disk, serial & parallel port.
128K SM_RAM address space from 0xA0000
to 0xB0000
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JTAG
Boundary Scan compatible IEEE1149.1.
Scan Chain control.
Bypass register compatible IEEE1149.1.
ID register compatible IEEE1149.1.
RAM BIST control.
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Serial interface
16550 compatible
Programmable word length, stop bits, parity.
16-bit programmable baud rate generator.
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Interrupt generator.
Loop-back mode.
8-bit scratch register.
Two 16-bit FIFOs.
Two DMA handshake lines.
Parallel port
All IEEE Standard 1284 protocols supported:
Compatibility, Nibble, Byte, EPP, and ECP
modes.
16 bytes FIFO for ECP.
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PanelLink is a trademark of SiliconImage, Inc
Table of Contents
1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.1. ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.2. GRAPHICS FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.3. INTERFACES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.4. FEATURE MULTIPLEXING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.5. POWER MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.6. JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.7. CLOCK TREE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.1. INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2. SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.2.1. BASIC CLOCKS AND RESETS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.2. MEMORY INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.3. PCI INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.4. ISA BUS INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.5. PCMCIA INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.6. LOCAL BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.7. IPC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.8. IDE INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.9. MONITOR INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.10. VIDEO INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.11. TFT INTERFACE SIGNALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.12. USB Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.13. SERIAL INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.14. KEYBOARD/MOUSE INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.15. PARALLEL PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.16. MISCELLANEOUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.17. COL_SEL Colour Select. JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3 SIGNAL DETAIL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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3 STRAP OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.1 STRAP OPTION REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
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3.1.1. STRAP REGISTER 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.2 STRAP REGISTER 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.3 HCLK PLL STRAP REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.4. STRAP REGISTER 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.5 CPUCLK/HCKL Deskew Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 TYPICAL STRAP OPTION IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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4 ELECTRICAL SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.1. INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.2. ELECTRICAL CONNECTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.2.1. Power/Ground Connections/Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.2. Unused Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.3. Reserved Designated Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3. ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
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4.3.1. 5V Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.4. DC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
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Table of Contents
4.5. AC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.5.1. Power on sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5.2 RESET sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5.3. SDRAM interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5.4 PCI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5.5 IPC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5.6 Isa interface AC Timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5.7. Local bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5.8 PCMCIA interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5.9 IDE interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5.10 TFT interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5.11 USB interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5.12 KEYBOARD & MOUSE INTERFACES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5.13 IEEE1284 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5.14 JTAG interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1. 516-PIN PACKAGE DIMENSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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5.2. 516-PIN PACKAGE THERMAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
5.3. SOLDERING RECOMMENDATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
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6 DESIGN GUIDELINES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
6.1. TYPICAL APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
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6.1.1. Thin Client . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
6.1.2. Internet Terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
6.2. STPC CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
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6.2.1. Local Bus / ISA bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.2.2. Clock configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.3. ARCHITECTURE RECOMMENDATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
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6.3.1. POWER DecouPling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.2. 14MHz oscillator stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.3. SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.4. PCI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.5. Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.6. IPC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.7. IDE / ISA dynamic demultiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.8. Basic audio using IDE interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.9. VGA interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.10. USB interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.11. Keyboard/Mouse interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.12. Parallel Port interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.13. JTAG interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4. PLACE AND ROUTE RECOMMENDATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
76
76
77
80
81
82
84
84
85
86
87
88
89
89
6.4.1. General recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4.2. PLL Definition and Implimentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4.3. Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.5. CLOCK TOPOLOGY FOR ON-BOARD SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
89
89
91
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6.5.1. PCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
6.5.2. Thermal dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
6/108
Table of Contents
6.6. DEBUG METHODOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.6.1. Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.6.2. Boot sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.6.3. ISA mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.6.4. Local Bus mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.6.5. Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.6.6. PCMCIA mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7 ORDERING DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1. ORDERING CODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
103
103
103
104
104
104
108
108
7.2 AVAILABLE PART NUMBERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
8 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
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STPC® ATLAS
1 GENERAL DESCRIPTION
At the heart of the STPC Atlas is an advanced
processor block that includes a powerful x86
processor core along with a 64-bit SDRAM
controller, advanced 64-bit accelerated graphics
and video controller, a high speed PCI bus
controller and industry standard PC chip set
functions (Interrupt controller, DMA Controller,
Interval timer and ISA bus).
The STPC Atlas has in addition, a TFT output, a
Video Input, an EIDE controller, a Local Bus
interface, PCMCIA and super I/O features
including USB host hub.
1.1. ARCHITECTURE
The STPC Atlas makes use of a tightly coupled
Unified Memory Architecture (UMA), where the
same memory array is used for CPU main memory
and graphics frame-buffer. This means a reduction
in total system memory for system performances
that are equal to that of a comparable frame buffer
and system memory based system, and generally
much better, due to the higher memory bandwidth
allowed by attaching the graphics engine directly
to the 64-bit processor host interface running at
the speed of the processor bus rather than the
traditional PCI bus.
The ‘standard’ PC chipset functions (DMA,
interrupt controller, timers, power management
logic) are integrated together with the x86
processor core; additional low bandwidth functions
such as communication ports are accessed by the
STPC Atlas via an internal ISA bus.
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The PCI bus is the main data communication link
to the STPC Atlas chip. The STPC Atlas translates
appropriate host bus I/O and Memory cycles onto
the PCI bus. It also supports the generation of
Configuration cycles on the PCI bus. The STPC
Atlas, as a PCI bus agent (host bridge class), is
compatible with PCI specification 2.1. The chip-set
also implements the PCI mandatory header
registers in Type 0 PCI configuration space for
easy porting of PCI aware system BIOS. The
device contains a PCI arbitration function for three
external PCI devices.
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Figure 1-1 describes this architecture.
8/108
1
Graphics functions are controlled through the onchip SVGA controller and the monitor display is
produced through the 2D graphics display engine.
This Graphics Engine is tuned to work with the
host CPU to provide a balanced graphics system
with a low silicon area cost. It performs limited
graphics drawing operations which include
hardware acceleration of text, bitblts, transparent
blts and fills. The results of these operations
change the contents of the on-screen or off-screen
frame buffer areas of SDRAM memory. The frame
buffer can occupy a space up to 4 Mbytes
anywhere in the physical main memory.
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The maximum graphics resolution supported is
1280 x 1024 in 16 Million colours at 75 Hz refresh
rate and is VGA and SVGA compatible. Horizontal
timing fields are VGA compatible while the vertical
fields are extended by one bit to accommodate
above display resolution.
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To generate the TFT output, the STPC Atlas
extracts the digital video stream before the
RAMDAC and reformats it to the TFT format. The
height and width of the flat panel are
programmable.
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The 64-bit wide memory array provides the system
with an 800MB/s peak bandwidth. This allows for
higher resolution screens and greater color depth.
The processor bus runs at 133 MHz, further
increasing “standard” bandwidth by at least a
factor of two.
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1.2. GRAPHICS FEATURES
1.3. INTERFACES
An industry standard EIDE (ATA 2) controller is
built in to the STPC Atlas and connected internally
via the PCI bus.
The STPC Atlas integrates two USB ports.
Universal Serial Bus (USB) is a general purpose
communications
interface
for
connecting
peripherals to a PC. The USB Open Host
Controller Interface (Open HCI) Specification,
revision 1.1, supports speeds of up to 12 MB/s.
USB is royalty free and is likely to replace lowspeed legacy serial, parallel, keyboard, mouse
and floppy drive interfaces. USB Revision 1.1 is
fully supported under Microsoft Windows 98 and
Windows 2000.
The STPC Atlas PCMCIA controller has been
specifically designed to provide the interface with
PCMCIA cards which contain additional memory
or I/O
The power management control facilities include
socket power control, insertion/removal capability,
power saving with Windows inactivity, NCS
controlled Chip Power Down, together with further
STPC® ATLAS
controls for 3.3V suspend with Modem Ring
Resume Detection.
The STPC Atlas implements a multi-function
parallel port. The standard PC/AT compatible
logical address assignments for LPT1, LPT2 and
LPT3 are supported. It can be configured for any
of the following three modes and supports the
IEEE Standard 1284 parallel interface protocol
standards, as follows:
- Compatibility Mode (Forward channel, standard)
- Nibble Mode (Reverse channel, PC compatible)
- Byte Mode (Reverse channel, PS/2 compatible)
The General Purpose Input/Output (GPIO)
interface provides a 16-bit I/O facility, using 16
dedicated device pins. It is organised using two
blocks of 8-bit Registers, one for lines 0 to 7, the
other for lines 8 to 15.
Each GPIO port can be configured as an input or
an output simply by programming the associated
port direction control register. All GPIO ports are
configured as inputs at reset, which also latches
the input levels into the Strap Registers. The input
states of the ports are thus recorded automatically at reset, and this can be used as a strap
register anywhere in the system.
1.4. FEATURE MULTIPLEXING
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There 3 multiplexed functions are the external ISA
bus, the Local Bus and the PCMCIA interface.
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1.5. POWER MANAGEMENT
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The STPC Atlas core is compliant with the
Advanced
Power
Management
(APM)
specification to provide a standard method by
which the BIOS can control the power used by
personal computers. The Power Management Unit
(PMU) module controls the power consumption,
providing a comprehensive set of features that
controls the power usage and supports
compliance with the United States Environmental
Protection Agency's Energy Star Computer
Program. The PMU provides the following
hardware structures to assist the software in
managing the system power consumption:
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- 3 power-down timers detecting system inactivity:
- Doze timer (short durations).
- Stand-by timer (medium durations).
- Suspend timer (long durations).
- House-keeping activity detection.
- House-keeping timer to cope with short bursts of
house-keeping activity while dozing or in stand-by
state.
- Peripheral activity detection.
- Peripheral timer detecting peripheral inactivity
- SUSP# modulation to adjust the system
performance in various power down states of the
system including full power-on state.
- Power control outputs to disable power from
different planes of the board.
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Lack of system activity for progressively longer
periods of time is detected by the three power
down timers. These timers can generate SMI
interrupts to CPU so that the SMM software can
put the system in decreasing states of power
consumption. Alternatively, system activity in a
power down state can generate an SMI interrupt to
allow the software to bring the system back up to
full power-on state. The chip-set supports up to
three power down states described above; these
correspond to decreasing levels of power savings.
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The STPC Atlas BGA package has 516 balls. This
however is not sufficient for all of the integrated
functions available; some features therefore share
the same balls and cannot thus be used at the
same time. The STPC Atlas configuration is done
by ‘strap options’. This is a set of pull-up or pulldown resistors on the memory data bus, checked
on reset, which auto-configure the STPC Atlas.
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- System Activity Detection.
Power down puts the STPC Atlas into suspend
mode. The processor completes execution of the
current instruction, any pending decoded
instructions and associated bus cycles. During the
suspend mode, internal clocks are stopped.
Removing power-down, the processor resumes
instruction fetching and begins execution in the
instruction stream at the point it had stopped.
Because of the static nature of the core, no
internal data is lost.
1.6. JTAG
JTAG stands for Joint Test Action Group and is the
popular name for IEEE Std. 1149.1, Standard Test
Access Port and Boundary-Scan Architec-ture.
This built-in circuitry is used to assist in the test,
maintenance and support of functional circuit
blocks. The circuitry includes a standard interface
through which instructions and test data are
communicated. A set of test features is defined,
including a boundary-scan register so that a
component is able to respond to a minimum set of
test instructions.
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1
STPC® ATLAS
Figure 1-1. Functional description.
Host
I/F
x86
Core
USB
PCI Bus
PCI
m/s
PMU
IPC
ISA
m/s
I/Os
IDE
I/F
PCI
m/s
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ISA Bus
PCMCIA
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CTRL
Video
Pipeline
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Local Bus
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C Key
K Key
LUT
Monitor
SVGA
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SDRAM
CTRL
CRTC
Cursor
GE I/F
VIP
TFT
TFT I/F
Video In
JTAG
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STPC® ATLAS
The speed of the PLLs is either fixed (DEVCLK),
either programmable by strap option (HCLK)
either programmable by software (DCLK, MCLK).
When in synchronized mode, MCLK speed is fixed
to HCLKO speed and HCLKI is generated from
MCLKI.
1.7. CLOCK TREE
The STPC Atlas integrates many features and
generates all its clocks from a single 14MHz
oscillator. This results in multiple clock domains as
described in Figure 1-2.
Figure 1-2. STPC Atlas clock architecture
MCLKO
VCLK
MCLKI
DCLK
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SDRAM controller
CRTC,Video,TFT
GE, LDE, AFE
48MHz
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PLL
DCLK
PLL
MCLK
PLL
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HCLKI
CPU
IPC
1/4
HCLKO
x2
PCMCIA
UARTs
1/26
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HCLK
PLL
du
North Bridge
Host
Kbd/Mouse
Local Bus
South Bridge
PWM
1/2
1/3
// Port
bs
1/2
1/4
O
DEVCLK
(24MHz)
XTALO
XTALI
OSC14M
(14MHz)
ISACLK
PCICLKI
HCLK
PCICLKO
14.31818 MHz
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1
STPC® ATLAS
Figure 1-3. Typical ISA-based Application.
RTC
5V tolerant
Flash
Boot
EIDE
USB
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ISA
ROMCS#
IRQ
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SDRAM
1
oSVGA
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TFT
2 Serial Ports
Keyboard
Parallel Port
Mouse
VIP
16 GPIOs
PCI
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STPC® ATLAS
Figure 1-4. Typical PCMCIA-based Application.
5V tolerant
EIDE
Flash
Boot
USB
PCMCIA
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ROMCS#
STPC Atlas
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2 Serial Ports
Keyboard
Parallel Port
Mouse
VIP
16 GPIOs
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STPC® ATLAS
Figure 1-5. Typical Local-Bus-based Application.
RTC
Flash
Boot
EIDE
USB
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Local Bus
IRQ
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SDRAM
1
oSVGA
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TFT
2 Serial Ports
Keyboard
Parallel Port
Mouse
VIP
16 GPIOs
PCI
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STPC® ATLAS
2 PIN DESCRIPTION
2.1. INTRODUCTION
The STPC Atlas integrates most of the
functionalities of the PC architecture. Therefore,
many of the traditional interconnections between
the host PC microprocessor and the peripheral
devices are totally internal to the STPC Atlas. This
offers improved performance due to the tight
coupling of the processor core and it’s peripherals.
As a result many of the external pin connections
are made directly to the on-chip peripheral
functions.
Table 2-1 describes the physical implementation
listing signal types and their functionalities. Table
2-2 provides a full pin listing and description.
Table 2-6 provides a full listing of the STPC Atlas
package pin location physical connection. Please
refer to the pin allocation drawing for reference.
Due to the number of pins available for the
package, and the number of functional I/Os, some
pins have several functions, selectable by strap
option on Reset. Table 2-4 provides a summary of
these pins and their functions.
Non multi-functional pins associated with a
particular function are not available for use
elsewhere when that function is disabled. For
Table 2-2. Definition of Signal Pins
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Signal Name
Dir
Buffer Type1
BASIC CLOCKS AND RESETS
SYSRSTI#
I SCHMITT_FT
SYSRSTO#
O BD8STRP_FT
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XTALI
I
XTALO
PCI_CLKI
PCI_CLKO
ISA_CLK,
ISA_CLK2X
OSC14M
HCLK
DEV_CLK
DCLK
VDD_xxx_PLL
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OSCI13B
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I TLCHT_FT
O BT8TRP_TC
O BT8TRP_TC
O
I/O
O
I/O
BD8STRP_FT
BD4STRP_FT
BT8TRP_TC
BD4STRP_FT
example, when in the ISA mode, the Local Bus is
disabled totally and Local Bus pins are set to the
tri-state (high-impedance) condition.
Table 2-1. Signal Description
Group name
Basic Clocks, Reset & Xtal (SYS)
SDRAM Controller (SDRAM)
PCI Controller
ISA Controller
Local Bus I/F
PCMCIA Controller
IDE Controller
VGA Controller (VGA) / I2C
Video Input Port
TFT output
USB Controller
Serial Interface
Keyboard/Mouse Controller
Parallel Port
GPIO Signals
JTAG Signals
Miscellaneous
Grounds
VDD 3.3 V/2.5 V
Reserved
Total Pin Count
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MCLKI
I TLCHT_TC
Memory Clock Input
MCLKO
O BT8TRP_TC
Memory Clock Output
Note1; See Table 2-3 for buffer type descriptions
19
95
51
80
67
62
34
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Description
System Reset / Power good
Reset Output to System
14.31818 MHz Crystal Input
External Oscillator Input
14.31818 MHz Crystal Output
33 MHz PCI Input Clock
33 MHz PCI Output Clock
ISA Clock x1 and x2
Multiplexer Select Line for IPC
ISA bus synchronisation clock
66 MHz Host Clock (Test pin)
24 MHz Peripheral Clock
135 MHz Dot Clock
2.5V Power Supply for PLL Clocks
Qty
100
10
11
24
6
16
4
18
16
5
5
96
36
4
516
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1
1
1
1
1
1
2
1
1
1
1
7
1
1
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STPC® ATLAS
Table 2-2. Definition of Signal Pins
Dir
Buffer Type1
O BD8STRP_TC
Signal Name
CS#[1:0]
CS#[3]/MA[12]/BA[1]
O BD16STARUQP_TC
CS#[2]/MA[11]
O BD16STARUQP_TC
MA[10:0]
BA[0]
RAS#[1:0]
CAS#[1:0]
MWE#
MD[0]
MD[53:1]
MD[63:54]
DQM[7:0]
O
O
O
O
O
I/O
I/O
I/O
O
BD16STARUQP_TC
BD16STARUQP_TC
BD16STARUQP_TC
BD16STARUQP_TC
BD16STARUQP_TC
BD8STRUP_FT
BD8TRP_TC
BD8STRUP_FT
BD8STRP_TC
Description
DIMM Chip Select
DIMM Chip Select
Memory Address
Bank Address
DIMM Chip Select
Memory Address
Memory Row & Column Address
Bank Address
Row Address Strobe
Column Address Strobe
Write Enable
Memory Data
Memory Data
Memory Data
Data Input/Ouput Mask
PCI INTERFACE
AD[31:0]
CBE[3:0]
FRAME#
TRDY#
IRDY#
STOP#
DEVSEL#
PAR
PERR#
SERR#
LOCK#
PCI_REQ#[2:0]
PCI_GNT#[2:0]
PCI_INT#[3:0]
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
I
I
O
I
BD8PCIARP_FT
BD8PCIARP_FT
BD8PCIARP_FT
BD8PCIARP_FT
BD8PCIARP_FT
BD8PCIARP_FT
BD8PCIARP_FT
BD8PCIARP_FT
BD8PCIARP_FT
BD8PCIARP_FT
TLCHT_FT
BD8PCIARP_FT
BD8PCIARP_FT
BD4STRUP_FT
Address / Data
Bus Commands / Byte Enables
Cycle Frame
Target Ready
Initiator Ready
Stop Transaction
Device Select
Parity Signal Transactions
Parity Error
System Error
PCI Lock
PCI Request
PCI Grant
PCI Interrupt Request
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Unlatched Address Bus
Latched Address Bus
Data Bus
I/O Channel Ready
Address Latch Enable
System Bus High Enable
Memory Read & Write
System Memory Read and Write
I/O Read and Write
Add On Card Owns Bus
Memory Chip Select 16
I/O Chip Select 16
Refresh Cycle
Address Enable
I/O Channel Check (ISA)
RTC Read / Write#
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ISA BUS INTERFACE
LA[23:17]
O BD8STRUP_FT
SA[19:0]
O BD8STRUP_FT
SD[15:0]
I/O BD8STRP_FT
IOCHRDY
I BD8STRUP_FT
ALE
O BD4STRP_FT
BHE#
O BD8STRUP_FT
MEMR#, MEMW#
I/O BD8STRUP_FT
SMEMR#, SMEMW# O BD8STRP_FT
IOR#, IOW#
I/O BD8STRUP_FT
MASTER#
I BD4STRUP_FT
MCS16#
I BD4STRUP_FT
IOCS16#
I BD4STRUP_FT
REF#
I BD8STRP_FT
AEN
O BD8STRUP_FT
IOCHCK#
I BD4STRUP_FT
RTCRW#
O BD4STRP_FT
Note1; See Table 2-3 for buffer type descriptions
Qty
2
)
s
t(
11
1
2
2
1
1
53
10
8
32
4
1
1
1
1
1
1
1
1
1
3
3
4
7
20
16
1
1
1
2
2
2
1
1
1
1
1
1
1
STPC® ATLAS
Table 2-2. Definition of Signal Pins
Signal Name
RTCDS#
RTCAS
RMRTCCS#
GPIOCS#
IRQ_MUX[3:0]
DACK_ENC[2:0]
DREQ_MUX[1:0]
TC
ISAOE#
KBCS#
ZWS#
Dir
O
O
O
I/O
I
O
I
O
I
I/O
I
Buffer Type1
BD4STRP_FT
BD4STRP_FT
BD4STRP_FT
BD4STRP_FT
BD4STRP_FT
BD4STRP_FT
BD4STRP_FT
BD4STRP_FT
BD4STRP_FT
BD4STRP_FT
BD4STRP_FT
Description
RTC Data Strobe
RTC Address Strobe
ROM / RTC Chip Select
General Purpose Chip Select
Multiplexed Interrupt Request
DMA Acknowledge
Multiplexed DMA Request
ISA Terminal Count
ISA (0) / IDE (1) SELECTION
External Keyboard CHIP SELECT
ZERO WAIT STATE
Qty
1
1
1
1
4
3
2
1
1
1
1
PCMCIA INTERFACE
RESET
A[23:0]
D[15:0]
IORD#, IOWR#
O
O
I/O
O
BD8STRP_FT
BD8STRUP_FT
BD8STRP_FT
BD8STRUP_FT
1
24
16
2
WP / IOIS16#
I
BD4STRUP_FT
BVD2, BVD1
READY# / IREQ#
WAIT#
OE#
WE#
REG#
CD2#, CD1#
CE2#, CE1#
VCC5_EN
VCC3_EN
VPP_PGM
VPP_VCC
GPI#
I
I
I
O
O
O
I
O
O
O
O
O
I
BD4STRUP_FT
BD4STRUP_FT
BD8STRUP_FT
BD8STRUP_FT
BD4STRP_FT
BD4STRUP_FT
BD4STRUP_FT
BD4STRP_FT
BD4STRP_FT
BD8STRP_FT
BD8STRP_FT
BD4STRP_FT
BD4STRP_FT
Reset
Address Bus
Data Bus
I/O Read and Write
DMA Request // Write Protect
I/O Size is 16 bit
Battery Voltage Detect
Busy / Ready# // Interrupt Request
Wait
Output Enable // DMA Terminal Count
Write Enable // DMA Terminal Count
DMA Acknowledge // Register
Card Detect
Card Enable
Power Switch control: 5 V power
Power Switch control: 3.3 V power
Power Switch control: Program power
Power Switch control: VCC power
General Purpose Input
)
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LOCAL BUS INTERFACE
PA[24:20,15,9:8,3:0] O BD4STRP_FT
PA[19,11]
O BD8STRP_FT
PA[18:16,14:12,7:4]
O BD8STRUP_FT
PA[10]
O BD4STRUP_FT
PD[15:0]
I/O BD8STRP_FT
PRD#
O BD4STRUP_FT
PWR#
O BD4STRUP_FT
PRDY
I BD8STRUP_FT
IOCS#[7:4]
O BD4STRUP_FT
IOCS#[3]
O BD4STRP_FT
IOCS#[2:0]
O BD8STRUP_FT
PBE#[1]
O BD8STRP_FT
PBE#[0]
O BD4STRUP_FT
FCS0#
O BD4STRP_FT
FCS1#
O BT8TRP_TC
Note1; See Table 2-3 for buffer type descriptions
s
b
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e
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O
-
Address Bus [24:20], [15], [9:8], [3:0]
Address Bus [19], [11]
Address Bus [18:16], [14:12], [7:4]
Address Bus [10]
Data Bus [15:0]
Memory and I/O Read signal
Memory and I/O Write signal
Data Ready
I/O Chip Select
I/O Chip Select
I/O Chip Select
Upper Byte Enable (PD[15:8])
Lower Byte Enable (PD[7:0])
Flash Bank 0 Chip Select
Flash Bank 1 Chip Select
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1
2
1
1
1
1
1
2
2
1
1
1
1
1
12
2
10
1
16
1
1
1
4
1
3
1
1
1
1
17/108
1
STPC® ATLAS
Table 2-2. Definition of Signal Pins
Signal Name
FCS_0H#
FCS_0L#
FCS_1H#
FCS_1L#
IRQ_MUX[3:0]1
Dir
O
O
O
O
I/O
Buffer Type1
BD8STRP_FT
BD8STRP_FT
BD8STRP_FT
BD8STRP_FT
BD4STRP_FT
Description
Upper half Bank 0 Flash Chip Select
Lower half Bank 0 Flash Chip Select
Upper half Bank 1 Flash Chip Select
Lower half Bank 1 Flash Chip Select
Muxed Interrupt Lines
Qty
1
1
1
1
4
IDE CONTROLLER
DD[15:12]
DD[11:0]
DA[2:0]
PCS1, PCS3
SCS1, SCS3
DIORDY
PIRQ/SIRQ
PDRQ/SDRQ
PDACK#/SDACK#
PDIOR#/SDIOR#
PDIOW#/SDIOW#
I/O
I/O
O
O
O
O
I
I
O
O
O
BD4STRP_FT
BD8STRUP_FT
BD8STRUP_FT
BD8STRUP_FT
BD8STRUP_FT
BD8STRUP_FT
BD4STRP_FT
BD4STRP_FT
BD8STRP_FT
BD8STRUP_FT
BD8STRP_FT
Data Bus
Data Bus
Address Bus
Primary Chip Selects
Secondary Chip Selects
Data I/O Ready
Primary / Secondary Interrupt Request
Primary / Secondary DMA Request
Primary / Secondary DMA Acknowledge
Primary / Secondary IO Read
Primary / Secondary IO Write
4
12
3
2
2
1
2
2
2
2
2
VGA CONTROLLER
RED, GREEN, BLUE O VDDCO
VSYNC, HSYNC
I/O BD4STRP_FT
VREF_DAC
I ANA
RSET
I ANA
COMP
I ANA
COL_SEL
O BD4STRP_FT
I2C INTERFACE
SCL / DDC[1]
SDA / DDC[0]
TFT INTERFACE
TFTR[5:2]
TFTR[1:0]
TFTG[5:2]
,TFTG[1:0]
TFTB[5:2]
TFTB[1:0]
TFTLINE
TFTFRAME
TFTDE
TFTENVDD,
TFTENVCC
TFTPWM
TFTDCLK
I/O BD4STRUP_FT
I/O BD4STRUP_FT
BD4STRP_TC
BD4STRP_FT
BD4STRP_TC
BD4STRP_FT
BD4STRP_TC
BD4STRP_FT
BD8STRP_TC
BD4STRP_TC
BD4STRP_TC
1
e
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le
o
s
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O
-
I²C Interface - Clock / VGA DDC[1]
I²C Interface - Data / VGA DDC[0]
3
2
1
1
1
1
1
1
Red
Red
Green
Green
Blue
Blue
Horizontal Sync
Vertical Sync
Data Enable
4
2
4
2
4
2
1
1
1
O BD4STRP_TC
Enable Vdd & Vcc of flat panel
2
O BD8STRP_TC
O BT8TRP_TC
PWM back-light control
Dot clock for Flat Panel
1
1
27-33 MHz Video Input Port Clock
Video Input Data Bus
Video Input Odd/even Field
Video Input Horizontal Sync
1
8
1
1
u
d
o
VIDEO INPUT PORT
VCLK
I/O BD8STRP_FT
VIN[7:0]
I BD4STRP_FT
ODD_EVEN#
I/O BD4STRP_FT
VCS
I/O BD4STRP_FT
Note1; See Table 2-3 for buffer type descriptions
18/108
Red, Green, Blue
Vertical & Horizontal Synchronisations
DAC Voltage reference
Resistor Set
Compensation
Colour Select
)
s
(
ct
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t
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l
o
s
b
O
O
O
O
O
O
O
O
O
O
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STPC® ATLAS
Table 2-2. Definition of Signal Pins
Signal Name
Buffer Type1
Dir
USB INTERFACE
OC
USBDPLS[0]1
USBDMNS[0]1
USBDPLS[1]1
USBDMNS[1]1
POWERON1
I
1
I/O USBDS_2V5
Universal Serial Bus Port 0
2
I/O USBDS_2V5
Universal Serial Bus Port 1
2
O BT4CRP
USB power supply lines
1
Clear to send, MSR[4] status bit
Data Carrier detect, MSR[7] status bit
Data set ready, MSR[5] status bit.
Data terminal ready, MSR[0] status bit
Ring indicator, MSR[6] status bit
Request to send, MSR[1] status bit
Receive data, Input Serial Input
Transmit data, Serial Output
2
2
2
2
2
2
2
2
TLCHT_FT
TLCHT_FT
TLCHT_FT
BD4STRP_TC
TLCHT_FT
BD4STRP_TC
TLCHT_FT
BD4STRP_TC
KEYBOARD & MOUSE INTERFACE
KBCLK
I/O BD4STRP_TC
KBDATA
I/O BD4STRP_TC
MCLK
I/O BD4STRP_TC
MDATA
I/O BD4STRP_TC
Keyboard Clock Line
Keyboard Data Line
Mouse Clock Line
Mouse Data Line
PARALLEL PORT
PE
SLCT
BUSY#
ERR#
ACK#
PDIR#
STROBE#
INIT#
AUTOFD#
SLCTIN#
PPD[7:0]
Paper End
SELECT
BUSY
ERROR
Acknowledge
Parallel Device Direction
PCS / STROBE#
INIT
Automatic Line Feed
SELECT IN
Data Bus
s
b
O
JTAG
TCLK
TRST
TDI
TMS
TDO
I
I
I
I
I
O
O
O
O
O
I/O
BD14STARP_FT
BD14STARP_FT
BD14STARP_FT
BD14STARP_FT
BD14STARP_FT
BD14STARP_FT
BD14STARP_FT
BD14STARP_FT
BD14STARP_FT
BD14STARP_FT
BD14STARP_FT
)
s
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ct
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GPIO SIGNALS
GPIO[15:0]
Qty
Over Current Detect
SERIAL CONTROLLER
CTS0#, CTS1#
I
DCD0#, DCD1#
I
DSR0#, DSR1#
I
DTR0#, DTR1#
O
RI0#, RI1#
I
RTS0#, RTS1#
O
RXD0, RXD1
I
TXD0, TXD1
O
TLCHTU_TC
Description
o
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O
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e
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1
1
1
1
1
1
1
1
1
1
1
1
1
1
8
I/O BD4STRP_FT
General Purpose IOs
16
I
I
I
I
O
Test Clock
Test Reset
Test Data Input
Test Mode Set
Test Data output
1
1
TLCHT_FT
TLCHT_FT
TLCHTD_FT
TLCHT_FT
BT8TRP_TC
MISCELLANEOUS
SCAN_ENABLE
I TLCHTD_FT
Test Pin - Reserved
Note1; See Table 2-3 for buffer type descriptions
1
1
1
19/108
1
STPC® ATLAS
Table 2-2. Definition of Signal Pins
Signal Name
Dir
Buffer Type1
Description
SPKRD
O BD4STRP_FT
Speaker Device Output
Note1; See Table 2-3 for buffer type descriptions
Qty
1
Table 2-3. Buffer Type Descriptions
Buffer
ANA
OSCI13B
Analog pad buffer
Oscillator, 13 MHz, HCMOS
Description
BT4CRP
BT8TRP_TC
LVTTL Output, 4 mA drive capability, Tri-State Control
LVTTL Output, 8 mA drive capability, Tri-State Control, Schmitt trigger
BD4STRP_FT
BD4STRUP_FT
BD4STRP_TC
BD8STRP_FT
BD8STRUP_FT
BD8STRP_TC
BD8TRP_TC
BD8PCIARP_FT
BD14STARP_FT
BD16STARUQP_TC
LVTTL Bi-Directional, 4 mA drive capability, Schmitt trigger, 5V tolerant
LVTTL Bi-Directional, 4 mA drive capability, Schmitt trigger, Pull-Up, 5V tolerant
LVTTL Bi-Directional, 4 mA drive capability, Schmitt trigger
LVTTL Bi-Directional, 8 mA drive capability, Schmitt trigger, 5V tolerant
LVTTL Bi-Directional, 8 mA drive capability, Schmitt trigger, Pull-Up, 5V tolerant
LVTTL Bi-Directional, 8 mA drive capability, Schmitt trigger
LVTTL Bi-Directional, 8 mA drive capability, Schmitt trigger
LVTTL Bi-Directional, 8 mA drive capability, PCI compatible, 5V tolerant
LVTTL Bi-Directional, 14 mA drive capability, Schmitt trigger, IEEE1284 compliant, 5V tolerant
LVTTL Bi-Directional, 16 mA drive capability, Schmitt trigger
SCHMITT_FT
TLCHT_FT
TLCHT_TC
TLCHTD_TC
TLCHTU_TC
LVTTL Input, Schmitt trigger, 5V tolerant
LVTTL Input, 5V tolerant
LVTTL Input
LVTTL Input, Pull-Down
LVTTL Input, Pull-Up
USBDS_2V5
USB 1.1 compliant pad buffer
)
s
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ct
Analog output pad
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O
1
u
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P
e
VDDCO
20/108
c
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O
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)
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STPC® ATLAS
2.2. SIGNAL DESCRIPTIONS
2.2.1. BASIC CLOCKS AND RESETS
SYSRSTI# System Reset/Power good. This input
is low when the reset switch is depressed.
Otherwise, it reflects the power supply’s power
good signal. PWGD is asynchronous to all clocks,
and acts as a negative active reset. The reset
circuit initiates a hard reset on the rising edge of
PWGD.
Note that while Reset is being asserted, the
signals on the device pins are in an unknown
state.
SYSRSTO# Reset Output to System. This is the
system reset signal and is used to reset the rest of
the components (not on Host bus) in the system.
The ISA bus reset is an externally inverted
buffered version of this output and the PCI bus
reset is an externally buffered version of this
output.
XTALI 14.3 MHz Crystal Input
XTALO 14.3 MHz Crystal Output. These pins are
provided for the connection of an external 14.318
MHz crystal to provide the reference clock for the
internal frequency synthesizer, from which the
HCLK and CLK24M signals are generated.
DCLK 135 MHz Dot Clock. This is the dot clock,
which drives graphics display cycles. Its frequency
can be as high as 135 MHz, and it is required to
have a worst case duty cycle of 60-40. For further
details, refer to Section 3.1.4. bit 4.
2.2.2. MEMORY INTERFACE
MCLKI Memory Clock Input. This clock is driving
the SDRAM controller, the graphics engine and
display controller. This input should be a buffered
version of the MCLKO signal with the track lengths
between the buffer and the pin matched with the
track lengths between the buffer and the Memory
Banks.
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MCLKO Memory Clock Output. This clock drives
the Memory Banks on board and is generated
from an internal PLL.
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The STPC Atlas MClock signal can run up to
100MHz reliably, but PCB layout is so critical that
the maximum guaranteed speed is 90MHz
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CS#[1:0] Chip Select These signals are used to
disable or enable device operation by masking or
enabling all SDRAM inputs except MCLK, CKE,
and DQM.
o
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O
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PCI_CLKI 33 MHz PCI Input Clock. This signal
must be connected to a clock generator and is
usually connected to PCI_CLKO.
PCI_CLKO 33 MHz PCI Output Clock. This is the
master PCI bus clock output.
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DEV_CLK 24 MHz Peripheral Clock (floppy drive).
This 24 MHz signal is provided as a convenience
for the system integration of a Floppy Disk driver
function in an external chip. This clock signal is not
available in Local Bus mode.
ISA_CLK ISA Clock Output (also Multiplexer
Select Line For IPC). This pin produces the Clock
signal for the ISA bus. It is also used with
ISA_CLK2X as the multiplexer control lines for the
Interrupt Controller Interrupt input lines. This is a
divided down version of the PCICLK or OSC14M.
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ISA_CLKX2 ISA Clock Output (also Multiplexer
Select Line For IPC). This pin produces a signal at
twice the frequency of the ISA bus Clock signal. It
is also used with ISA_CLK as the multiplexer
control lines for the Interrupt Controller Interrupt
input lines.
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CLK14M ISA bus synchronisation clock. This is
the buffered 14.318 MHz clock to the ISA bus.
HCLK Host Clock. This is the host clock. Its
frequency can vary from 25 to 66 MHz. All host
transactions
and
PCI
transactions
are
synchronized to this clock. Host transactions
executed by the DRAM controller are also driven
by this clock.
CS#[2]/MA[11] Chip Select/Bank Address This
pin is CS#[2] in the case when 16-Mbit devices are
used. For all other densities, it becomes MA[11].
CS#[3]/MA[12]/BA[1] Chip Select/ Memory
Address/ Bank Address This pin is CS#[3] in the
case when 16 Mbit devices are used. For all other
densities, it becomes MA[12] when 2 internal
banks devices are used and BA[1] when 4 internal
bank devices are used.
MA[10:0] Memory Address. Multiplexed row and
column address lines.
BA[0] Bank Address. Internal bank address line.
MD[63:0] Memory Data. This is the 64-bit memory
data bus. This bus is also used as input at the
rising edge of SYSRSTI# to latch in power-up
configuration information into the ADPC strap
registers.
RAS#[1:0] Row Address Strobe. There are two
active-low row address strobe output signals. The
RAS# signals drive the memory devices directly
without any external buffering.
21/108
1
STPC® ATLAS
CAS#[1:0] Column Address Strobe. There are two
active-low column address strobe output signals.
The CAS# signals drive the memory devices
directly without any external buffering.
the STPC Atlas is the target of the current PCI
transaction or when no other device asserts
DEVSEL# prior to the subtractive decode phase of
the current PCI transaction.
MWE# Write Enable. Write enable specifies
whether the memory access is a read (MWE# = H)
or a write (MWE# = L). This single write enable
controls all DRAMs. The MWE# signals drive the
memory devices directly without any external
buffering.
PAR Parity Signal Transactions. This is the parity
signal of the PCI bus. This signal is used to
guarantee even parity across AD[31:0],
CBE[3:0]#, and PAR. This signal is driven by the
master during the address phase and data phase
of write transactions. It is driven by the target
during data phase of read transactions. (Its
assertion is identical to that of the AD bus delayed
by one PCI clock cycle)
2.2.3. PCI INTERFACE
AD[31:0] PCI Address/Data. This is the 32-bit
multiplexed address and data bus of the PCI. This
bus is driven by the master during the address
phase and data phase of write transactions. It is
driven by the target during data phase of read
transactions.
PBE[3:0]# Bus Commands/Byte Enables. These
are the multiplexed command and Byte enable
signals of the PCI bus. During the address phase
they define the command and during the data
phase they carry the Byte enable information.
These pins are inputs when a PCI master other
than the STPC Atlas owns the bus and outputs
when the STPC Atlas owns the bus.
FRAME# Cycle Frame. This is the frame signal of
the PCI bus. It is an input when a PCI master owns
the bus and is an output when STPC Atlas owns
the PCI bus.
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IRDY# Initiator Ready. This is the initiator ready
signal of the PCI bus. It is used as an output when
the STPC Atlas initiates a bus cycle on the PCI
bus. It is used as an input during the PCI cycles
targeted to the STPC Atlas to determine when the
current PCI master is ready to complete the
current transaction.
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STOP# Stop Transaction. STOP# is used to
implement the disconnect, retry and abort protocol
of the PCI bus. It is used as an input for the bus
cycles initiated by the STPC Atlas and is used as
an output when a PCI master cycle is targeted to
the STPC Atlas.
DEVSEL# Device Select. This signal is used as an
input when the STPC Atlas initiates a bus cycle on
the PCI bus to determine if a PCI slave device has
decoded itself to be the target of the current
transaction. It is asserted as an output either when
22/108
1
SERR# System Error. This is the system error
signal of the PCI bus. It may, if enabled, be
asserted for one PCI clock cycle if target aborts a
STPC Atlas initiated PCI transaction. Its assertion
by either the STPC Atlas or by another PCI bus
agent will trigger the assertion of NMI to the host
CPU. This is an open drain output.
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LOCK# PCI Lock. This is the lock signal of the PCI
bus and is used to implement the exclusive bus
operations when acting as a PCI target agent.
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PCI_REQ#[2:0] PCI Request. These pins are the
three external PCI master request pins. They
indicates to the PCI arbiter that the external agents
desire use of the bus.
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TRDY# Target Ready. This is the target ready
signal of the PCI bus. It is driven as an output
when the STPC Atlas is the target of the current
bus transaction. It is used as an input when STPC
Atlas initiates a cycle on the PCI bus.
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PERR# Parity Error
PCI_GNT#[2:0] PCI Grant. These pins indicate
that the PCI bus has been granted to the master
requesting it on its PCI_REQ#.
PCI_INT#[3:0] PCI Interrupt Request. These are
the PCI bus interrupt signals. They are to be
encoded before connection to the STPC Atlas
using ISACLK and ISACLKX2 as the input
selection strobes.
2.2.4. ISA BUS INTERFACE
LA[23:17] Unlatched Address. These unlatched
ISA Bus pins address bits 23-17 on 16-bit devices.
When the ISA bus is accessed by any cycle
initiated from the PCI bus, these pins are in output
mode. When an ISA bus master owns the bus,
these pins are tristated.
SA[19:0] Unlatched Address. These are the 20
low bits of the system address bus of ISA. These
pins are used as an input when an ISA bus master
owns the bus and are outputs at all other times.
SD[15:0] I/O Data Bus (ISA). These are the
external ISA databus pins.
STPC® ATLAS
IOCHRDY IO Channel Ready. IOCHRDY is the IO
channel ready signal of the ISA bus and is driven
as an output in response to an ISA master cycle
targeted to the host bus or an internal register of
the STPC Atlas. The STPC Atlas monitors this
signal as an input when performing an ISA cycle
on behalf of the host CPU, DMA master or refresh.
ISA masters which do not monitor IOCHRDY are
not guaranteed to work with the STPC Atlas since
the access to the system memory can be
considerably delayed due to CRT refresh or a
write back cycle.
ALE Address Latch Enable. This is the address
latch enable output of the ISA bus and is asserted
by the STPC Atlas to indicate that LA23-17, SA190, AEN and SBHE# signals are valid. The ALE is
driven high during refresh, DMA master or an ISA
master cycles by the STPC Atlas.
ALE is driven low after reset.
BHE# System Bus High Enable. This signal, when
asserted, indicates that a data Byte is being
transferred on SD15-8 lines. It is used as an input
when an ISA master owns the bus and is an output
at all other times.
MEMR# Memory Read. This is the memory read
command signal of the ISA bus. It is used as an
input when an ISA master owns the bus and is an
output at all other times.
The MEMR# signal is active during refresh.
SMEMR# System Memory Read. The STPC Atlas
generates SMEMR# signal of the ISA bus only
when the address is below one MByte or the cycle
is a refresh cycle.
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IOCS16# IO Chip Select16. This signal is the
decode of SA15-0 address pins of the ISA address
bus without any qualification of the command
signals. The STPC Atlas does not drive IOCS16#
(similar to PC-AT design). An ISA master access
to an internal register of the STPC Atlas is
executed as an extended 8-bit IO cycle.
REF# Refresh Cycle. This is the refresh command
signal of the ISA bus. It is driven as an output
when the STPC Atlas performs a refresh cycle on
the ISA bus. It is used as an input when an ISA
master owns the bus and is used to trigger a
refresh cycle.
The STPC Atlas performs a pseudo hidden
refresh. It requests the host bus for two host clocks
to drive the refresh address and capture it in
external buffers. The host bus is then relinquished
while the refresh cycle continues on the ISA bus.
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AEN Address Enable. Address Enable is enabled
when the DMA controller is the bus owner to
indicate that a DMA transfer will occur. The
enabling of the signal indicates to IO devices to
ignore the IOR#/IOW# signal during DMA
transfers.
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MEMW# Memory Write. This is the memory write
command signal of the ISA bus. It is used as an
input when an ISA master owns the bus and is an
output at all other times.
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MCS16# Memory Chip Select16. This is the
decode of LA23-17 address pins of the ISA
address bus without any qualification of the
command signal lines. MCS16# is always an
input. The STPC Atlas ignores this signal during
IO and refresh cycles.
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SMEMW# System Memory Write. The STPC Atlas
generates SMEMW# signal of the ISA bus only
when the address is below one MByte.
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IOR# I/O Read. This is the IO read command
signal of the ISA bus. It is an input when an ISA
master owns the bus and is an output at all other
times.
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IOW# I/O Write. This is the IO write command
signal of the ISA bus. It is an input when an ISA
master owns the bus and is an output at all other
times.
MASTER# Add On Card Owns Bus. This signal is
active when an ISA device has been granted bus
ownership.
IOCHCK# IO Channel Check. IO Channel Check
is enabled by any ISA device to signal an error
condition that can not be corrected. NMI signal
becomes active upon seeing IOCHCK# active if
the corresponding bit in Port B is enabled.
GPIOCS# I/O General Purpose Chip Select 1.
This output signal is used by the external latch on
ISA bus to latch the data on the SD[7:0] bus. The
latch can be use by PMU unit to control the
external peripheral devices to power down or any
other desired function.
RTCRW# Real Time Clock RW#. This pin is used
as RTCRW#. This signal is asserted for any I/O
write to port 71h.
RTCDS# Real Time Clock DS. This pin is used as
RTCDS#. This signal is asserted for any I/O read
to port 71h. Its polarity complies with the DS pin of
the MT48T86 RTC device when configured with
Intel timings.
RTCAS Real time clock address strobe. This
signal is asserted for any I/O write to port 70h.
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STPC® ATLAS
RMRTCCS# ROM/Real Time clock chip select.
This pin is a multi-function pin. This signal is
asserted if a ROM access is decoded during a
memory cycle. It should be combined with MEMR#
or MEMW# signals to properly access the ROM.
During an IO cycle, this signal is asserted if access
to the Real Time Clock (RTC) is decoded. It should
be combined with IOR# or IOW# signals to
properly access the real time clock.
IRQ_MUX[3:0] Multiplexed Interrupt Request.
These are the ISA bus interrupt signals. They are
to be encoded before connection to the STPC
Atlas using ISACLK and ISACLKX2 as the input
selection strobes.
Note that IRQ8B, which by convention is
connected to the RTC, is inverted before being
sent to the interrupt controller, so that it may be
connected directly to the IRQ# pin of the RTC.
ISAOE# Bidirectional OE Control. This signal
controls the OE signal of the external transceiver
that connects the IDE DD bus and ISA SA bus.
KBCS# Keyboard Chip Select. This signal is
asserted if a keyboard access is decoded during a
I/O cycle.
IORD# I/O Read. This output is used with REG# to
gate I/O read data from the PC Card, (only when
REG# is asserted).
IOWR# I/O Write. This output is used with REG#
to gate I/O write data from the PC Card, (only
when REG# is asserted).
WP Write Protect. This input indicates the status of
the Write Protect switch (if fitted) on memory PC
Cards (asserted when the switch is set to write
protect).
BVD1, BVD2 Battery Voltage Detect. These
inputs will be generated by memory PC Cards that
include batteries and are an indication of the
condition of the batteries. BVD1 and BVD2 are
kept asserted high when the battery is in good
condition.
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READY#/BUSY#/IREQ#
Ready/busy/Interrupt
request. This input is driven low by memory PC
Cards to signal that their circuits are busy
processing a previous write command.
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WAIT# Bus Cycle Wait. This input is driven by the
PC Card to delay completion of the memory or I/O
cycle in progress.
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ZWS# Zero Wait State. This signal, when asserted
by addressed device, indicates that current cycle
can be shortened.
OE# Output Enable. OE# is an active low output
which is driven to the PC Card to gate Memory
Read data from memory PC Cards.
DACK_ENC[2:0] DMA Acknowledge. These are
the ISA bus DMA acknowledge signals. They are
encoded by the STPC Atlas before output and
should be decoded externally using ISACLK and
ISACLKX2 as the control strobes.
WE#/PRGM# Write Enable. This output is used by
the host for gating Memory Write data. WE# is also
used for memory PC Cards that have
programmable memory.
DREQ_MUX[1:0] ISA Bus Multiplexed DMA
Request. These are the ISA bus DMA request
signals. They are to be encoded before connection
to the STPC Atlas using ISACLK and ISACLKX2
as the input selection strobes.
REG# Attribute Memory Select. This output is
inactive (high) for all normal accesses to the Main
Memory of the PC Card. I/O PC Cards will only
respond to IORD# or IOWR# when REG# is active
(low). Also see Section 2.2.7.
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TC ISA Terminal Count. This is the terminal count
output of the DMA controller and is connected to
the TC line of the ISA bus. It is asserted during the
last DMA transfer, when the Byte count expires.
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2.2.5. PCMCIA INTERFACE
RESET Card Reset. This output forces a hard
reset to a PC Card.
A[25:0] Address Bus. These are the 25 low bits of
the system address bus of the PCMCIA bus.
These pins are used as an input when an PCMCIA
bus owns the bus and are outputs at all other
times.
D[15:0] I/O Data Bus (PCMCIA). These are the
external PCMCIA databus pins.
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CD1#, CD2# Card Detect. These inputs provide
for the detection of correct card insertion. CD#1
and CD#2 are positioned at opposite ends of the
connector to assist in the detection process.
These inputs are internally grounded on the PC
Card therefore they will be forced low whenever a
card is inserted in a socket.
CE1#, CE2# Card Enable. These are active low
output signals provided from the PCIC. CE#1
enables even Bytes, CE#2 odd Bytes.
ENABLE# Enable. This output is used to activate/
select a PC Card socket. ENABLE# controls the
external address buffer logic.C card has been
detected (CD#1 and CD#2 = '0').
STPC® ATLAS
ENIF# ENIF. This output is used to activate/select
a PC Card socket.
EXT_DIR EXternal Transceiver Direction Control.
This output is high during a read and low during a
write. The default power up condition is write (low).
Used for both Low and High Bytes of the Data Bus.
VCC_EN#, VPP1_EN0, VPP1_EN1, VPP 2_EN0,
VPP2_EN1 Power Control. Five output signals
used to control voltages (VPP1, VPP2 and VCC)
to a PC Card socket.
GPI# General Purpose Input. This signal is
hardwired to 1.
2.2.6. LOCAL BUS
PA[24:0] Address Bus Output.
PD[15:0] Data Bus. This is the 16-bit data bus.
D[7:0] is the LSB and PD[15:8] is the MSB.
PRD#[1:0] Read Control output. These are
memory and I/O Read signals. PRD0# is used to
read the LSB and PRD1# to read the MSB.
PWR#[1:0] Write Control output. These are
memory and I/O Write signals. PWR0# is used to
write the LSB and PWR1# to write the MSB.
TC ISA Terminal Count. This is the terminal count
output of the DMA controller and is connected to
the TC line of the ISA bus. It is asserted during the
last DMA transfer, when the Byte count expires.
2.2.8. IDE INTERFACE
DA[2:0] Address. These signals are connected to
DA[2:0] of IDE devices directly or through a buffer.
If the toggling of signals are to be masked during
ISA bus cycles, they can be externally ORed with
ISAOE# before being connected to the IDE
devices.
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DD[15:0] Databus. When the IDE bus is active,
they serve as IDE signals DD[11:0]. IDE devices
are connected to SA[19:8] directly and ISA bus is
connected to these pins through two LS245
transceivers.
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PCS1, PCS3, SCS1, SCS3 Primary & Secondary
Chip Selects. These signals are used as the active
high primary and secondary master & slave IDE
chip select signals. These signals must be
externally NANDed with the ISAOE# signal before
driving the IDE devices to guarantee it is active
only when ISA bus is idle. In Local Bus mode, they
just need to be inverted.
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PRDY Data Ready input. This signal is used to
create wait states on the bus. When high, it
completes the current cycle.
FCS#[1:0] Two Flash Memory Chip Select
outputs. These are the Programmable Chip Select
signals for Flash memory.
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DREQ_MUX[1:0] ISA Bus Multiplexed DMA
Request. These are the ISA bus DMA request
signals. They are to be encoded before connection
to the STPC Industrial using ISACLK and
ISACLKX2 as the input selection strobes.
IOCS#[7:0] I/O Chip Select output. These are the
Programmable Chip Select signals for up to 4
external I/O devices.
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PBE#[1:0] Byte Enable. These are the Byte
enables that identifies on which databus the date
is valid. PBE#[0] corresponds to PD[7:0] and
PBE#[1] corresponds to PD[15:8]. These are
normally used when 8 bit transfers are transfered
across the 16 bit bus.
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IRQ_MUX#[3:0] Multiplexed Interrupt Lines.
2.2.7. IPC
DACK_ENC[2:0] DMA Acknowledge. These are
the ISA bus DMA acknowledge signals. They are
encoded by the STPC Industrial before output and
should be decoded externally using ISACLK and
ISACLKX2 as the control strobes.
DIORDY Busy/Ready. This pin serves as IDE
signal DIORDY.
PIRQ Primary Interrupt Request.
SIRQ Secondary Interrupt Request.
Interrupt request from IDE channels.
PDRQ Primary DMA Request.
SDRQ Secondary DMA Request.
DMA request from IDE channels.
PDACK# Primary DMA Acknowledge.
SDACK# Secondary DMA Acknowledge.
DMA acknowledge to IDE channels.
PDIOR#, PDIOW# Primary I/O Read & Write.
SDIOR#, SDIOW# Secondary I/O Read & Write.
Primary & Secondary channel read & write.
2.2.9. MONITOR INTERFACE
RED, GREEN, BLUE RGB Video Outputs. These
are the 3 analog colour outputs from the
RAMDACs. These signals are sensitive to
interference, therefore they need to be properly
shielded.
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STPC® ATLAS
VSYNC Vertical Synchronisation Pulse. This is the
vertical synchronization signal from the VGA
controller.
- odd (not-top) field: LOW level
- even (bottom) field: HIGH level
2.2.11. TFT INTERFACE SIGNALS
HSYNC Horizontal Synchronisation Pulse. This is
the horizontal synchronization signal from the
VGA controller.
VREF_DAC DAC Voltage reference. This pin is an
input driving the digital to analog converters. This
allows an external voltage reference source to be
used.
The TFT (Thin Film Transistor) interface converts
signals from the CRT controller into control signals
for an external TFT Flat Panel. The signals are
listed below.
TFTFRAME, Vertical Sync. pulse Output.
TFTLINE, Horizontal Sync. Pulse Output.
RSET Resistor Current Set. This is the reference
current input to the RAMDAC. Used to set the fullscale output of the RAMDAC.
TFTDE, Data Enable.
TFTR5-0, Red Output.
COMP Compensation. This is the RAMDAC
compensation pin. Normally, an external capacitor
(typically 10nF) is connected between this pin and
VDD to damp oscillations.
TFTG5-0, Green Output.
TFTB5-0, Blue Output.
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DDC[1:0] Direct Data Channel Serial Link. These
bidirectional pins are connected to CRTC register
3Fh to implement DDC capabilities. They conform
to I2C electrical specifications, they have opencollector output drivers which are internally
connected to VDD through pull-up resistors.
TFTENVDD, Enable VDD of Flat Panel.
They can instead be used for accessing I²C
devices on board. DDC1 and DDC0 correspond to
SCL and SDA respectively.
TFTDCLK, Dot clock for the Flat Panel.
2.2.10. VIDEO INTERFACE
OC OVER CURRENT DETECT This signal is
used to monitor the status of the USB power
supply lines of both devices. USB port are
disabled when OC signal is asserted.
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VIN[7:0] YUV Video Data Input ITU-R 601 or 656.
Time
multiplexed
4:2:2
luminance
and
chrominance data as defined in ITU-R Rec601-2
and Rec656 (except for TTL input levels). This bus
typically carries a stream of Cb,Y,Cr,Y digital video
at VCLK frequency, clocked on the rising edge (by
default) of VCLK.
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VCS Line synchronisation Input. This is the
horizontal synchronisation of the incomming
CCIR601 video.
The signal is synchronous to rising edge of VCLK.
ODD_EVEN Frame Synchronisation Output. This
is the vertical synchronisation of the incomming
CCIR601 video.
The signal is synchronous to rising edge of VCLK.
The default polarity for this pin is:
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PWM PWM Back-Light Control. This PWM is
clocked by the PCI clock.
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VCLK Pixel Clock Input.This signal is used to
synchronise data being transferred from an
external video device to either the frame buffer, or
alternatively out the TV output in bypass mode.
This pin can be sourced from STPC if no external
VCLK is detected, or can be input from an external
video clock source.
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TFTENVCC, Enable VCC of Flat Panel.
2.2.12. USB INTERFACE
USBDPL0, USBDMNS0 UNIVERSAL SERIAL
BUS DATA 0 This signal pair comprises the
differential data signal for USB port 0.
USBDPL1, USBDMNS1 UNIVERSAL SERIAL
BUS PORT 1 This signal pair comprises the
differential data signal for USB port 1.
POWERON USB power supply lines
2.2.13. SERIAL INTERFACE
RXD0, RXD1 Serial Input. Data is clocked in using
RCLK/16.
TXD0, TXD1 Serial Output. Data is clocked out
using TCLK/16 (TCLK=BAUD#).
DCD0#, DCD1# Input Data carrier detect.
RI0#, RI1# Input Ring indicator.
DSR0#, DSR1# Input Data set ready.
STPC® ATLAS
INIT# Initialize Printer. This output sends an
initialize command to the connected printer.
CTS0#, CTS1# Input Clear to send.
RTS0#, RTS1# Output Request to send.
AUTOFD# Automatic Line feed. This output sends
a command to the connected printer to
automatically generate line feed on received
carriage returns.
DTR0#, DTR1# Output Data terminal read.
2.2.14. KEYBOARD/MOUSE INTERFACE
KBCLK, Keyboard Clock line. Keyboard data is
latched by the controller on each negative clock
edge produced on this pin. The keyboard can be
disabled by pulling this pin low by software control.
KBDATA, Keyboard Data Line. 11-bits of data are
shifted serially through this line when data is being
transferred. Data is synchronised to KBCLK.
MCLK, Mouse Clock line. Mouse data is latched
by the controller on each negative clock edge
produced on this pin. The mouse can be disabled
by pulling this pin low by software control.
MDATA, Mouse Data Line. 11-bits of data are
shifted serially through this line when data is being
transferred. Data is synchronised to MCLK.
2.2.15. PARALLEL PORT
SLCTIN# Select In. Printer select output.
PPD[7-0] Parallel Port Data Lines Data transfer
lines to printer. Bidirectional depending on modes.
2.2.16. MISCELLANEOUS
SPKRD Speaker Drive. This is the output to the
speaker and is the AND of the counter 2 output
with bit 1 of Port 61h and drives an external
speaker driver. This output should be connected to
a 7407 type high voltage driver.
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SCAN_ENABLE Reserved. This pin is reserved
for Test and Miscellaneous functions. It has to be
set to ‘0’ or connected to ground in normal
operation.
2.2.17. COL_SEL
INTERFACE
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PE Paper End. Input status signal from printer.
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Colour
Select.
JTAG
TCLK Test clock
SLCT Printer Select. Printer selected input.
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TDI Test data input
BUSY# Printer Busy.
Input status signal from printer.
TMS Test mode input
ERR# Error. Input status signal from printer.
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ACK# Acknowledge.
Input status signal from printer.
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PDDIR# Parallel Device Direction.
Bidirectional control line output.
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STROBE# PCS/Strobe#.
Data transfer strobe line to printer.
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TDO Test data output
TRST Test reset input
2.3 SIGNAL DETAIL
The muxing between ISA, LOCAL BUS and
PCMCIA is performed by external strap options.
The resulting interface is then dynamically muxed
with the IDE Interface.
Table 2-4. Multiplexed Signals (on the same pin)
O
bs
IDE Pin Name
DIORDY
DA[2]
DA[1:0]
SCS3,SCS1
PCS3,PCS1
DD[15]
DD[14]
DD[13:12]
DD[11:0]
ISA Pin Name
IOCHRDY
LA[19]
LA[18:17]
LA[23:22]
LA[21:20]
RMRTCCS#
KBCS#
RTCRW#, RTCDS#
SA[19:8]
PCMCIA Pin Names
=0
A[25:24]
A[23:22]
A[21:20]
ROMCS#
Hi-Z
Hi-Z
A[19:8]
Local Bus Pin Name
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STPC® ATLAS
Table 2-4. Multiplexed Signals (on the same pin)
IDE Pin Name
ISAOE# = 1
ISA Pin Name
SD[15:0]
RTCAS
DEV_CLK
SA[3]
SA[2:0]
SMEMW#
IOCS16#
MASTER#
MCS16#
DACK_ENC [2:0]
TC
SA[7:4]
ZWS#
GPIOCS#
IOCHCK#
REF#
IOW#
IOR#
MEMR#
ALE
AEN
BHE#
MEMW#
SMEMR#
DREQ_MUX#[1:0]
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
ISAOE# = 0
Table 2-5. Signal value on Reset
Signal Name
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BASIC CLOCKS AND RESETS
XTALO
ISA_CLK
ISA_CLK2X
OSC14M
DEV_CLK
HCLK
PCI_CLKO
DCLK
MEMORY CONTROLLER
MCLKO
CS#[3:1]
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PCMCIA Pin Names
D[15:0]
=0
DEV_CLK
A[3]
A[2:0]
VPP_PGM
WP/IOIS16#
BVD1
=0
= 0x04
=0
A[7:4]
GPI#
VCC5_EN
BVD2
RESET
IOWR#
IORD#
=0
=0
WAIT#
OE#
=0
VCC3_EN
CE2#, CE1#
Hi-Z
VPP_VCC
WE#
REG#
READY#
CD1#, CD2#
ISAOE# = 0
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-
SYSRSTI# active
Local Bus Pin Name
PD[15:0]
FCS0#
FCS1#
PRDY
IOCS#[2:0]
PBE#[1]
PBE#[0]
PRD#
PWR#
PA[2:0]
PA[3]
PA[7:4]
PA[8]
PA[9]
PA[10]
PA[11]
PA[12]
PA[13]
PA[14]
PA[15]
PA[16]
PA[17]
PA[18]
PA[19]
PA[21:20]
PA[22]
PA[23]
PA[24]
IOCS#[7]
IOCS#[6]
IOCS#[5], IOCS#[4]
IOCS#[3]
SYSRSTI# inactive
SYSRSTO# active
release of SYSRSTO#
14MHz
Low
7MHz
14MHz
14MHz
24MHz
Oscillating at the speed defined by the strap options.
HCLK divided by 2 or 3, depending on the strap options.
17MHz
66MHz if asynchonous mode, HCLK speed if synchronized mode.
High
STPC® ATLAS
Table 2-5. Signal value on Reset
Signal Name
SYSRSTI# active
CS#[0]
MA[10:0], BA[0]
RAS#[1:0], CAS#[1:0]
MWE#, DQM[7:0]
MD[63:0]
PCI INTERFACE
AD[31:0]
CBE[3:0], PAR
FRAME#, TRDY#, IRDY#
STOP#, DEVSEL#
PERR#, SERR#
PCI_GNT#[2:0]
ISA BUS INTERFACE
ISAOE#
RMRTCCS#
LA[23:17]
SA[19:0]
SD[15:0]
BHE#, MEMR#
MEMW#, SMEMR#, SMEMW#, IOR#, IOW#
REF#
ALE, AEN
DACK_ENC[2:0]
TC
GPIOCS#
RTCDS#, RTCRW#, KBCS#
RTCAS
PCMCIA INTERFACE
RESET
A[23:0]
D[15:0]
IORD#, IOWR#, OE#
WE#, REG#
CE2#, CE1#, VCC5_EN, VCC3_EN
VPP_PGM, VPP_VCC
LOCAL BUS INTERFACE
PA[24:0]
PD[15:0]
PRD#
PBE#[1:0], FCS0#, FCS_0H#
FCS_0L#, FCS1#, FCS_1H#, FCS_1L#
PWR#, IOCS#[7:0]
IDE CONTROLLER
DD[15:0]
DA[2:0]
PCS1, PCS3, SCS1, SCS3
PDACK#, SDACK#
PDIOR#, PDIOW#, SDIOR#, SDIOW#
VGA CONTROLLER
RED, GREEN, BLUE
VSYNC, HSYNC
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SYSRSTI# inactive
SYSRSTO# active
High
0x00
High
High
Input
SDRAM init sequence:
Write Cycles
0x0000
Low
Input
Input
Input
High
First prefetch cycles
when not in Local Bus mode.
High
Hi-Z
Unknown
0xFFFXX
Unknown
Unknown
Unknown
Unknown
Low
Input
Input
Hi-Z
Hi-Z
Unknown
Low
0x00
0xFFF03
0xFF
High
High
High
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Unknown
Unknown
Unknown
Unknown
High
High
Low
(t s)
release of SYSRSTO#
Unknown
Unknown
Unknown
High
High
High
0xFF
Unknown
Unknown
High
High
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First prefetch cycles
when in ISA or PCMCIA mode.
Address start is 0xFFFFF0
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0x04
Low
High
Low
High
0x00
0xFF
High
First prefetch cycles
using RMRTCCS#
0xFF
High
First prefetch cycles
Low
Low
Black
Low
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STPC® ATLAS
Table 2-5. Signal value on Reset
Signal Name
SYSRSTI# active
COL_SEL
I2C INTERFACE
SCL / DDC[1]
SDA / DDC[0]
TFT INTERFACE
TFT[R,G,B][5:0]
TFTLINE, TFTFRAME
TFTDE, TFTENVDD, TFTENVCC, TFTPWM
TFTDCLK
USB INTERFACE
USBDPLS[1:0]1
USBDMNS[1:0]1
POWERON1
SERIAL CONTROLLER
TXD0, RTS0#, DTR0#
TXD1, RTS1#, DTR1#
KEYBOARD & MOUSE INTERFACE
KBCLK, MCLK
KBDATA, MDATA
PARALLEL PORT
PDIR#, INIT#
STROBE#, AUTOFD#
SLCTIN#
PPD[7:0]
GPIO SIGNALS
GPIO[15:0]
JTAG
TDO
MISCELLANEOUS
SPKRD
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release of SYSRSTO#
Unknown
Input
Input
0x00,0x00,0x00
Low
Low
Oscillating at DCLK speed
Low
High
Unknown
Low
High
High
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Low
Input
Low
High
Unknown
Unknown
High
High
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SYSRSTI# inactive
SYSRSTO# active
Low
Low
0x00
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STPC® ATLAS
Table 2-6. Pinout
Table 2-6. Pinout
Pin#
D15
C15
AF21
AF22
AF23
AF24
E15
A16
AB18
AB24
AB25
AC18
Pin Name
SYSRSETI#
SYSRSETO#
XTALI
XTALO
PCI_CLKI
PCI_CLKO
ISA_CLK
ISA_CLK2X
OSC14M
HCLK
DEV_CLK1/FCS1#
DCLK
AF20
MCLKI
AF19
MCLKO
U5
MA[0]
V1
MA[1]
V2
MA[2]
V3
MA[3]
V4
MA[4]
V5
MA[5]
W1
MA[6]
W2
MA[7]
W3
MA[8]
W5
MA[9]
Y1
MA[10]
Y2
BA[0]
U3
RAS#[0]
U4
RAS#[1]
R5
CAS#[0]
T1
CAS#[1]
R4
MWE#
J4
MD[0]
J2
MD[1]
K5
MD[2]
K3
MD[3]
K1
MD[4]
L4
MD[5]
L2
MD[6]
M5
MD[7]
M3
MD[8]
M1
MD[9]
N4
MD[10]
N2
MD[11]
P1
MD[12]
P3
MD[13]
P5
MD[14]
R2
MD[15]
Note1; This signal is multiplexed
see Table 2-4
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le
)
s
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P
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O
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l
o
Pin#
Pin Name
AA4
MD[16]
AB1
MD[17]
AB3
MD[18]
AC1
MD[19]
AC3
MD[20]
AD2
MD[21]
AF3
MD[22]
AE4
MD[23]
AF4
MD[24]
AD5
MD[25]
AF5
MD[26]
AC6
MD[27]
AF6
MD[28]
AC7
MD[29]
AE7
MD[30]
AB8
MD[31]
J3
MD[32]
J1
MD[33]
K4
MD[34]
K2
MD[35]
L5
MD[36]
L3
MD[37]
L1
MD[38]
M4
MD[39]
M2
MD[40]
N5
MD[41]
N3
MD[42]
N1
MD[43]
P2
MD[44]
P4
MD[45]
R1
MD[46]
R3
MD[47]
AA5
MD[48]
AB2
MD[49]
AB4
MD[50]
AC2
MD[51]
AD1
MD[52]
AE3
MD[53]
AD4
MD[54]
AC5
MD[55]
AB6
MD[56]
AE5
MD[57]
AB7
MD[58]
AD6
MD[59]
AE6
MD[60]
AD7
MD[61]
AF7
MD[62]
AC8
MD[63]
U1
CS#[0]
U2
CS#[1]
Note1; This signal is multiplexed
see Table 2-4
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STPC® ATLAS
Table 2-6. Pinout
Table 2-6. Pinout
Pin#
Y3
Y4
T2
T4
Y5
AA2
T3
T5
AA1
AA3
Pin#
B8
A8
A7
D8
E8
C8
C14
B14
A14
A13
B13
C13
Pin Name
CS#[2]/MA[11]
CS#[3]/MA[12]/BA[1]
DQM[0]
DQM[1]
DQM[2]
DQM[3]
DQM[4]
DQM[5]
DQM[6]
DQM[7]
B3
AD[0]
A3
AD[1]
C4
AD[2]
B4
AD[3]
A4
AD[4]
D5
AD[5]
C5
AD[6]
B5
AD[7]
A5
AD[8]
D6
AD[9]
C6
AD[10]
B6
AD[11]
A6
AD[12]
E7
AD[13]
D7
AD[14]
C7
AD[15]
A9
AD[16]
E10
AD[17]
C10
AD[18]
B10
AD[19]
A10
AD[20]
E11
AD[21]
D11
AD[22]
C11
AD[23]
A11
AD[24]
E12
AD[25]
D12
AD[26]
C12
AD[27]
B12
AD[28]
A12
AD[29]
E13
AD[30]
D13
AD[31]
E6
CBE[0]
B7
CBE[1]
B9
CBE[2]
B11
CBE[3]
C9
FRAME#
E9
TRDY#
D9
IRDY#
Note1; This signal is multiplexed
see Table 2-4
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C20
LA[17]1
B21
LA[18]1
B20
LA[19]1
E19
LA[20]1
E18
LA[21]1
C21
LA[22]1
D19
LA[23]1
P22
SA[0]1
P23
SA[1]1
P24
SA[2]1
P25
SA[3]1
P26
SA[4]1
N26
SA[5]1
N25
SA[6]1
N24
SA[7]1
N23
SA[8]1
N22
SA[9]1
M26
SA[10]1
M25
SA[11]1
M24
SA[12]1
M23
SA[13]1
M22
SA[14]1
L26
SA[15]1
L25
SA[16]1
L24
SA[17]1
L23
SA[18]1
L22
SA[19]1
K24
SD[0]1
J26
SD[1]1
J25
SD[2]1
J24
SD[3]1
K23
SD[4]1
K22
SD[5]1
H26
SD[6]1
H25
SD[7]1
H24
SD[8]1
G26
SD[9]1
1
Note ; This signal is multiplexed
see Table 2-4
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Pin Name
STOP#
DEVSEL#
PAR
PERR#
SERR#
LOCK#
PCI_REQ#[0]
PCI_REQ#[1]
PCI_REQ#[2]
PCI_GNT#[0]
PCI_GNT#[1]
PCI_GNT#[2]
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STPC® ATLAS
Table 2-6. Pinout
Table 2-6. Pinout
Pin#
G25
G24
J22
J23
F26
F25
F23
D20
K25
F24
A22
G23
E21
H22
E26
E25
E24
C22
G22
E17
A23
U25
U26
U24
U23
D22
D24
E23
C26
F22
A24
C23
B23
D26
D25
B24
B15
A15
E14
D14
B16
B22
K26
Pin#
T25
T24
R22
T26
Pin Name
PDIOR#
PDIOW#
SDIOR#
SDIOW#
D18
C19
B19
A17
B17
C16
E16
D17
C18
B18
C17
PA[22]
PA[23]
PA[24]
FCS_0H
FCS_0L
FCS_1H
FCS_1L
IOCS#[4]
IOCS#[5]
IOCS#[6]
IOCS#[7]
AD8
AF8
AC9
AB10
AF9
AB9
AD9
AE8
AE9
AC10
RED
GREEN
BLUE
VSYNC
HSYNC
VREF_DAC
RSET
COMP
VDD_DAC
VSS_DAC
AB15
AF16
AE16
AC16
AB16
AF17
AE17
AD17
AB17
AD18
AF18
VCLK
VIN[0]
VIN[1]
VIN[2]
VIN[3]
VIN[4]
VIN[5]
VIN[6]
VIN[7]
ODD_EVEN#
VCS
Pin Name
SD[10]1
SD[11]1
SD[12]1
SD[13]1
SD[14]1
SD[15]1
IOCHRDY1
ALE1
BHE#1
MEMR#1
MEMW#1
SMEMR#1
SMEMW#1
IOR#1
IOW#1
MASTER#1
MCS16#1
IOCS16#1
REF#1
AEN1
IOCHCK#1
RTCRW#1
RTCDS#1
RTCAS1/FCS0#
RMRTCCS#1
GPIOCS#1
IRQ_MUX[0]
IRQ_MUX[1]
IRQ_MUX[2]
IRQ_MUX[3]
DACK_ENC[0]
DACK_ENC[1]1
DACK_ENC[2]1
DREQ_MUX[0]1
DREQ_MUX[1]1
TC1
PCI_INT#[0]
PCI_INT#[1]
PCI_INT#[2]
PCI_INT#[3]
ISAOE#1
KBCS#1
ZWS#1
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R23
PIRQ
R24
SIRQ
T22
PDRQ
T23
SDRQ
R25
PDACK#
R26
SDACK#
Note1; This signal is multiplexed
see Table 2-4
e
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-
AE10
TFTR0
AF10
TFTR1
AB11
TFTR2
AD11
TFTR3
AE11
TFTR4
AF11
TFTR5
AB12
TFTG0
AC12
TFTG1
AD12
TFTG2
AE12
TFTG3
Note1; This signal is multiplexed
see Table 2-4
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1
STPC® ATLAS
Table 2-6. Pinout
Table 2-6. Pinout
Table 2-6. Pinout
Pin#
AF12
AB13
AC13
AD13
AE13
AF13
AF14
AE14
AB14
AC14
AF15
AE15
AD15
AC15
AD14
Pin Name
TFTG4
TFTG5
TFTB0
TFTB1
TFTB2
TFTB3
TFTB4
TFTB5
TFTLINE
TFTFRAME
TFTDE
TFTENVDD
TFTENVCC
TFTPWM
TFTDCLK
Pin#
V22
V24
V25
V26
U22
Y22
AA24
AA25
AA26
Y24
Y25
Y26
W22
Pin Name
PDDIR
STROBE#
INIT#
AUTOFD#
SLCTIN#
PPD[0]
PPD[1]
PPD[2]
PPD[3]
PPD[4]
PPD[5]
PPD[6]
PPD[7]
Pin#
AE21
Pin Name
VDD_PCICLK_PLL
F13
F15
F17
K6
M21
N6
P21
R6
U21
AA10
AA12
AA14
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
AC19
AD19
SCL / DDC[1]
SDA / DDC[0]
D21
A20
A18
A21
A19
E20
OC
USBDMNS[0]
USBDMNS[1]
USBDPLS[0]
USBDPLS[1]
POWERON
AC22
AC24
AD21
AE24
AC21
AD25
AD22
AC26
AD23
AA22
AE22
AC25
AB21
AD26
AE23
AB23
CTS0#
CTS1#
DCD0#
DCD1#
DSR0#
DSR1#
DTR0#
DTR1#
RI0#
RI1#
RTS0#
RTS1#
RXD0
RXD1
TXD0
TXD1
C2
C1
D3
D2
D1
E4
E3
E2
E1
F5
F4
F3
F2
G5
G4
G2
GPIO[0]
GPIO[1]
GPIO[2]
GPIO[3]
GPIO[4]
GPIO[5]
GPIO[6]
GPIO[7]
GPIO[8]
GPIO[9]
GPIO[10]
GPIO[11]
GPIO[12]
GPIO[13]
GPIO[14]
GPIO[15]
H2
J5
H5
H3
H1
TCLK
TRST
TDI
TMS
TDO
A2
A25
B1
B26
F7
F11
F20
G6
G21
H6
J21
K21
U6
V6
Y6
Y21
AA7
AA16
AA18
AA20
AE01
AE26
AF02
AF25
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
G1
AD10
C25
SCAN_ENABLE
COL_SEL
SPKRD
AD20
AB19
AC20
AB20
)
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l
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KBCLK
KBDATA
MDATA
MCLK
AA23
PE
W24
SLCT
W23
BUSY
W25
ERR#
W26
ACK#
Note1; This signal is multiplexed
see Table 2-4
e
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O
-
AD16
VDD_DCLK_PLL
Y23
VDD_DEVCLK_PLL
AE20
VDD_HCLKI_PLL
AB26
VDD_HCLKO_PLL
AE19
VDD_MCLKI_PLL
AE18
VDD_MCLKO_PLL
Note1; This signal is multiplexed
see Table 2-4
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A1
GND
A26
GND
B2
GND
B25
GND
C3
GND
C24
GND
D4
GND
D10
GND
D16
GND
D23
GND
Note1; This signal is multiplexed
see Table 2-4
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STPC® ATLAS
Table 2-6. Pinout
Table 2-6. Pinout
Table 2-6. Pinout
Pin#
Pin Name
E5
GND
E22
GND
F6
GND
F8
GND
F9
GND
F10
GND
F12
GND
F14
GND
F16
GND
F18
GND
F19
GND
F21
GND
H4
GND
H21
GND
H23
GND
J6
GND
L6
GND
L11:16
GND
L21
GND
M6
GND
M11:16 GND
N11:16 GND
Note1; This signal is multiplexed
see Table 2-4
Pin#
Pin Name
N21
GND
P6
GND
P11:16
GND
R11:16 GND
R21
GND
T6
GND
T11:16
GND
T21
GND
V21
GND
V23
GND
W4
GND
W6
GND
W21
GND
AA6
GND
AA8
GND
AA9
GND
AA11
GND
AA13
GND
AA15
GND
AA17
GND
AA19
GND
AA21
GND
Note1; This signal is multiplexed
see Table 2-4
Pin#
AB5
AB22
AC4
AC11
AC17
AC23
AD3
AD24
AE2
AE25
AF1
AF26
G3
Reserved
F1
Reserved
Note1; This signal is multiplexed
see Table 2-4
e
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ct
Pin Name
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
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STPC® ATLAS
3 STRAP OPTION
This chapter defines the STPC
Atlas Strap Options and their
locations. Some strap options
are left programmable for future
versions of silicon. The strap
options are sampled at a
specific point of the boot
process. This is shown in detail
in Figure 4-3
Actual
Set to ’0’ Set to ’1’
Settings
Reserved2
Not accessible
Pull Up
MD1
MD2
Index 5F,bit 6 User defined
HCLK Speed
See Section 3.1.3
MD3
Index 5F,bit 7 User defined
MD[4]
PCI_CLKO Divisor
Index 4A,bit 1
Pull-up
See Section 3.1.1.
MD[5]
MCLK Synchro (see Section 3.1.1. )
Index 4A,bit 2 User defined
Async
Sync
MD[6]
Index 4A,bit 6 User defined
PCI_CLKO Programming
See Section 3.1.1.
MD[7]
Index 4A,bit 7
Pull-down
MD[8]
Index 4A,bit 3 User defined
ISA / PCMCIA / Local Bus
See Section 3.1.1.
MD[9]
Index 4A,bit 3 User defined
MD10
Reserved2
Index 4B,bit 2
Pull down
Reserved2
Index 4B,bit 3
Pull down
MD11
Reserved2
Index 4B,bit 4
Pull up
MD12
Reserved2
Index 4B,bit 5
Pull up
MD13
MD14
CPU clock Multiplication
Index 4B,bit 6
Pull-up
See Section 3.1.2
Reserved2
Not accessible
Pull up
MD15
Reserved2
Not accessible
Pull up
MD16
MD17
PCI_CLKO Divisor
Index 4A,bit 0 User defined
See Section 3.1.1.
MD18
HCLK Pad Direction
Index 4C,bit 2
Pull-up
Input
Output
MD19
MCLK Pad Direction
Index 4C,bit 3
Pull-up
Hi-Z
Output
MD20
DCLK Pad Direction
Index 4C,bit 4 User defined
Input
Output
Reserved2
Index 5F,bit 0
Pull up
MD21
Reserved2
Index 5F,bit 2
Pull up
MD23
MD24
Index 5F,bit 3 User defined
MD25
HCLK PLL Speed
Index 5F,bit 4 User defined
See Section 3.1.3
MD26
Index 5F,bit 5 User defined
Reserved2
Not accessible
Pull up
MD27
Reserved2
Not accessible
Pull up
MD28
Reserved2
Not accessible
Pull up
MD29
Reserved2
Not accessible
Pull up
MD30
Reserved2
Not accessible
Pull up
MD31
MD32
Reserved2
Not accessible
Pull up
MD33
Reserved2
Not accessible
Pull up
MD34
Reserved2
Not accessible
Pull up
2
MD35
Reserved
Not accessible
Pull up
MD36
Local Bus Boot Device Size
Index 4B,bit 0 User defined
8-bit
16-bit
Reserved2
Not accessible
Pull down
MD37
Reserved2
Not accessible
Pull down
MD38
MD40
CPU clock Multiplication
Index 4B,bit 7 User defined
See Section 3.1.2
Note1: Strap options on TC/PA[3] and DACK_ENC[2:0]/PA[2:0] are required for all the STPC Atlas Configurations (ISA,
PCMCIA, Local Bus).
Note2: Must be implemented.
Signal
Designation
Location
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STPC® ATLAS
Actual
Set to ’0’ Set to ’1’
Settings
2
MD41
Reserved
Not accessible
Pull down
Reserved2
Not accessible
Pull up
MD42
Reserved2
Not accessible
Pull down
MD 43
MD 45
Not accessible User defined
CPUCLK/HCKL Deskew Programming
See Section 3.1.5
MD 46
Not accessible User defined
MD 47
Reserved2
Not accessible
Pull down
Reserved2
Not accessible
Pull up
MD 48
MD 50
Internal UART2 (see Section 3.1.4. )
Index 4C,bit 0 User defined
Disable
Enable
MD 51
Internal UART1 (see Section 3.1.4. )
Index 4C,bit 1 User defined
Disable
Enable
MD 52
Internal Kbd / Mouse (see Section 3.1.4. ) Index 4C,bit 6 User defined
Disable
Enable
MD 53
Internal Parallel Port (see Section 3.1.4. ) Index 4C,bit 7 User defined
Disable
Enable
Reserved2
Hardware
Pull up
TC1
1
2
Reserved
Hardware
Pull up
DACK_ENC[2]
Reserved2
Hardware
Pull up
DACK_ENC[1]1
Reserved2
Hardware
Pull up
DACK_ENC[0]1
Note1: Strap options on TC/PA[3] and DACK_ENC[2:0]/PA[2:0] are required for all the STPC Atlas Configurations (ISA,
PCMCIA, Local Bus).
Note2: Must be implemented.
Signal
Designation
Location
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STPC® ATLAS
3.1 STRAP OPTION
REGISTER DESCRIPTION
3.1.1. STRAP REGISTER 0
This register is read only.
STRAP0
Access = 0022h/0023h
Regoffset =04Ah
7
6
5
4
3
2
1
0
MD[7]
MD[6]
MD[9]
MD[8]
RSV
MD[5]
MD[4]
MD[17]
This register defaults to the values sampled on the MD pins after reset
Bit Number Sampled
Mnemonic
Description
MD[7:6]
PCICLK PLL set-up: The value sampled on MD[7:6] controls the PCICLK
PLL programming according to the PCICLK frequency.
MD7 MD6
0
0 PCICLK frequency between 16 & 32 MHz
0
1 PCICLK frequency between 32 & 64 MHz
1
X Reserved
Bits 5-4
MD[9:8]
Mode selection:
MD9 MD8
0
0 ISA mode: ISA enabled, PCMCIA & Local Bus disabled
0
1 PCMCIA mode: PCMCIA enabled, ISA & Local Bus disabled
1
0 Local Bus mode: Local Bus enabled, ISA & PCMCIA disabled
1
1 Reserved
Bit 3
Rsv
Bit 2
MD[5]
Host Memory synchronization. This bit reflects the value sampled on
[MD5] and controls the MCLK/HCLK synchronization.
0: MCLK and HCLK not synchronized
1: MCLK and HCLK synchronized.
MD[4], MD[17]
PCICLK division: These bits reflect the values sampled on [MD4] and
MD[17] to select the PCICLK frequency.
MD4 MD17
0
X PCI Clock output = HCLK / 4
1
0 PCI Clock output = HCLK / 3
1
1 PCI Clock output = HCLK / 2
Bits 7-6
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Bits 1-0
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Reserved
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STPC® ATLAS
3.1.2 STRAP REGISTER 1
This register is read only.
STRAP1
Access = 0022h/0023h
Regoffset =04Bh
7
6
5
4
3
2
1
0
MD[40]
MD[14]
RSV
RSV
RSV
RSV
RSV
MD[36]
This register defaults to the values sampled on the MD pins after reset
Bit Number Sampled
Mnemonic
Description
Bits 7-6
MD[40] & MD[14]
Bits 5-1
Rsv
Bit 0
MD[36]
CPU Clock Multiplication (486 mode):
MD14 MD40
1
0 X1
1
1 X2
All other settings are reserved
HCLK maximum speed is 66MHz and in CPU mode X2.
Operation in X1 mode is only guaranteed up to 66MHz.
Reserved
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These bits reflect the values sampled on MD[36] and determines the
Local Bus Boot device width:
0: 8-bit Boot Device
1: 16-bit Boot Device
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STPC® ATLAS
3.1.3 HCLK PLL STRAP REGISTER
This register is read only.
HCLK_STRAP0
7
Access = 0022h/0023h
6
RSV
5
4
3
MD[26]
MD[25]
MD[24]
Regoffset =05Fh
2
1
0
RSV
This register defaults to the values sampled on the MD pins after reset
Bit Number Sampled
Mnemonic
Bits 7-6
Rsv
Bits 5-3
MD[26:24]
Bits 2-0
Rsv
Description
These bits are fixed to ‘0’
These pins reflect the values sampled on MD[26:24] pins respectively
and control the Host clock frequency synthesizer as shown in Table 3-1
Reserved
c
u
d
Table 3-1. HCLK Frequency Configuration
MD[3]
0
0
0
0
MD[2]
0
0
0
0
MD[26]
MD[25]
0
0
0
0
0
1
0
1
All other settings are reserved
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-
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MD[24]
0
1
0
1
)
s
t(
HCLK Speed
25 MHz
50 MHz
60 MHz
66 MHz
STPC® ATLAS
3.1.4. STRAP REGISTER 2
This register is read only with the exception of bit 4
STRAP2
Access = 0022h/0023h
Regoffset =04Ch
7
6
5
4
3
2
1
0
MD[53]
MD[52]
RSV
MD[20]
MD[19]
MD[18]
MD[51]
MD[50]
This register defaults to the values sampled on the MD pins after reset
Bit Number Sampled
Mnemonic
Bit 7
MD[53]
This bit reflects the value sampled on MD[53] pin and determines
whether the internal Parallel Port Controller is used
0: Internal Parallel Port Controller is disabled
1: Internal Parallel Port Controller is enabled
Bit 6
MD[52]
This bit reflects the value sampled on MD[52] pin and determines
whether the internal Keyboard controller is used
0: Internal Keyboard Controller is disabled
1: Internal Keyboard Controller is enabled
Bit 5
Rsv
Bit 4
MD[20]
This bit reflects the value sampled on MD[20] pin and controls the Dot
clock pin (DCLK) direction as follows:
0: Input.
1: Output of the internal frequency synthesizer DCLK PLL.
Bit 3
MD[19]
This bit reflects the value sampled on MD[19] pin and controls the
Memory clock output pin (MCLKO) as follows:
0: Tristated.
1: Output of the internal frequency synthesizer MCLKO PLL.
Bit 2
MD[18]
This bit reflects the value sampled on MD[18] pin and controls the Host
clock pin (HCLK) direction as follows:
0: Input.
1: Output of the internal frequency synthesizer HCLK PLL.
Bit 1
MD[51]
t
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MD[50]
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Reserved
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s
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Bit 0
Description
)
s
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-
This bit reflects the value sampled on MD[51] pin and determines
whether the internal UART1 is enabled:
0: Internal UART1 is disabled
1: Internal UART1 is enabled
This bit reflects the value sampled on MD[50] pin and determines
whether the internal UART2 is enabled:
0: Internal UART2 is disabled
1: Internal UART2 is enabled
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1
STPC® ATLAS
3.1.5 CPUCLK/HCKL DESKEW PROGRAMMING
MD[45]
MD[46]
Description
1
0
HCLK between 33MHz and
64MHz
0
1
HCLK between 64MHz and
133MHz
3.2 TYPICAL STRAP OPTION
IMPLEMENTATION
Table 3-1.shows the detailed Strap options
required to boot the STPC in ISA mode with a Host
Clock Frequency of 66MHz in X2 mode with
internal keyboard/mouse, UARTS and parallel port
enabled.
All other settings are reserved
Note that these straps are not accessible by
software.
Table 3-1. Typical Strap Option Implementation
Actual
Description
Settings
2
Reserved
Pull Up
MD1
MD2
Pull down
HCLK Speed
HCLK = 66MHz
MD3
Pull down
MD[4]
PCI_CLKO Divisor
Pull up
PCICLK = HCLK/2
MD[5]
MCLK Synchro (see Section 3.1.1. )
Pull down
Asynchronous
MD[6]
Pull up
PCICLK PLL Window =
PCI_CLKO Programming
32MHz - 64MHz
MD[7]
Pull down
MD[8]
Pull down
ISA / PCMCIA / Local Bus
ISA Mode
MD[9]
Pull down
2
MD10
Reserved
Pull down
2
Reserved
Pull down
MD11
MD14
CPU clock Multiplication
Pull up
X2 Mode
Reserved2
Pull up
MD15
Reserved2
Pull up
MD16
MD17
PCI_CLKO Divisor
Pull up
PCICLK = HCLK/2
MD18
HCLK Pad Direction
Pull up
Output
MD19
MCLK Pad Direction
Pull up
Output
MD20
DCLK Pad Direction
Pull up
Output
Reserved2
Pull up
MD21
Reserved2
Pull up
MD23
MD24
Pull up
MD25
HCLK PLL Speed
Pull up
HCLK = 66MHz
MD26
Pull down
Reserved2
Pull up
MD27
Reserved2
Pull up
MD28
Reserved2
Pull up
MD29
2
Reserved
Pull up
MD30
Reserved2
Pull up
MD31
MD32
Reserved2
Pull up
MD33
Reserved2
Pull up
MD34
Reserved2
Pull up
Note1: Strap options on TC/PA[3] and DACK_ENC[2:0]/PA[2:0] are required for all the STPC Atlas Configurations (ISA,
PCMCIA, Local Bus).
Note2: Must be implemented.
Signal
Designation
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)
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t(
STPC® ATLAS
Table 3-1. Typical Strap Option Implementation
Actual
Description
Settings
MD35
Reserved2
Pull up
MD36
Local Bus Boot Device Size
User defined
Not Applicable
Reserved2
Pull down
MD37
Reserved2
Pull down
MD38
MD40
CPU clock Multiplication
Pull up
X2 mode
Reserved2
Pull down
MD41
Reserved2
Pull up
MD42
Reserved2
Pull down
MD 43
MD 45
Pull down HCLK between 64MHz and
CPUCLK/HCKL Deskew Programming
133MHz
MD 46
Pull up
2
MD 47
Reserved
Pull down
Reserved2
Pull up
MD 48
MD 50
Internal UART2 (see Section 3.1.4. )
Pull up
Enable
MD 51
Internal UART1 (see Section 3.1.4. )
Pull up
Enable
MD 52
Internal Kbd / Mouse (see Section 3.1.4. )
Pull up
Enable
MD 53
Internal Parallel Port (see Section 3.1.4. )
Pull up
Enable
Reserved2
Pull up
TC1
1
2
Reserved
Pull up
DACK_ENC[2]
Reserved2
Pull up
DACK_ENC[1]1
Reserved2
Pull up
DACK_ENC[0]1
Note1: Strap options on TC/PA[3] and DACK_ENC[2:0]/PA[2:0] are required for all the STPC Atlas Configurations (ISA,
PCMCIA, Local Bus).
Note2: Must be implemented.
Signal
Designation
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STPC® ATLAS
4 ELECTRICAL SPECIFICATIONS
4.1. INTRODUCTION
4.2.3. RESERVED DESIGNATED PINS
The electrical specifications in this chapter are
valid for the STPC Atlas.
Pins designated as reserved should be left disconnected. Connecting a reserved pin to a pull-up
resistor, pull-down resistor, or an active signal
could cause unexpected results and possible
circuit malfunctions.
4.2. ELECTRICAL CONNECTIONS
4.2.1.
POWER/GROUND
DECOUPLING
CONNECTIONS/
Due to the high frequency of operation of the
STPC Atlas, it is necessary to install and test this
device using standard high frequency techniques.
The high clock frequencies used in the STPC Atlas
and its output buffer circuits can cause transient
power surges when several output buffers switch
output levels simultaneously. These effects can be
minimized by filtering the DC power leads with
low-inductance decoupling capacitors, using low
impedance wiring, and by utilizing all of the VSS
and VDD pins.
4.2.2. UNUSED INPUT PINS
No unused input pin should be left unconnected
unless they have an integrated pull-up or pulldown. Connect active-low inputs to VDD through a
20 kΩ (±10%) pull-up resistor and active-high
inputs to VSS. For bi-directionnal active-high
inputs, connect to VSS through a 20 kΩ (±10%)
pull-up resistor to prevent spurious operation.
)
s
(
ct
4.3. ABSOLUTE MAXIMUM RATINGS
The following table lists the absolute maximum
ratings for the STPC Atlas device. Stresses
beyond those listed under Table 4-1 limits may
cause permanent damage to the device. These
are stress ratings only and do not imply that
operation under any conditions other than those
specified in section "Operating Conditions".
)
s
t(
Exposure to conditions beyond those outlined in
Table 4-1 may (1) reduce device reliability and (2)
result in premature failure even when there is no
immediately apparent sign of failure. Prolonged
exposure to conditions at or near the absolute
maximum ratings (Table 4-1) may also result in
reduced useful life and reliability.
c
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4.3.1. 5V TOLERANCE
o
s
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-
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d
o
The STPC is capable of running with I/O systems
that operate at 5 V such as PCI and ISA devices.
Certain pins of the STPC tolerate inputs up to
5.5 V. Above this limit the component is likely to
sustain permanent damage.
All 5 volt tolerant pins are outlined in Table 2-3
Buffer Type Descriptions.
Table 4-1. Absolute Maximum Ratings
Symbol
VDDx
VCORE
VI, VO
V5T
VESD
TSTG
r
P
e
Parameter
DC Supply Voltage
DC Supply Voltage for Core
Digital Input and Output Voltage
5Volt Tolerance
ESD Capacity (Human body mode)
Storage Temperature
t
e
l
o
s
b
O
TOPER
PTOT
Operating Temperature (Note 1)
Maximum Power Dissipation (package)
Note 1: The figures specified apply to the Tcase of a
STPC device that is soldered to a board, as detailed in the
44/108
1
Minimum
-0.3
-0.3
-0.3
-0.3
-40
0
-40
-
Maximum
4.0
2.7
VDD + 0.3
5.5
2000
+150
+85
+115
4.8
Units
V
V
V
V
V
°C
°C
°C
W
Design Guidelines Section, for Commercial and Industrial
temperature ranges.
STPC® ATLAS
4.4. DC CHARACTERISTICS
Table 4-2. DC Characteristics
Symbol
VDD
VCORE
PDD
PCORE
Parameter
3.3V Operating Voltage
2.5V Operating Voltage
3.3V Supply Power
2.5V Supply Power1
Test conditions
Min
3.0
2.45
Typ
3.3
2.5
Max
Unit
3.6
V
2.7
V
3.0V < VDD < 3.6V
0.24
W
2.45V < VCORE < 2.7V
4.1
W
Except XTALI
-0.3
0.8
V
VIL
Input Low Voltage
XTALI
-0.3
0.8
V
V
Except XTALI
2.1
VDD+0.3
VIH Input High Voltage
V
XTALI
2.35
VDD+0.3
Input Leakage Current
Input, I/O
-5
5
µA
ILK
Integrated Pull up/down
50
KΩ
Note 1; Power consumption is heavily dependant on the clock frequencies and on the enabled features. See details in
Table 4-5. to Table 4-8..
c
u
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Table 4-3. PAD buffers DC Characteristics
)
s
t(
I/O VIH min VIL max VOH min VOL max IOL min IOH max Cload max Derating
Buffer Type
count
(V)
(V)
(V)
(V)
(mA)
(mA)
(pF)
(ps/pF)1
ANA
10
2.35
0.9
OSCI13B
2
2.1
0.8
2.4
0.4
2
-2
50
0.4
4
-4
100
30
BT4CRP
1
0.85*VDD
BT8TRP_TC
7
2.4
0.4
8
-8
200
21
BD4STRP_FT
64
2
0.8
2.4
0.4
4
-4
100
42
BD4STRUP_FT
14
2
0.8
2.4
0.4
4
-4
100
41
BD4STRP_TC
26
2
0.8
2.4
0.4
4
-4
100
42
BD8STRP_FT
30
2
0.8
2.4
0.4
8
-8
200
23
BD8STRUP_FT
47
2
0.8
2.4
0.4
8
-8
200
23
BD8STRP_TC
12
2
0.8
2.4
0.4
8
-8
200
21
BD8TRP_TC
53
2
0.8
2.4
0.4
8
-8
200
21
1.5
- 0.5
200
15
BD8PCIARP_FT
50 0.5*VDD 0.3*VDD 0.9*VDD 0.1*VDD
BD14STARP_FT
18
2
0.8
2.4
0.4
14
-14
100
71
BD16STARUQP_TC
19
2
0.8
2.4
0.4
16
-16
400
12
SCHMITT_FT
1
2
0.8
TLCHT_FT
16
2
0.8
TLCHT_TC
1
2
0.8
TLCHTD_TC
1
2
0.8
TLCHTU_TC
1
2
0.8
USBDS_2V5 (slow)
45.2
4
2
0.8
2.4
0.4
100
USBDS_2V5 (fast)
98.8
Note 1: time to output variation depending on the capacitive load.
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CIN
(pF)
5.61
6.89
5.97
5.97
5.83
5.96
5.96
7.02
7.03
6.97
6.20
9.34
5.97
5.97
5.97
5.97
5.97
8.41
45/108
1
STPC® ATLAS
Table 4-4. RAMDAC DC Specification
Symbol
Vref_dac
INL
DNL
BLC
WLC
Parameter
Min
1.00 V
1.0 mA
15.00 mA
Voltage Reference
Integrated Non Linear Error
Differentiated Non Linear Error
Black Level Current
White Level Current
Max
1.24 V
3 LSB
1 LSB
2.0 mA
18.50 mA
Table 4-5. VGA RAMDAC Power Consumption
DCLK
DAC mode
(MHz)
6.25 - 135
(State)
Shutdown
Active
PMax (mW)
VDD_DAC = 2.7V
VDD_DAC = 2.45V
0
0
150
180
Table 4-6. 2.5V Power Consumptions (VCORE + VDD_x_PLL + VDD_DAC)
HCLK
CPUCLK
MCLK
(MHz)
(MHz)
(MHz)
Mode
DCLK
PMU
(MHz)
(State)
Stop Clock
Full Speed
Stop Clock
Full Speed
Stop Clock
Full Speed
Stop Clock
Full Speed
Stopped
66
133 (x2)
66
SYNC
135
Stopped
66
133 (x2)
90
ASYNC
o
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135
Note 1: PCI clock at 33MHz
Table 4-7. 3.3V Power Consumptions (VDD)
HCLK
CPUCLK
(MHz)
(MHz)
66
133 (x2)
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133 (x2)
MCLK
(MHz)
66
90
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PMax (W)
V2.5V=2.7V
V2.5V=2.45V
1.5
1.9
2.5
3.0
2.1
2.6
2.1
3.6
1.9
2.4
2.8
3.5
2.5
3.1
3.3
4.1
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DCLK
PMU
(MHz)
6.26
135
6.26
135
(State)
Full Speed
Full Speed
PMax
(mW)
130
215
150
240
Table 4-8. PLL Power Consumptions
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VDD_DCLK_PLL
VDD_DEVCLK_PLL
VDD_HCLKI_PLL
VDD_HCLKO_PLL
VDD_MCLKI_PLL
VDD_MCLKO_PLL
VDD_PCICLK_PLL
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PLL name
PMax (mW)
VDD_PLL = 2.7V
VDD_PLL = 2.45V
5
10
5
10
5
10
5
10
5
10
5
10
5
10
STPC® ATLAS
4.5. AC CHARACTERISTICS
Figure 4-1 shows output delay (A and B) and input
setup and hold times (C and D). Input setup and
hold times (C and D) are specified minimums,
defining the smallest acceptable sampling window
a synchronous input signal must be stable for
correct operation.
This section lists the AC characteristics of the
STPC interfaces including output delays, input
setup requirements, input hold requirements and
output float delays. These measurements are
based on the measurement points identified in
Figure 4-1 and Figure 4-2. The rising clock edge
reference level VREF and other reference levels
are shown in Table 4-9 below. Input or output
signals must cross these levels during testing.
Table 4-9. Drive Level and Measurement Points for Switching Characteristics
Symbol
VREF
VIHD
VILD
Value
1.5
2.5
0.0
Units
V
V
V
Note: Refer to Figure 4-1.
Figure 4-1. Drive Level and Measurement Points for Switching Characteristics
Tx
e
t
le
CLK:
A
B
OUTPUTS:
Valid
Output n
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INPUTS:
t
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LEGEND:
s
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MIN
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VIHD
VRef
VILD
o
s
b
O
MAX
Valid
Output n+1
VRef
du
C
D
VIHD
Valid
Input
VRef
VILD
A - Maximum Output Delay Specification
B - Minimum Output Delay Specification
C - Minimum Input Setup Specification
D - Minimum Input Hold Specification
47/108
1
STPC® ATLAS
4.5.1. POWER ON SEQUENCE
Figure 4-2. CLK Timing Measurement Points
T1
T2
VIH (MIN)
VRef
CLK
VIL (MAX)
T5
T4
T3
T1 - One Clock Cycle
T2 - Minimum Time at VIH
T3 - Minimum Time at VIL
T4 - Clock Fall Time
T5 - Clock Rise Time
NOTE; All sIgnals are sampled on the rising edge of the CLK.
LEGEND:
Figure 4-3 describes the power-on sequence of
the STPC, also called cold reset.
There is no dependency between the different
power supplies and there is no constraint on their
rising time.
u
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1
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Strap Options are continuously sampled during
SYSRSTI# low and must remain stable. Once
SYSRSTI# is high, they MUST NOT CHANGE
until SYSRSTO# goes high.
e
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O
-
SYSRSTI# as no constraint on its rising edge but
must stay active until power supplies are all within
specifications, a margin of 10µs is even
recommended to let the STPC PLLs and strap
options stabilize.
)
s
(
ct
c
u
d
)
s
t(
Bus activity starts only few clock cycles after the
release of SYSRSTO#. The toggling signals
depend on the STPC configuration.
In ISA mode, activity is visible on PCI prior to the
ISA bus as the controller is part of the south
bridge.
In Local Bus mode, the PCI bus is not accessed
and the Flash Chip Select is the control signal to
monitor.
STPC® ATLAS
Figure 4-3. Power-on timing diagram
Power Supplies
14 MHz
> 10 us
1.6 V
SYSRSTI#
c
u
d
ISACLK
e
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)
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t(
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VALID CONFIGURATION
Strap Options
HCLK
)
s
(
ct
u
d
o
PCI_CLK
r
P
e
o
s
b
O
-
2.3 ms
t
e
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SYSRSTO#
s
b
O
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1
STPC® ATLAS
4.5.2 RESET SEQUENCE
Figure 4-4 describes the reset sequence of the
STPC, also called warm reset.
The constraints on the strap options and the bus
activities are the same as for the cold reset.
The SYSRSTI# pulse duration must be long
enough to have all the strap options stabilized and
must be adjusted depending on resistor values.
It is mandatory to have a clean reset pulse without
glitches as the STPC could then sample invalid
strap option setting and enter into an umpredictable mode.
While SYSRSTI# is active, the PCI clock PLL runs
in open loop mode at a speed of few 100’s KHz.
Figure 4-4. Reset timing diagram
14 MHz
1.6 V
SYSRSTI#
c
u
d
ISACLK
Strap Options
MD[63:0]
e
t
le
HCLK
PCI_CLK
SYSRSTO#
)
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1
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VALID CONFIGURATION
o
s
b
O
-
2.3 ms
)
s
t(
STPC® ATLAS
MCLKx clocks are the input clock of the SDRAM
devices.
4.5.3. SDRAM INTERFACE
Figure 4-5, Table 4-10, Table 4-11 lists the AC
characteristics of the SDRAM interface. The
Figure 4-5. SDRAM Timing Diagram
MCLKx
Tdelay
MCLKI
Thigh
Tlow
Tcycle
STPC.output
Toutput (max)
c
u
d
Toutput (min)
STPC.input
e
t
le
)
s
t(
o
r
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Tsetup
Thold
o
s
b
O
-
Table 4-10. SDRAM Bus AC Timings - Commercial Temperature Range
)
s
(
ct
Name
Tcycle
Thigh
Tlow
Parameter
Min
Typ
Max
MCLKI Cycle Time
11
MCLKI High Time
4
MCLKI Low Time
4
MCLKI Rising Time
1
MCLKI Falling Time
1
Tdelay
MCLKx to MCLKI delay
0.5
1
1.5
MCLKI to RAS# Valid
1.6
5.2
MCLKI to CAS# Valid
1.6
5.2
MCLKI to CS# Valid
1.6
5.2
Toutput
MCLKI to DQM[ ] Outputs Valid
1.35
5.2
MCLKI to MD[ ] Outputs Valid
1.35
5.2
MCLKI to MA[ ] Outputs Valid
1.6
5.2
MCLKI to MWE# Valid
1.6
5.2
Tsetup
MD[63:0] setup to MCKLI
4.7
Thold
MD[63:0] hold from MCKLI
-0.36
2.3
Note: These timings are for a load of 50pF, part running at 100MHz and ReadCLK activated and set to 0
u
d
o
r
P
e
t
e
l
o
s
b
O
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
The PC100 memory is recommended to reach 90MHz operation.
51/108
1
STPC® ATLAS
Table 4-11. SDRAM Bus AC Timings - Industrial Temperature Range
Name
Tcycle
Thigh
Tlow
Parameter
Min
Typ
MCLKI Cycle Time
11
MCLKI High Time
4
MCLKI Low Time
4
MCLKI Rising Time
MCLKI Falling Time
Tdelay
MCLKx to MCLKI delay
0.5
1
MCLKI to RAS# Valid
1.7
MCLKI to CAS# Valid
1.7
MCLKI to CS# Valid
1.7
Toutput
MCLKI to DQM[ ] Outputs Valid
2
MCLKI to MD[ ] Outputs Valid
2
MCLKI to MA[ ] Outputs Valid
1.7
MCLKI to MWE# Valid
1.7
Tsetup
MD[63:0] setup to MCKLI
4.7
Thold
MD[63:0] hold from MCKLI
-0.36
Note: These timings are for a load of 50pF, part running at 90MHz and ReadCLK not activated
The PC100 memory is recommended to reach 90MHz operation.
)
s
(
ct
u
d
o
r
P
e
t
e
l
o
s
b
O
52/108
1
1
1
1.5
6.5
6.5
6
6
7.8
6.5
6
uc
d
o
r
P
e
let
o
s
b
O
-
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
)
s
t(
2.3
STPC® ATLAS
4.5.4 PCI INTERFACE
Figure 4-6 and Table 4-12. list the AC characteristics of the PCI interface. PCICLKx stands for any
PCI device clock input.
Figure 4-6. PCI Timing Diagram
HCLK
PCICLKx
Tclkx
PCICLKI
Thigh
Thclk
Tlow
Tcycle
c
u
d
STPC.output
Toutput (max)
STPC.input
Thold
Table 4-12. PCI Bus AC Timings
Name
s
b
O
t
e
l
o
o
r
P
Toutput (min)
e
t
le
o
s
b
O
-
Tsetup
u
d
o
)
s
(
ct
Parameter
HCLK to PCICLKO delay (MD[30:27] = 1111)
Thclk
HCLK to PCICLKI delay
Tclkx
PCICLKI to PCICLKx skew
Tcycle
PCICLKI Cycle Time
Thigh
PCICLKI High Time
Tlow
PCICLKI Low Time
Note: These timings are for a load of 50pF.
r
P
e
)
s
t(
Min
4.4
6.5
-0.5
30
13
13
Typ
5.0
7.5
0.3
Max
5.7
8.5
1.0
Unit
ns
ns
ns
ns
ns
ns
53/108
1
STPC® ATLAS
4.5.5 IPC INTERFACE
Table 4-13 lists the AC characteristics of the IPC
interface.
Figure 4-7. IPC timing diagram
ISACLK2X
Tdly
ISACLK
Tsetup
Tsetup
IRQ_MUX[3:0]
c
u
d
DREQ_MUX[1:0]
Table 4-13. IPC Interface AC Timings
Name
Tsetup
Tsetup
Parameter
IRQ_MUX[3:0] Input setup to ISACLK2X
DREQ_MUX[1:0] Input setup to ISACLK2X
)
s
(
ct
u
d
o
r
P
e
t
e
l
o
s
b
O
54/108
1
o
s
b
O
-
e
t
le
)
s
t(
o
r
P
Min
0
0
Max
-
Unit
nS
nS
STPC® ATLAS
4.5.6 ISA INTERFACE AC TIMING CHARACTERISTICS
Figure 4-8 and Table 4-14 list the AC characteristics of the ISA interface.
Figure 4-8. ISA Cycle (ref Table 4-14.)
2
15
38
37
14
13
12
25
9
56
18
29
ALE
22
AEN
Valid AENx
34
33
LA [23:17]
3
Valid Address
42
11
24
41
c
u
d
57
10
27
SA [19:0]
Valid Address, SBHE*
26
23
o
r
P
55
58
59
48
47
e
t
le
61
CONTROL (Note 1)
IOCS16#
MCS16#
IOCHRDY
READ DATA
WRITE DATA
)
s
(
ct
o
s
b
O
-
)
s
t(
28
64
54
V.Data
VALID DATA
u
d
o
Note 1: Stands for SMEMR#, SMEMW#, MEMR#, MEMW#, IOR# & IOW#.
The clock has not been represented as it is dependent on the ISA Slave mode.
r
P
e
Table 4-14. ISA Bus AC Timing
t
e
l
o
Name
2
3
Parameter
LA[23:17] valid before ALE# negated
LA[23:17] valid before MEMR#, MEMW# asserted
3a Memory access to 16-bit ISA Slave
3b Memory access to 8-bit ISA Slave
9
SA[19:0] & SBHE valid before ALE# negated
10
SA[19:0] & SBHE valid before MEMR#, MEMW# asserted
10a Memory access to 16-bit ISA Slave
10b Memory access to 8-bit ISA Slave
10
SA[19:0] & SHBE valid before SMEMR#, SMEMW# asserted
Note: The signal numbering refers to Figure 4-8
s
b
O
Min
5T
Max
Units
Cycles
5T
5T
1T
Cycles
Cycles
Cycles
2T
2T
Cycles
Cycles
55/108
1
STPC® ATLAS
Table 4-14. ISA Bus AC Timing
Name
Parameter
Min
10c Memory access to 16-bit ISA Slave
2T
10d Memory access to 8-bit ISA Slave
2T
10e
SA[19:0] & SBHE valid before IOR#, IOW# asserted
2T
11
ISACLK2X to IOW# valid
11a Memory access to 16-bit ISA Slave - 2BCLK
2T
11b Memory access to 16-bit ISA Slave - Standard 3BCLK
2T
11c Memory access to 16-bit ISA Slave - 4BCLK
2T
11d Memory access to 8-bit ISA Slave - 2BCLK
2T
11e
Memory access to 8-bit ISA Slave - Standard 3BCLK
2T
12
ALE# asserted before ALE# negated
1T
13
ALE# asserted before MEMR#, MEMW# asserted
13a Memory Access to 16-bit ISA Slave
2T
13b Memory Access to 8-bit ISA Slave
2T
13
ALE# asserted before SMEMR#, SMEMW# asserted
13c Memory Access to 16-bit ISA Slave
2T
13d Memory Access to 8-bit ISA Slave
2T
13e
ALE# asserted before IOR#, IOW# asserted
2T
14
ALE# asserted before AL[23:17]
14a Non compressed
15T
14b Compressed
15T
15
ALE# asserted before MEMR#, MEMW#, SMEMR#, SMEMW# negated
15a Memory Access to 16-bit ISA Slave- 4 BCLK
11T
15e Memory Access to 8-bit ISA Slave- Standard Cycle
11T
18a
ALE# negated before LA[23:17] invalid (non compressed)
14T
18a
ALE# negated before LA[23:17] invalid (compressed)
14T
22
MEMR#, MEMW# asserted before LA[23:17]
22a Memory access to 16-bit ISA Slave.
13T
22b Memory access to 8-bit ISA Slave.
13T
23
MEMR#, MEMW# asserted before MEMR#, MEMW# negated
23b Memory access to 16-bit ISA Slave Standard cycle
9T
23e Memory access to 8-bit ISA Slave Standard cycle
9T
23
SMEMR#, SMEMW# asserted before SMEMR#, SMEMW# negated
23h Memory access to 16-bit ISA Slave Standard cycle
9T
23l Memory access to 16-bit ISA Slave Standard cycle
9T
23
IOR#, IOW# asserted before IOR#, IOW# negated
23o Memory access to 16-bit ISA Slave Standard cycle
9T
23r Memory access to 8-bit ISA Slave Standard cycle
9T
24
MEMR#, MEMW# asserted before SA[19:0]
24b Memory access to 16-bit ISA Slave Standard cycle
10T
24d Memory access to 8-bit ISA Slave - 3BLCK
10T
24e Memory access to 8-bit ISA Slave Standard cycle
10T
24f Memory access to 8-bit ISA Slave - 7BCLK
10T
24
SMEMR#, SMEMW# asserted before SA[19:0]
24h
Memory access to 16-bit ISA Slave Standard cycle
10T
Note: The signal numbering refers to Figure 4-8
e
t
le
)
s
(
ct
u
d
o
r
P
e
t
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o
s
b
O
56/108
1
o
s
b
O
-
Max
Units
Cycle
Cycle
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
o
r
P
c
u
d
)
s
t(
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
STPC® ATLAS
Table 4-14. ISA Bus AC Timing
Name
Parameter
Min
24i
Memory access to 16-bit ISA Slave - 4BCLK
10T
24k
Memory access to 8-bit ISA Slave - 3BCLK
10T
24l
Memory access to 8-bit ISA Slave Standard cycle
10T
24
IOR#, IOW# asserted before SA[19:0]
24o
I/O access to 16-bit ISA Slave Standard cycle
19T
24r
I/O access to 16-bit ISA Slave Standard cycle
19T
25
MEMR#, MEMW# asserted before next ALE# asserted
25b
Memory access to 16-bit ISA Slave Standard cycle
10T
25d
Memory access to 8-bit ISA Slave Standard cycle
10T
25
SMEMR#, SMEMW# asserted before next ALE# asserted
25e
Memory access to 16-bit ISA Slave - 2BCLK
10T
25f
Memory access to 16-bit ISA Slave Standard cycle
10T
25h
Memory access to 8-bit ISA Slave Standard cycle
10T
25
IOR#, IOW# asserted before next ALE# asserted
25i
I/O access to 16-bit ISA Slave Standard cycle
10T
25k
I/O access to 16-bit ISA Slave Standard cycle
10T
26
MEMR#, MEMW# asserted before next MEMR#, MEMW# asserted
26b
Memory access to 16-bit ISA Slave Standard cycle
12T
26d
Memory access to 8-bit ISA Slave Standard cycle
12T
26
SMEMR#, SMEMW# asserted before next SMEMR#, SMEMW# asserted
26f
Memory access to 16-bit ISA Slave Standard cycle
12T
26h
Memory access to 8-bit ISA Slave Standard cycle
12T
26
IOR#, IOW# asserted before next IOR#, IOW# asserted
26i
I/O access to 16-bit ISA Slave Standard cycle
12T
26k
I/O access to 8-bit ISA Slave Standard cycle
12T
28
Any command negated to MEMR#, SMEMR#, MEMR#, SMEMW# asserted
28a
Memory access to 16-bit ISA Slave
3T
28b
Memory access to 8-bit ISA Slave
3T
28
Any command negated to IOR#, IOW# asserted
28c
I/O access to ISA Slave
3T
29a
MEMR#, MEMW# negated before next ALE# asserted
1T
29b
SMEMR#, SMEMW# negated before next ALE# asserted
1T
29c
IOR#, IOW# negated before next ALE# asserted
1T
33
LA[23:17] valid to IOCHRDY negated
33a
Memory access to 16-bit ISA Slave - 4 BCLK
8T
33b
Memory access to 8-bit ISA Slave - 7 BCLK
14T
34
LA[23:17] valid to read data valid
34b
Memory access to 16-bit ISA Slave Standard cycle
8T
34e
Memory access to 8-bit ISA Slave Standard cycle
14T
37
ALE# asserted to IOCHRDY# negated
37a
Memory access to 16-bit ISA Slave - 4 BCLK
6T
37b
Memory access to 8-bit ISA Slave - 7 BCLK
12T
37c
I/O access to 16-bit ISA Slave - 4 BCLK
6T
37d
I/O access to 8-bit ISA Slave - 7 BCLK
12T
Note: The signal numbering refers to Figure 4-8
e
t
le
)
s
(
ct
u
d
o
r
P
e
s
b
O
t
e
l
o
o
s
b
O
-
Max
Units
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
o
r
P
c
u
d
)
s
t(
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
57/108
1
STPC® ATLAS
Table 4-14. ISA Bus AC Timing
Name
38
Parameter
Min
Max
ALE# asserted to read data valid
38b
Memory access to 16-bit ISA Slave Standard Cycle
4T
38e
Memory access to 8-bit ISA Slave Standard Cycle
10T
38h
I/O access to 16-bit ISA Slave Standard Cycle
4T
38l
I/O access to 8-bit ISA Slave Standard Cycle
10T
41
SA[19:0] SBHE valid to IOCHRDY negated
41a
Memory access to 16-bit ISA Slave
6T
41b
Memory access to 8-bit ISA Slave
12T
41c
I/O access to 16-bit ISA Slave
6T
41d
I/O access to 8-bit ISA Slave
12T
42
SA[19:0] SBHE valid to read data valid
42b
Memory access to 16-bit ISA Slave Standard cycle
4T
42e
Memory access to 8-bit ISA Slave Standard cycle
10T
42h
I/O access to 16-bit ISA Slave Standard cycle
4T
42l
I/O access to 8-bit ISA Slave Standard cycle
10T
47
MEMR#, MEMW#, SMEMR#, SMEMW#, IOR#, IOW# asserted to IOCHRDY negated
47a
Memory access to 16-bit ISA Slave
2T
47b
Memory access to 8-bit ISA Slave
5T
47c
I/O access to 16-bit ISA Slave
2T
47d
I/O access to 8-bit ISA Slave
5T
48
MEMR#, SMEMR#, IOR# asserted to read data valid
48b
Memory access to 16-bit ISA Slave Standard Cycle
2T
48e
Memory access to 8-bit ISA Slave Standard Cycle
5T
48h
I/O access to 16-bit ISA Slave Standard Cycle
2T
48l
I/O access to 8-bit ISA Slave Standard Cycle
5T
54
IOCHRDY asserted to read data valid
54a
Memory access to 16-bit ISA Slave
1T(R)/2T(W)
54b
Memory access to 8-bit ISA Slave
1T(R)/2T(W)
54c
I/O access to 16-bit ISA Slave
1T(R)/2T(W)
54d
I/O access to 8-bit ISA Slave
1T(R)/2T(W)
IOCHRDY asserted to MEMR#, MEMW#, SMEMR#, SMEMW#,
1T
55a
IOR#, IOW# negated
55b
IOCHRY asserted to MEMR#, SMEMR# negated (refresh)
1T
56
IOCHRDY asserted to next ALE# asserted
2T
57
IOCHRDY asserted to SA[19:0], SBHE invalid
2T
58
MEMR#, IOR#, SMEMR# negated to read data invalid
0T
59
MEMR#, IOR#, SMEMR# negated to data bus float
0T
61
Write data before MEMW# asserted
61a
Memory access to 16-bit ISA Slave
2T
Memory access to 8-bit ISA Slave (Byte copy at end of
2T
61b
start)
61
Write data before SMEMW# asserted
61c
Memory access to 16-bit ISA Slave
2T
61d
Memory access to 8-bit ISA Slave
2T
61
Write Data valid before IOW# asserted
Note: The signal numbering refers to Figure 4-8
c
u
d
e
t
le
)
s
(
ct
u
d
o
r
P
e
t
e
l
o
s
b
O
58/108
1
o
s
b
O
-
o
r
P
Units
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
)
s
t(
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
STPC® ATLAS
Table 4-14. ISA Bus AC Timing
Name
Parameter
61e
I/O access to 16-bit ISA Slave
61f
I/O access to 8-bit ISA Slave
64a
MEMW# negated to write data invalid - 16-bit
64b
MEMW# negated to write data invalid - 8-bit
64c
SMEMW# negated to write data invalid - 16-bit
64d
SMEMW# negated to write data invalid - 8-bit
64e
IOW# negated to write data invalid
MEMW# negated to copy data float, 8-bit ISA Slave, odd Byte
64f
by ISA Master
IOW# negated to copy data float, 8-bit ISA Slave, odd Byte by
64g
ISA Master
Note: The signal numbering refers to Figure 4-8
Min
2T
2T
1T
1T
1T
1T
1T
Max
1T
Cycles
1T
Cycles
c
u
d
e
t
le
)
s
(
ct
Units
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
Cycles
)
s
t(
o
r
P
o
s
b
O
-
u
d
o
r
P
e
t
e
l
o
s
b
O
59/108
1
STPC® ATLAS
4.5.7. LOCAL BUS INTERFACE
Figure 4-3 to Figure 4-12 and Table 4-16 list the
AC characteristics of the Local Bus interface.
Figure 4-9. Synchronous Read Cycle
HCLK
PA[ ] bus
Tsetup
Tactive
Thold
CSx#
BE#[1:0]
c
u
d
PRD#
e
t
le
PD[15:0]
)
s
(
ct
u
d
o
r
P
e
t
e
l
o
s
b
O
60/108
1
o
s
b
O
-
o
r
P
)
s
t(
STPC® ATLAS
Figure 4-10. Asynchronous Read Cycle
HCLK
PA[ ] bus
Tsetup
Tend
Thold
CSx#
BE#[1:0]
c
u
d
PRD#
PD[15:0]
e
t
le
PRDY
Figure 4-11. Synchronous Write Cycle
)
s
(
ct
HCLK
t
e
l
o
CSx#
o
r
P
o
s
b
O
-
u
d
o
r
P
e
PA[ ] bus
)
s
t(
Tsetup
Tactive
Thold
s
b
O
BE#[1:0]
PWR#
PD[15:0]
61/108
1
STPC® ATLAS
Figure 4-12. Asynchronous Write Cycle
HCLK
PA[ ] bus
Tsetup
Tend
Thold
CSx#
BE#[1:0]
PWR#
c
u
d
PD[15:0]
e
t
le
PRDY
Table 4-15. Local Bus cycle lenght
Cycle
Memory (FCSx#)
Peripheral (IOCSx#)
o
r
P
e
Tsetup
4 + Vh
4 + Vh
c
u
d
(t s)
o
r
P
o
s
b
O
-
The Table 4-15. below refers to Vh, Va, Vs which
are the register value for Setup time, Active Time
Tactive
2 + Va
2 + Va
)
s
t(
and Hold time, as described in the Programming
Manual.
Thold
4 + Vs
4 + Vs
Tend
4
4
Unit
HCLK
HCLK
Table 4-16. Local Bus Interface AC Timing
Name
Parameters
HCLK to PA bus
HCLK to PD bus
HCLK to FCS#[1:0]
HCLK to IOCS#[3:0]
HCLK to PWR#, PRD#
HCLK to BE#[1:0]
PD[15:0] Input setup to HCLK
PD[15:0] Input hold to HCLK
PRDY Input setup to HCLK
PRDY Input hold to HCLK
t
e
l
o
s
b
O
62/108
1
Min
2
2
Max
15
15
15
15
15
15
4
4
-
Units
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
STPC® ATLAS
4.5.8 PCMCIA INTERFACE
Table 4-17 lists the AC characteristics of the
PCMCIA interface.
Table 4-17. PCMCIA Interface AC Timing
Name
t27
t28
t29
t30
t31
t32
t33
t34
t35
t36
t37
t38
Parameters
Input setup to ISACLK2X
Input hold from ISACLK2X
ISACLK2X to IORD
ISACLK2X to IORW
ISACLK2X to AD[25:0]
ISACLK2X to OE#
ISACLK2X to WE#
ISACLK2X to DATA[15:0]
ISACLK2X to INPACK
ISACLK2X to CE1#
ISACLK2X to CE2#
ISACLK2X to RESET
Min
24
5
2
2
0
2
7
7
2
Max
55
55
25
55
55
35
55
65
65
55
c
u
d
e
t
le
)
s
(
ct
Units
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
)
s
t(
o
r
P
o
s
b
O
-
u
d
o
r
P
e
t
e
l
o
s
b
O
63/108
1
STPC® ATLAS
4.5.9 IDE INTERFACE
Figure 4-13, Figure 4-14 and Table 4-18 lists the
AC characteristics of the IDE interface.
Figure 4-13. IDE PIO timing diagram
CS#,DA[2:0]
Thold
DIOR#,DIOW#
Tsetup
DD[15:0]
IORDY
c
u
d
Figure 4-14. IDE DMA timing diagram
e
t
le
CS#
REQ
)
s
(
ct
ACK#
u
d
o
DIOR#,DIOW#
)
s
t(
o
r
P
o
s
b
O
Thold
Tsetup
r
P
e
DD[15:0] read
t
e
l
o
DD[15:0] write
s
b
O
Table 4-18. IDE Interface Timing
Name
Tsetup
Thold
64/108
1
Parameters
DD[15:0] setup to PIOR#/SIOR# falling
DD[15:0} hold to PIOR#/SIOR# falling
Min
15
0
Max
-
Units
ns
ns
STPC® ATLAS
4.5.10 TFT INTERFACE
Table 4-19 lists the AC characteristics of the TFT
interface.
Table 4-19. TFT Interface Timings
Name
Parameters
DCLK (input) to R[5:0], G[5:0], B[5;0]
DCLK (input) to FPLINE
DCLK (input) to FPFRAME
DCLK (output) to R[5:0], G[5:0], B[5;0]
DCLK (output) to FPLINE
DCLK (output) to FPFRAME
Min
Max
15
15
15
Units
nS
nS
nS
nS
nS
nS
4.5.11 USB INTERFACE
The USB interface integrated into the STPC
device is compliant with the USB 1.1 standard.
4.5.12 KEYBOARD & MOUSE INTERFACES
c
u
d
Table 4-20 and Table 4-21 list the AC
characteristics of the Keyboard and Mouse
interfaces.
Table 4-20. Keyboard Interface AC Timing
Name
Parameters
Input setup to KBCLK
Input hold to KBCLK
KBCLK to KBDATA
e
t
le
Table 4-21. Mouse Interface AC Timing
Name
Parameters
Input setup to MCLK
Input hold to MCLK
MCLK to MDATA
)
s
(
ct
o
s
b
O
-
o
r
P
)
s
t(
Min
5
1
-
Max
12
Units
nS
nS
nS
Min
5
1
-
Max
12
Units
nS
nS
nS
Min
0
0
0
Max
-
Units
nS
nS
nS
u
d
o
4.5.13 IEEE1284 INTERFACE
r
P
e
Table 4-22 lists the AC characteristics of the
Keyboard and Mouse interfaces.
Table 4-22. Parallel Interface AC Timing
t
e
l
o
Name
s
b
O
Parameters
STROBE# to BUSY setup
PD bus to AUTPFD# hold
PB bus to BUSY setup
65/108
1
STPC® ATLAS
4.5.14 JTAG INTERFACE
Figure 4-15 lists the AC characteristics of the
JTAG interface.
Table 4-23. JTAG AC Timings
Name
Treset
Tcycle
Tjset
Tjhld
Tjset
Tjhld
Tjout
Tpset
Tphld
Tpout
Parameter
TRST pulse width
TCLK period
TCLK rising time
TCLK falling time
TMS setup time
TMS hold time
TDI setup time
TDI hold time
TCLK to TDO valid
STPC pin setup time
STPC pin hold time
TCLK to STPC pin valid
Min
1
400
Max
20
20
200
200
200
200
30
30
30
30
c
u
d
Figure 4-15. JTAG timing diagram
Treset
e
t
le
TRST
TCK
)
s
(
ct
u
d
o
TMS,TDI
TDO
t
e
l
o
r
P
e
s
b
O
Tjset
o
s
b
O
-
o
r
P
Tcycle
Tjhld
Tjout
STPC.input
Tpset Tphld
STPC.output
Tpout
66/108
1
Unit
Tcycle
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
)
s
t(
STPC® ATLAS
5 MECHANICAL DATA
Dimensions are shown in Figure 5-2, Table 5-1.
and Figure 5-3, Table 5-2..
5.1. 516-PIN PACKAGE DIMENSION
The pin numbering for the STPC 516-pin Plastic
BGA package is shown in Figure 5-1.
Figure 5-1. 516-Pin PBGA Package - Top View
1
3
2
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
7
6
9
8
11
10
13
12
15
14
17
16
19
18
21
20
23
22
25
24
26
c
u
d
e
t
le
)
s
(
ct
o
r
P
o
s
b
O
-
u
d
o
r
P
e
t
e
l
o
s
b
O
5
4
1
3
2
5
4
7
6
9
8
11
10
13
12
15
14
17
16
19
18
21
20
23
22
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
)
s
t(
25
24
26
67/108
1
STPC® ATLAS
Figure 5-2. 516-pin PBGA Package - PCB Dimensions
A1 Ball Pad Corner
A
B
A
c
u
d
e
t
le
)
s
(
ct
u
d
o
r
P
e
o
r
P
o
s
b
O
-
D
E
F
Detail
t
e
l
o
s
b
O
)
s
t(
C G
Table 5-1. 516-pin PBGA Package - PCB Dimensions
Symbols
A
B
C
D
E
68/108
1
Min
34.80
1.22
0.60
1.57
0.15
mm
Typ
35.00
1.27
0.76
1.62
0.20
Max
35.20
1.32
0.90
1.67
0.25
Min
1.370
0.048
0.024
0.062
0.006
inches
Typ
1.378
0.050
0.030
0.064
0.008
Max
1.386
0.052
0.035
0.066
0.001
STPC® ATLAS
Table 5-1. 516-pin PBGA Package - PCB Dimensions
F
G
0.05
0.75
0.10
0.80
0.15
0.85
0.002
0.030
0.004
0.032
0.006
0.034
Figure 5-3. 516-pin PBGA Package - Dimensions
C
F
D
E
Solderball
Solderball after collapse
c
u
d
)
s
t(
o
r
P
B
e
t
le
G
A
)
s
(
ct
o
s
b
O
-
Table 5-2. 516-pin PBGA Package - Dimensions
Symbols
A
B
C
D
E
F
G
u
d
o
r
P
e
t
e
l
o
s
b
O
Min
0.50
1.12
0.60
0.52
0.63
0.60
mm
Typ
0.56
1.17
0.76
0.53
0.78
0.63
30.0
Max
0.62
1.22
0.92
0.54
0.93
0.66
Min
0.020
0.044
0.024
0.020
0.025
0.024
inches
Typ
0.022
0.046
0.030
0.021
0.031
0.025
11.8
Max
0.024
0.048
0.036
0.022
0.037
0.026
69/108
1
STPC® ATLAS
5.2. 516-PIN PACKAGE THERMAL DATA
The structure in shown in Figure 5-4.
516-pin PBGA package has a Power Dissipation
Capability of 4.5W which increases to 6W when
used with a Heatsink.
Thermal dissipation options are illustrated in
Figure 5-5 and Figure 5-6.
Figure 5-4. 516-Pin PBGA Structure
Signal layers
Power & Ground layers
Thermal balls
c
u
d
Figure 5-5. Thermal Dissipation Without Heatsink
e
t
le
Board
)
s
(
ct
Ambient
r
P
e
u
d
o
Case
t
e
l
o
bs
O
70/108
1
Board dimensions:
- 10.2 cm x 12.7 cm
- 4 layers (2 for signals, 1 GND, 1VCC)
Junction
6
Junction
6
Board
Case
8.5
125
Rjb
Board
Rba
o
r
P
o
s
b
O
-
Rca
Rjc
)
s
t(
Ambient
Ambient
Rja = 13 °C/W
The PBGA is centred on board
There are no other devices
1 via pad per ground ball (8-mil wire)
40% copper on signal layers
Copper thickness:
- 17µm for internal layers
- 34µm for external layers
Airflow = 0
Board temperature taken at the centre balls
STPC® ATLAS
Figure 5-6. Thermal Dissipation With Heatsink
Board
c
u
d
Rca
Case
3
Rjc
The PBGA is centred on board
There are no other devices
1 via pad per ground ball (8-mil wire)
40% copper on signal layers
6
Board
Junction
Case
8.5
50
Rjb
Board
Ambient
Rba
b
O
-
Rja = 9.5 °C/W
e
t
le
o
r
P
Copper thickness:
- 17µm for internal layers
- 34µm for external layers
so
Ambient
)
s
(
ct
)
s
t(
Board dimensions:
- 10.2 cm x 12.7 cm
- 4 layers (2 for signals, 1 GND, 1VCC)
Junction
Ambient
Airflow = 0
Board temperature taken at the centre balls
Heat sink is 11.1°C/W
u
d
o
r
P
e
t
e
l
o
s
b
O
71/108
1
STPC® ATLAS
5.3. SOLDERING RECOMMENDATIONS
High quality, low defect soldering requires
identifying the optimum temperature profile for
reflowing the solder paste, therefore optimizing the
process. The heating and cooling rise rates must
be compatible with the solder paste and
components. A typical profile consists of a
preheat, dryout, reflow and cooling sections.
The most critical parameter in the preheat
section is to minimize the rate of temperature rise
to less than 2°C / second, in order to minimize
thermal
shock
on
the
semi-conductor
components.
Dryout section is used primarily to ensure that
the solder paste is fully dried before hitting reflow
temperatures.
Solder reflow is accomplished in the reflow zone,
where the solder paste is elevated to a
temperature greater than the melting point of the
solder. Melting temperature must be exceeded by
approximately 20°C to ensure quality reflow.
In reality the profile is not a line, but rather a range
of temperatures all solder joints must be
exposed. The total temperature deviation from
component thermal mismatch, oven loading and
oven uniformity must be within the band.
Figure 5-7. Reflow soldering temperature range
Temperature ( °C )
c
u
d
250
e
t
le
200
150
100
)
s
(
ct
50
PREHEAT
0
0
r
P
e
t
e
l
o
s
b
O
72/108
1
u
d
o
DRYOUT
)
s
t(
o
r
P
o
s
b
O
-
REFLOW
COOLING
Time ( s )
240
STPC® ATLAS
6 DESIGN GUIDELINES
6.1. TYPICAL APPLICATIONS
The STPC Atlas is well suited for many
applications.
Some
of
the
possible
implementations are described below.
6.1.1. THIN CLIENT
A Thin-Client is a terminal running ICATM (Citrix)
or RDPTM (Microsoft) protocol. The display is
computed by the server and sent in a compressed
way to the terminal for display. The same
streaming approach is used for sending the
keyboard/mouse/USB data to the server.
These protocols have room for dedicated data
channels in case the terminal is not ’thin’ and can
execute locally some applications, hence
optimizing the bandwidth usage. For example, if a
terminal has browsing or MPEG decoding
capability, the server will provide internet source
files or MPEG streaming.
The same hardware can run X-terminal protocol
and can be reconfigured by the server when
booting on the network by uploading a different
OS and application.
Figure 6-1. Thin-Client - Block Diagram
SDRAM
VGA
FLASH
16
LAN
PCI
MPEG
DECODER
CCIR
Audio
c
u
d
64
)
s
(
ct
IDE / PCI
TFT
e
t
le
STPC
ATLAS
o
s
b
O
-
)
s
t(
o
r
P
USB
IEEE1284
Kbd / Mouse
u
d
o
r
P
e
t
e
l
o
s
b
O
73/108
1
STPC® ATLAS
6.1.2. INTERNET TERMINAL
The internet terminal described here is an
optimized implementation where the STPC Atlas
board is integrated into the CRT itself. The
advantages are a reduced overall cost and a good
image definition.
The STPC Atlas platform being integrated into the
monitor itself enables the choice of a limited
amount of horizontal frequencies and simplifies
the CRT driving stage:
- 1024x768: 56.5KHz horizontal, 70Hz vertical
- 800x600: 53.7KHz horizontal, 85Hz vertical
Like for the Thin-Client, an external MPEG
decoder can be connected to the STPC Atlas
through the PCI bus and the Video Input Port.
The same concept can be applied using a TFT
display instead of a CRT.
Figure 6-2. Internet Terminal - Block Diagram
VSYNC
SDRAM
64
VBOOSTER
FLASH
16
HSYNC
PCI
MODEM
r,g,B
3
E2
PROM
IEEE1284
P
e
let
GPIOs
KEY-
I2C
KEY+
SEL
)
s
(
ct
u
d
o
r
P
e
s
b
O
74/108
1
3
QuAD
DAC
b
O
-
so
DC
rESTORING
c
u
d
ro
3
USB
Kbd / Mouse
)
s
t(
YOKE
sTPC
ATLAS
IDE / PCI
t
e
l
o
H
stv2001
RS232
SmartCard
Audio
YOKE
r,g,B
TDA9535
3
TILT
3
STPC® ATLAS
6.2. STPC CONFIGURATION
Table 6-2. Main STPC modes
The STPC is a very flexible product thanks to
decoupled clock domains and to strap options
enabling a user-optimized configuration.
As some trade off are often necessary, it is
important to do an analysis of the application
needs prior to design a system based on this
product. The applicative constraints are usually
the following:
- CPU performance
- graphics / video performances
- power consumption
- PCI bandwidth
- booting time
- EMC
Some other elements can help to tune the choice:
- Code size of CPU Consuming tasks
- Data size and location
On the STPC side, the configurable parameters
are the following:
- Synchronous / asynchronous mode
- HCLK speed
- MCLK speed
- Local Bus / ISA bus
6.2.1. LOCAL BUS / ISA BUS
)
s
(
ct
u
d
o
Need
Legacy I/O device (Floppy, ...), Super I/O
DMA capability (Soundblaster)
Flash, SRAM, basic I/O device
Fast boot
Boot flash of 4MB or more
Programmable Chip Select
r
P
e
t
e
l
o
Mode
1
2
Synchronous
Asynchronous
HCLK
MHz
66
66
CPU clock
clock ratio
133 (x2)
133 (x2)
MCLK
MHz
66
90
The advantage of the synchronous mode
compared to the asynchronous mode is a lower
latency when accessing SDRAM from the CPU or
the PCI (saves 4 MCLK cycles for the first access
of the burst). For the same CPU to Memory
transfer performance, MCLK has to be roughly
higher by 20MHz between SYNC and ASYNC
modes to get the same system performance level
(example: 66MHz SYNC = 86MHz ASYNC) .
In all cases, use SDRAM with CAS Latency equals
to 2 (CL2) for the best performances.
)
s
t(
The advantage of the asynchronous mode is the
capability to reprogram the MCLK speed on the fly.
This could help for applications where power
consumption must be optimized.
c
u
d
o
r
P
The last, and more complex, information to
consider is the behaviour of the software. In case
high CPU or FPU computation is needed, it is
sometime better to be in DX2-133/MCLK=66
synchronous mode than DX2-133/MCLK=90
asynchronous mode. This depends on the locality
of the number crunching code and the amount of
data manipulated.
e
t
le
o
s
b
O
-
The selection between the ISA bus and the Local
Bus is relatively simple. The first one is a standard
bus but slow. The Local Bus is fast and
programmable but doesn't support any DMA nor
external master mechanisms. The Table 6-1
below summarize the selection:
Table 6-1. Bus mode selection
C
Selection
ISA Bus
ISA Bus
Local Bus
Local Bus
Local Bus
Local Bus
s
b
O
Before implementing a function requiring DMA
capability on the ISA bus, it is recommended to
check if it exists on PCI, or if it can be implemented
differently, in order to use the local bus mode.
6.2.2. CLOCK CONFIGURATION
The CPU clock and the memory clock are
independent unless the "synchronous mode" strap
option is set (see the STRAP OPTIONS chapter).
The potential clock configurations are then
The Table 6-3 below gives some examples. The
right column correspond to the configuration
number as described in Table 6-2 :
Table 6-3. Clock mode selection
Constraints
Need CPU power
Critical code fits into L1 cache
Need CPU power
Code or data does not fit into L1 cache
Need flexible SDRAM speed
C
1
3
2
Obviously, the values for HCLK or MCLK can be
reduced compared to Table 6-2 in case there is no
need to push the device at its limits, or when
avoiding to use specific frequency ranges (FM
radio band for example).
6.3. ARCHITECTURE RECOMMENDATIONS
This
section
describes
the
recommend
implementations for the STPC interfaces. For
more
details,
download
the
Reference
Schematics from the STPC web site.
75/108
1
STPC® ATLAS
An appropriate decoupling of the various STPC
power pins is mandatory for optimum behaviour.
When insufficient, the integrity of the signals is
deteriorated, the stability of the system is reduced
and EMC is increased.
minimum. The use of multiple capacitances with
values in decade is the best (for example: 10pF,
1nF, 100nF, 10uF), the smallest value, the closest
to the power pin. Connecting the various digital
power planes through capacitances will reduce
furthermore the overall impedance and electrical
noise.
6.3.1.1. PLL decoupling
6.3.2. 14MHZ OSCILLATOR STAGE
This is the most important as the STPC clocks are
generated from a single 14MHz stage using
multiple PLLs which are highly sensitive analog
cells. The frequencies to filter are the 25-50 KHz
range which correspond to the internal loop
bandwidth of the PLL and the 10 to 100 MHz
frequency of the output. PLL power pins can be
tied together to simplify the board layout.
The 14.31818 MHz oscillator stage can be
implemented using a quartz, which is the preferred
and cheaper solution, or using an external 3.3V
oscillator.
6.3.1. POWER DECOUPLING
Figure 6-3. PLL decoupling
The crystal must be used in its series-cut
fundamental mode and not in overtone mode. It
must have an Equivalent Series Resistance (ESR,
sometimes referred to as Rm) of less than 50
Ohms (typically 8 Ohms) and a shunt capacitance
(Co) of less than 7 pF. The balance capacitors of
16 pF must be added, one connected to each pin,
as described in Figure 6-4.
c
u
d
PWR
VDD_PLL
In the event of an external oscillator providing the
master clock signal to the STPC device, the
LVTTL signal should be connected to XTALI, as
described in Figure 6-4.
100nF 47uF
VSS_PLL
GND
Connections must be as short as possible
6.3.1.2. Decoupling of 3.3V and Vcore
e
t
le
o
r
P
As this clock is the reference for all the other onchip
generated
clocks,
it
is strongly
recommended to shield this stage, including the
2 wires going to the STPC balls, in order to reduce
the jitter to the minimum and reach the optimum
system stability.
o
s
b
O
-
A power plane for each of these supplies with one
decoupling capacitance for each power pin is the
)
s
(
ct
Figure 6-4. 14.31818 MHz stage
u
d
o
r
P
e
XTALI
t
e
l
o
s
b
O
76/108
1
15pF
)
s
t(
XTALO
XTALI
1MOHM
XTALO
3.3V
15pF
STPC® ATLAS
memory and extends to the top of populated
SDRAM. Bank 0 must always be populated.
6.3.3. SDRAM
The STPC provides all the signals for SDRAM
control. Up to 128 MBytes of main memory are
supported. All Banks must be 64 bits wide. Up to 4
memory banks are available when using 16Mbit
devices. Only up to 2 banks can be connected
when using 64Mbit and 128Mbit components due
to the reallocation of CS2# and CS3# signals. This
is described in Table 6-4 and Table 6-5.
Graphics memory resides at the beginning of Bank
0. Host memory begins at the top of graphics
Figure 6-5, Figure 6-6 and Figure 6-7 show some
typical implementations.
The purpose of the serial resistors is to reduce
signal oscillation and EMI by filtering line
reflections. The capacitance in Figure 6-5 has a
filtering effect too, while it is used for propagation
delay compensation in the 2 other figures.
Figure 6-5. One Memory Bank with 4 Chips (16-bit)
MCLKI
Length(MCLKI+1ns(+/- 0.5ns)) = Length(MCLKx)
with x = {A,B,C,D}
c
u
d
MCLKO
10pF
Reference Knot
CS0#
MA[12:0]
BA[1:0]
RAS0#
CAS0#
WE#
)
s
(
ct
DQM[7:0]
MD[63:0]
MCLKD
e
t
le
MCLKC
o
s
b
O
DQM[7:6]
MD[63:48]
DQM[5:4]
MD[47:32]
o
r
P
)
s
t(
MCLKB
MCLKA
DQM[3:2]
MD[31:16]
DQM[1:0]
MD[15:0]
u
d
o
r
P
e
Refer to Section 4.5.3. for detailed timing constraints.
For other implementations like 32-bit SDRAM
devices, refers to the SDRAM controller signal
t
e
l
o
multiplexing and address mapping described in
the following Table 6-4 and Table 6-5.
s
b
O
77/108
1
STPC® ATLAS
Figure 6-6. One Memory Banks with 8 Chips (8-bit)
MCLKI
10pF
Length(MCLKI+1ns(+/- 0.5ns)) = Length(MCLKx)
with x = {A,B,C,D,E,F,G,H}
MCLKO
CY2305
H
G
F
E
D
C
B
CS0#
MA[12:0]
BA[1:0]
RAS0#
CAS0#
WE#
DQM[7:0]
MD[63:0]
c
u
d
DQM[7]
MD[63:56]
e
t
le
Refer to Section 4.5.3. for detailed timing constraints.
)
s
(
ct
u
d
o
r
P
e
t
e
l
o
s
b
O
78/108
1
o
s
b
O
-
o
r
P
A
)
s
t(
DQM[1] DQM[0]
MD[15:8] MD[7:0]
STPC® ATLAS
Figure 6-7. Two Memory Banks with 8 Chips (8-bit)
MCLKI
Length(MCLKI+1ns(+/- 0.5ns)) = Length(MCLKxy)
x = {A,B,C,D,E,F,G,H}
with
y = {0,1}
22pF
MCLKO
CY2305
H0
H1 G0
G1 F0
F1 E0
E1 D0
D1 C0
C1 B0
CS1#
CS0#
MA[12:0]
BA[1:0]
RAS0#
CAS0#
WE#
DQM[7:0]
MD[63:0]
c
u
d
DQM[7]
MD[63:56]
e
t
le
Refer to Section 4.5.3. for detailed timing constraints.
Table 6-4. DIMM Pinout
SDRAM Density
Internal Banks
DIMM Pin Number
...
123
126
39
122
16 Mbit
2 Banks
(t s)
MA[10:0]
BA0 (MA11)
o
r
P
e
c
u
d
B1 A0
o
s
b
O
-
o
r
P
A1
)
s
t(
DQM[1] DQM[0]
MD[15:8] MD[7:0]
64/128 Mbit
2 Banks
64/128 Mbit
4 Banks
STPC I/F
MA[10:0]
MA11
MA12
BA0 (MA13)
MA[10:0]
MA11
BA1 (MA12)
BA0 (MA13)
MA[10:0]
CS2# (MA11)
CS3# (MA12)
CS3# (BA1)
BA0
Table 6-5. Address Mapping
t
e
l
o
Address Mapping: 16 Mbit - 2 internal banks
STPC I/F
BA0
MA10 MA9
RAS Address A11
A22
A21
CAS Address A11
0
A24
Address Mapping: 64/128 Mbit - 2 internal banks
STPC I/F
BA0 MA12 MA11 MA10 MA9
RAS Address A11 A24
A23
A22
A21
CAS Address A11 0
0
0
A26
Address Mapping: 64/128 Mbit - 4 internal banks
STPC I/F
BA0 BA1 MA11 MA10 MA9
RAS Address A11 A12
A24
A23
A22
CAS Address A11 A12
0
0
A26
s
b
O
MA8
A2
A23
MA7
A19
A10
MA6
A18
A9
MA5
A17
A8
MA4
A16
A7
MA3
A15
A6
MA2
A14
A5
MA1
A13
A4
MA0
A12
A3
MA8
A20
A25
MA7
A19
A10
MA6
A18
A9
MA5
A17
A8
MA4
A16
A7
MA3
A15
A6
MA2
A14
A5
MA1
A13
A4
MA0
A12
A3
MA8
A21
A25
MA7
A20
A10
MA6
A19
A9
MA5
A18
A8
MA4
A17
A7
MA3
A16
A6
MA2
A15
A5
MA1
A14
A4
MA0
A13
A3
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STPC® ATLAS
6.3.4. PCI BUS
The PCI bus is always active and the following
control signals must be pulled-up to 3.3V or 5V
through 8K2 resistors even if this bus is not
connected to an external device: FRAME#,
TRDY#, IRDY#, STOP#, DEVSEL#, LOCK#,
SERR#, PERR#, PCI_REQ#[2:0].
PCI_CLKO must be connected to PCI_CLKI
through a 10 to 33 Ohms resistor. Figure 6-8
shows a typical implementation.
For more information on layout constraints, go to
the place and route recommendations section.
Figure 6-8. Typical PCI clock routing
PCICLKI
0 - 33pF
PCICLKA
PCICLKB
PCICLKO
PCICLKC
0 - 22
10 - 33
In the case of higher clock load it is recommended
to use a zero-delay clock buffer as described in
Figure 6-9. This approach is also recommended
)
s
(
ct
o
s
b
O
-
u
d
o
r
P
e
t
e
l
o
PCICLKO
PLL
Device A
s
b
O
Device B
Device C
Device D
CY2305
Implementation
80/108
1
Device B
c
u
d
Device C
o
r
P
)
s
t(
when implementing the delay on PCICLKI
according to the PCI section of the Electrical
Specifications chapter.
Figure 6-9. PCI clock routing with zero-delay clock buffer
PCICLKI
e
t
le
Device A
STPC® ATLAS
6.3.5. LOCAL BUS
The local bus has all the signals to directly connect
flash devices or I/O devices.
Figure 6-10 describes how to connect a 16-bit boot
flash (the corresponding strap options must be set
accordingly).
Figure 6-10. Typical 16-bit boot flash implementation
3V3
STS
PA[22:1]
FCS0#
PRD#
PWR#
22
PD[15:0]
16
A[22:1]
EO
G
W
DQ[15:0]
RP
SYSRSTI#
A0
BYTE
VPEN
LE
R
M58LW064D
STPC
uc
)
s
t(
GND
d
o
r
RESET#
P
e
let
)
s
(
ct
o
s
b
O
-
u
d
o
r
P
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t
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s
b
O
81/108
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STPC® ATLAS
6.3.6. IPC
Most of the IPC signals are multiplexed: Interrupt
inputs, DMA Request inputs, DMA Acknowledge
outputs. The figure below describes a complete
implementation of the IRQ[15:0] time-multiplexing.
When an interrupt line is used internally, the
corresponding input can be grounded. In most of
the embedded designs, only few interrupts lines
are necessary and the glue logic can be simplified.
Figure 6-11. Typical IRQ multiplexing
74x153
IRQ[0]
IRQ[1]
IRQ[2]
IRQ[3]
IRQ[4]
IRQ[5]
IRQ[6]
IRQ[7]
Timer 0
Keyboard
Slave PIC
COM2/COM4
COM1/COM3
LPT2
Floppy
LPT1
1C0
1C1
1C2
1C3
2C0
2C1
2C2
2C3
A
B
1Y
IRQ_MUX[0]
2Y
IRQ_MUX[1]
1G 2G
RTC
Mouse
FPU
PCI / IDE
PCI / IDE
u
d
o
r
P
e
t
e
l
o
s
b
O
)
s
(
ct
o
s
b
O
-
Floppy
IRQ[8]
IRQ[9]
IRQ[10]
IRQ[11]
IRQ[12]
IRQ[13]
IRQ[14]
IRQ[15]
ISA_CLK2X
ISA_CLK
When the interface is integrated into the STPC,
the corresponding interrupt line can be grounded
as it is connected internally.
82/108
1
e
t
le
c
u
d
)
s
t(
o
r
P
74x153
1C0
1C1
1C2
1C3
2C0
2C1
2C2
2C3
A
B
1Y
IRQ_MUX[2]
2Y
IRQ_MUX[3]
1G 2G
For example, if the integrated IDE controller is
activated, the IRQ[14] and IRQ[15] inputs can be
grounded.
STPC® ATLAS
The figure below describes a complete
implementation of the external glue logic for DMA
Request time-multiplexing and DMA Acknowledge
demultiplexing. Like for the interrupt lines, this
logic can be simplified when only few DMA
channels are used in the application.
This glue logic is not needed in Local bus mode as
it does not support DMA transfers.
Figure 6-12. Typical DMA multiplexing and demultiplexing
74x153
DRQ[0]
DRQ[1]
DRQ[2]
DRQ[3]
DRQ[4]
DRQ[5]
DRQ[6]
DRQ[7]
ISA, Refresh
ISA, PIO
ISA, FDC
ISA, PIO
Slave DMAC
ISA
ISA
ISA
1C0
1C1
1C2
1C3
2C0
2C1
2C2
2C3
A
B
1Y
DREQ_MUX[0]
2Y
DREQ_MUX[1]
1G 2G
ISA_CLK2X
ISA_CLK
DMA_ENC[0]
DMA_ENC[1]
DMA_ENC[2]
o
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c
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(t s)
e
t
le
74x138
o
s
b
O
A
B
C
Y0#
Y1#
Y2#
Y3#
Y4#
Y5#
Y6#
Y7#
c
u
d
)
s
t(
o
r
P
DACK0#
DACK1#
DACK2#
DACK3#
DACK5#
DACK6#
DACK7#
G1
G2A G2B
s
b
O
83/108
1
STPC® ATLAS
describes how to implement the external glue logic
to demultiplex the IDE and ISA interfaces. In Local
Bus mode the two buffers are not needed and the
NAND gates can be simplified to inverters.
6.3.7. IDE / ISA DYNAMIC DEMULTIPLEXING
Some of the ISA bus signals are dynamically
multiplexed to optimize the pin count. Figure 6-13
Figure 6-13. Typical IDE / ISA Demultiplexing
MASTER#
B
A
74xx245
DIR
ISAOE#
OE
STPC bus / DD[15:0]
LA[20]
PCS1#
LA[21]
PCS3#
LA[22]
SCS1#
LA[23]
SCS3#
6.3.8. BASIC AUDIO USING IDE INTERFACE
e
t
le
Figure 6-14. Basic audio on IDE
16
o
r
P
e
t
e
l
o
bs
O
Speaker
STPC
)
s
(
ct
du
o
r
P
o
s
b
O
-
D[15:0]
CS#
WR#
A/B
*
PR
RST
Q
D
Q
PR
Q
Q
RST
74xx74
Vcc
Note * : the inverter can be removed when the DAC CS# is directly connected to GND
84/108
1
Right
Audio Out
Left
Stereo DAC
Vcc
Vcc
D
c
u
d
)
s
t(
Figure 6-14). This low cost solution is not CPU
consuming thanks to the DMA controller
implemented in the IDE controller and can
generate 16-bit stereo sound. The clock speed is
programmable when using the speaker output.
When the application requires only basic audio
capabilities, an audio DAC on the IDE interface
can avoid using a PCI-based audio device(see
DD[15:0]
PCS1
PDIOW#
PDRQ
SYSRSTO#
RMRTCCS#
KBCS#
RTCRW#
RTCDS
SA[19:8]
STPC® ATLAS
6.3.9. VGA INTERFACE
The STPC integrates a voltage reference and
video buffers. The amount of external devices is
then limited to the minimum as described in the
Figure 6-15.
All the resistors and capacitors have to be as close
as possible to the STPC while the circuit protector
DALC112S1 must be close to the VGA connector.
The DDC[1:0] lines, not represented here, have
also to be protected when they are used on the
VGA connector.
COL_SEL can be used when implementing the
Picture-In-Picture function outside the STPC, for
example when multiplexing an analog video
source. In that case, the CRTC of the STPC has to
be genlocked to this analog source.
DCLK is usually used by the TFT display which
has RGB inputs in order to synchronise the picture
at the level of the pixel.
When the VGA interface is not needed, the signals
R, G, B, HSYNC, VSYNC, COMP, RSET can be
left unconnected, VSS_DAC and VDD_DAC must
then be connected to GND.
Figure 6-15. Typical VGA implementation
VDD_DAC
COMP
VREF_DAC
RSET
2.5V
10nF
VSS_DAC
143
1%
c
u
d
100nF 100nF 47uF
e
t
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)
s
t(
o
r
P
AGND
COL_SEL
DCLK
HSYNC
VSYNC
R
G
B
u
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o
)
s
(
ct
r
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e
t
e
l
o
o
s
b
O
75 1%
DALC112S1
3.3V
AGND
s
b
O
85/108
1
STPC® ATLAS
the ESD protection circuits USBDF01W5 and a
USB power supply controller. Figure 6-16
describes a typical implementation using these
devices.
6.3.10. USB INTERFACE
The STPC integrates a USB host interface with a
2-port Hub. The only external device needed are
Figure 6-16. Typical USB implementation
Connector
USBDF01W5 (note 1)
1
R = 15 Ohm
USBDMNS[0]
3
4
2
9
USBDPLS[0]
1
5
3
10
R = 152Ohm
4
100pF
USBDF01W5 (note 1)
15Ohm
Ohm
RR==15
USBDMNS[1]
USBDPLS[1]
3
4
1
5
6
e
t
le
100pF
(s)
OC
r
P
e
od
POWERON
t
e
l
o
s STPC
b
O
t
c
u
o
r
P
7
152Ohm
Ohm
RR==15
5V
11
12
8
GND
o
s
b
O
-
5V
5V
USBVCC
2,3
5
c
u
d
5
)
s
t(
6,7,8
TPS2014
4
1
100nF
100nF 2x 47uF
TPS2014
Power Decoupling
Note 1: The ESD protection will be adequate for most applications. In some instances, problems may occur
if the devices on the USB chain do not have enough power to drive the signals adequately. We therefore
recommend that you replace the part with discrete components and reduce the value of the capacitor.
86/108
1
STPC® ATLAS
6.3.11. KEYBOARD/MOUSE INTERFACE
The STPC integrates a PC/AT+ keyboard and PS/
2 mouse controller. The only external devices
needed are the ESD protection circuits
KBMF01SC6. Figure 6-17 describes a typical
implementation using a dual minidin connector.
Figure 6-17. Typical Keyboard / Mouse implementation
5V
5V
MiniDIN
MDATA
10
KBMF01SC6
MCLK
4
14 13
2
3
6
7
8
5V
c
u
d
11
o
r
P
9
)
s
t(
15 12
KBDATA
1
KBMF01SC6
KBCLK
STPC
)
s
(
ct
o
s
b
O
-
e
t
le
5
16
17
GND
u
d
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P
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t
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o
s
b
O
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STPC® ATLAS
circuits ST1284-01A8. Figure 6-18 describes a
typical implementation using this device.
6.3.12. PARALLEL PORT INTERFACE
The STPC integrates a parallel port where the only
external device needed is the ESD protection
Figure 6-18. Typical parallel port implementation
Connector
ACK#
BUSY
PE
SLCT
SLCTIN#
INIT#
c
u
d
ERR#
AUTOFD#
e
t
le
STROBE#
PD[7:0]
ST1284-01A8
STPC
)
s
(
ct
u
d
o
t
e
l
o
s
b
O
88/108
1
b
O
5V
r
P
e
so
8
o
r
P
8
)
s
t(
STPC® ATLAS
device needed are the pull up resistors. Figure 619 describes a typical implementation using these
devices.
6.3.13. JTAG INTERFACE
The STPC integrates a JTAG interface for scanchain and on-board testing. The only external
Figure 6-19. Typical JTAG implementation
3V3
3V3
3V3
3V3
Connector
10
9
TCLK
8
7
TDO
6
5
TMS
4
3
TDI
2
e
t
le
TRST
STPC
)
s
(
ct
c
u
d
)
s
t(
o
r
P
1
o
s
b
O
-
6.4. PLACE AND ROUTE RECOMMENDATIONS
u
d
o
6.4.1. GENERAL RECOMMENDATIONS
r
P
e
Some STPC Interfaces run at high speed and
need to be carefully routed or even shielded like:
t
e
l
o
1) Memory Interface
2) PCI bus
3) Graphics and video interfaces
4) 14 MHz oscillator stage
s
b
O
All clock signals have to be routed first and
shielded for speeds of 27MHz or higher. The high
speed signals follow the same constraints, as for
the memory and PCI control signals.
The next interfaces to be routed are Memory, PCI,
and Video/graphics.
All the analog noise-sensitive signals have to be
routed in a separate area and hence can be routed
indepedently.
6.4.2. PLL DEFINITION AND IMPLIMENTATION
PLLs are analog cells which supply the internal
STPC Clocks. To get the cleanest clock, the jitter
on the power supply must be reduced as much as
possible. This will result in a more stable system.
Each of the integrated PLL has a dedicated power
pin so a single power plane for all of these PLLs, or
one wire for each, or any solution in between
which help the layout of the board can be used.
Powering these pins with one Ferrite +
capacitances is enough. We recommend at least 2
capacitances: one 'big' (few uF) for power storage,
and one or 2 smalls (100nF + 1nF) for noise
filtering.
89/108
1
STPC® ATLAS
Figure 6-20. Shielding signals
ground ring
shielded signal line
ground pad
ground pad
)
s
t(
shielded signal lines
c
u
d
e
t
le
)
s
(
ct
u
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P
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t
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o
s
b
O
90/108
1
o
s
b
O
-
o
r
P
STPC® ATLAS
DIMM PCB is no longer present but it is then up to
the user to verify the timings.
6.4.3. MEMORY INTERFACE
6.4.3.1. Introduction
6.4.3.2. SDRAM Clocking Scheme
In order to achieve SDRAM memory interfaces
which work at clock frequencies of 90 MHz and
above, careful consideration has to be given to the
timing of the interface with all the various electrical
and physical constraints taken into consideration.
The guidelines described below are related to
SDRAM components on DIMM modules. For
applications where the memories are directly
soldered to the motherboard, the PCB should be
laid out such that the trace lengths fit within the
constraints shown here. The traces could be
slightly shorter since the extra routing on the
The SDRAM Clocking Scheme deserves a special
mention here. Basically the memory clock is
generated on-chip through a PLL and goes directly
to the MCLKO output pin of the STPC. The
nominal frequency is 90 MHz. Because of the high
load presented to the MCLK on the board by the
DIMMs it is recommended to rebuffer the MCLKO
signal on the board and balance the skew to the
clock ports of the different DIMMs and the MCLKI
input pin of STPC.
Figure 6-21. Clock Scheme
c
u
d
MCLKO
PLL
MCLKI
MA[ ] + Control
SDRAM
CONTROLLER
o
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P
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du
)
s
(
ct
MD[63:0]
t
e
l
o
bs
6.4.3.3. Board Layout Issues
O
The physical layout of the motherboard PCB
assumed in this presentation is as shown in Figure
6-22. Because all of the memory interface signal
balls are located in the same region of the STPC
device, it is possible to orientate the device to
reduce the trace lengths. The worst case routing
length to the DIMM1 is estimated to be 100 mm.
Solid power and ground planes are a must in order
to provide good return paths for the signals and to
register
o
s
b
O
-
DIMM1
PLL
o
r
P
DIMM2
e
t
le
)
s
t(
reduce EMI and noise. Also there should be ample
high frequency decoupling between the power and
ground planes to provide a low impedance path
between the planes for the return paths for signal
routings which change layers. If possible, the
traces should be routed adjacent to the same
power or ground plane for the length of the trace.
For the SDRAM interface, the most critical signal
is the clock. Any skew between the clocks at the
91/108
STPC® ATLAS
Figure 6-22. DIMM placement
35mm
STPC
35mm
SDRAM I/F
15mm
DIMM2
10mm
DIMM1
c
u
d
116mm
SDRAM components and the memory controller
will impact the timing budget. In order to get well
matched clocks at all components it is
recommended that all the DIMM clock pins, STPC
memory clock input (MCLKI) and any other
component using the memory clock are
individually driven from a low skew clock driver
with matched routing lengths specified in Section
4.5.3. . In other words, all clock line lengths that go
)
s
(
ct
Figure 6-23. Clock Routing
u
d
o
e
t
le
so
MCLKx = MCLKI+(1ns+/-0.5ns).
b
O
-
This is shown in Figure 6-23.
L+(1ns+/- 0.5ns)
r
P
e
bs
O
o
r
P
from the buffer to the memory chips (MCLKx) and
from the buffer to the STPC (MCLKI) must follow
this equation;
Low skew clock driver:
t
e
l
o
DIMM CKn input
DIMM CKn input
MCLKO
DIMM CKn input
L+75mm*
STPC MCLKI
20pF
* No additional 75mm when SDRAM directly soldered on board
92/108
)
s
t(
STPC® ATLAS
The maximum skew between pins for this part is
250ps. The important factors for the clock buffer
are a consistent drive strength and low skew
between the outputs. The delay through the buffer
is not important so it does not have to be a zero
delay PLL type buffer. The trace lengths from the
clock driver to the DIMM CKn pins should be
matched exactly. Since the propagation speed can
vary between PCB layers, the clocks should be
routed in a consistent way. The routing to the
STPC memory input should be longer by 75 mm to
compensate for the extra clock routing on the
DIMM. Also a 20 pF capacitor should be placed as
near as possible to the clock input of the STPC to
compensate for the DIMM’s higher clock load. The
impedance of the trace used for the clock routing
should be matched to the DIMM clock trace
impedance (60-75 ohms) To minimise crosstalk
the clocks should be routed with spacing to
adjacent tracks of at least twice the clock trace
width. For designs which use SDRAMs directly
mounted on the motherboard PCB all the clock
trace lengths should be matched to the constraints
given in Figure 6-23 and in Section 4.5.3. .
6.4.3.4. Summary
The DIMM sockets should be populated starting
with the furthest DIMM from the STPC device first
(DIMM1). There are two types of DIMM devices;
single-row and dual-row. The dual-row devices
require two chip select signals to select between
the two rows. A STPC device with 4 chip select
control lines could control either 4 single-row
DIMMs or 2 dual-row DIMMs. When only 2 chip
select control lines are activated, only two singlerow DIMMs or one dual-row DIMM can be
controlled.
6.5. CLOCK TOPOLOGY FOR ON-BOARD
SDRAM
.
)
s
(
ct
For unbuffered DIMMs the address/control signals
will be the most critical for timing. The simulations
show that for these signals the best way to drive
them is to use a parallel termination. For
applications where speed is not so critical series
termination can be used as this will save power.
Using a low impedance such as 50Ω for these
critical traces is recommended as it both reduces
the delay and the overshoot.
The other memory interface signals will typically
be not as critical as the address/control signals.
Using lower impedance traces is also beneficial for
the other signals but if their timing is not as critical
as the address/control signals they could use the
default value. Using a lower impedance implies
using wider traces which may have an impact on
the routing of the board.
)
s
t(
The layout of this interface can be validated by an
electrical simulation using the IBIS model
available on the STPC web site.
c
u
d
e
t
le
o
r
P
Figure 4-5 and Figure 6-25 give the recommended
clock topology and the resulting IBIS simulation in
the case of four on-board SDRAM devices and no
clock buffer.
o
s
b
O
-
Figure 6-24. Recommended topology for 4 on-board SDRAMs (IBIS model)
u
d
o
MCLKO
r
P
e
t
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o
MCLKI
s
b
O
400 mils
Track impedance= 75 Ohms
Trace thickness = 0.72 mil
Trace width = 4 to 8 mils
18 Ohms
400 mils
3500 mils
MCLK0
3500 mils
MCLK1
3500 mils
MCLK2
3500 mils
MCLK3
93/108
STPC® ATLAS
Figure 6-25. IBIS Simulation for on-board SDRAM / 90MHz
(V)
MCLKx
3
MCLKI
MCLKO
2.0 V
2
833ps
c
u
d
1
0.8 V
o
r
P
791ps
e
t
le
so
(s)
6.5.0.1. Clock topology for standard DIMM
t
c
u
b
O
-
)
s
t(
Time
in the case of a standard DIMM with the use of a
clock buffer.
Figure 6-26 and Figure 6-27 give the recommended clock topology and the resulting IBIS simulation
d
o
r
P
e
Figure 6-26. Recommended topology for DIMM (IBIS model)
t
e
l
o
Buffer out
s
b
O
Buffer out
22 Ohms
MCLKI
3000 mils
18 Ohms
2000 mils
DIMM
Track impedance= 75 Ohms
Trace thickness = 0.72 mil
Trace width = 4 to 8 mils
94/108
STPC® ATLAS
Figure 6-27. IBIS Simulation for DIMM / 90MHz
(V)
MCLKx
3
MCLKI
Buffer output
2.0 V
2
1.40 ns
c
u
d
1
0.8 V
)
s
t(
o
r
P
1.20 ns
e
t
le
)
s
(
ct
o
s
b
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STPC® ATLAS
6.5.1. PCI INTERFACE
6.5.1.3. Board Layout Issues
6.5.1.1. Introduction
The physical layout of the motherboard PCB
assumed in this presentation is as shown in Figure
6-29. For the PCI interface, the most critical signal
is the clock. Any skew between the clocks at the
PCI components and the STPC will impact the
timing budget. In order to get well matched clocks
at all components it is recommended that all the
PCI clocks are individually driven from a serial
resistance with matched routing lengths. In other
words, all clock line lengths that go from the
resistor to the PCI chips (PCICLKx) must be
identical.
In order to achieve a PCI interface which work at
clock frequencies up to 33MHz, careful
consideration has to be given to the timing of the
interface with all the various electrical and physical
constraints taken into consideration.
6.5.1.2. PCI Clocking Scheme
The PCI Clocking Scheme deserves a special
mention here. Basically the PCI clock (PCICLKO)
is generated on-chip from HCLK through a
programmable delay line and a clock divider. The
nominal frequency is 33MHz. This clock must be
looped to PCICLKI and goes to the internal South
Bridge through a deskewer. On the contrary, the
internal North Bridge is clocked by HCLK, putting
some additionnal constraints on T0 and T1.
The figure below is for PCI devices soldered onboard. In the case of a PCI slot, the wire length
must be shortened by 2.5" to compensate the
clock layout on the PCI board. The maximum clock
skew between all devices is 2ns according to PCI
specifications.
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The Figure 6-30 describes a typical clock delay
implementation. The exact timing constraints are
listed in the PCI section of the Electrical
Specifications Chapter.
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STPC® ATLAS
Figure 6-28. Clock Scheme
HCLK
HCLK PLL
T0
PCICLKO
1/2
1/3
1/4
clock
delay
T2
)
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1
PCICLKI
Deskewer
South
Bridge
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Bridge
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STPC® ATLAS
Figure 6-29. Typical PCI clock routing
Length(PCICLKI) = Length(PCICLKx) with x = {A,B,C}
PCICLKI
PCICLKA
PCICLKB
PCICLKO
PCICLKC
Device A
Device B
Device C
Note: The value of 22 Ohms corresponds to tracks with Z0 = 70 Ohms.
Figure 6-30. Clocks relationships
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HCLK
PCICLKO
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STPC® ATLAS
6.5.2. THERMAL DISSIPATION
6.5.2.1. Power saving
Thermal dissipation of the STPC depends mainly
on supply voltage. When the system does not
need to work at the upper voltage limit, it may
therefore be beneficial to reduce the voltage to the
lower voltage limit, where possible. This could
save a few 100’s of mW.
The second area to look at is unused interfaces
and functions. Depending on the application,
some input signals can be grounded, and some
blocks not powered or shutdown. Clock speed
dynamic adjustment is also a solution that can be
used along with the integrated power
management unit.
6.5.2.2. Thermal balls
The standard way to route thermal balls to ground
layer implements only one via pad for each ball
pad, connected using a 8-mil wire.
With such configuration the Plastic BGA package
does 90% of the thermal dissipation through the
ground balls, and especially the central thermal
balls which are directly connected to the die. The
remaining 10% is dissipated through the case.
Adding a heat sink reduces this value to 85%.
As a result, some basic rules must be followed
when routing the STPC in order to avoid thermal
problems.
As the whole ground layer acts as a heat sink, the
ground balls must be directly connected to it, as
illustrated in Figure 5-2. If one ground layer is not
enough, a second ground plane may be added.
When possible, it is important to avoid other
devices on-board using the PCB for heat
dissipation, like linear regulators, as this would
heat the STPC itself and reduce the temperature
range of the whole system, In case these devices
can not use a separate heat sink, they must not be
located just near the STPC
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Figure 6-31. Ground Routing
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Pad for ground ball
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Thru hole to ground layer
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Po
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Int
ern
al L
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ign
Bo
als
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STPC® ATLAS
When considering thermal dissipation, one of the
most important parts of the layout is the
connection between the ground balls and the
ground layer.
A 1-wire connection is shown in Figure 5-1. The
use of a 8-mil wire results in a thermal resistance
of 105°C/W assuming copper is used (418 W/
m.°K). This high value is due to the thickness (34
µm) of the copper on the external side of the PCB.
Figure 6-32. Recommended 1-wire Power/Ground Pad Layout
Pad for ground ball (diameter = 25 mil)
Solder Mask (4 mil)
Connection Wire (width = 12.5 mil)
34
Via (diameter = 24 mil)
.5
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Hole to ground layer (diameter = 12 mil)
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1 mil = 0.0254 mm
Considering only the central matrix of 36 thermal
balls and one via for each ball, the global thermal
resistance is 2.9°C/W. This can be easily
improved using four 12.5 mil wires to connect to
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The use of a ground plane like in Figure 6-34 is
even better.
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Figure 6-33. Recommended 4-wire Ground Pad Layout
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the four vias around the ground pad link as in
Figure 6-33. This gives a total of 49 vias and a
global resistance for the 36 thermal balls of 0.5°C/
W.
4 via pads for each ground ball
STPC® ATLAS
To obtain the optimum ground layout, place the
vias directly under the ball pads. In this case no
local board distortion is tolerated.
To avoid solder wicking over to the via pads during
soldering, it is important to have a solder mask of 4
mil around the pad (NSMD pad). This gives a
diameter of 33 mil for a 25 mil ground pad.
Figure 6-34. Optimum Layout for Central Ground Ball - top layer
Clearance = 6mil
External diameter = 37 mil
Via to Ground layer
hole diameter = 14 mil
Solder mask
diameter = 33 mil
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Pad for ground ball
diameter = 25 mil
connections = 10 mil
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6.5.2.3. Heat dissipation
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The possibility of using the whole system box for
thermal dissipation is very useful in cases of high
internal
temperatures
and
low
outside
temperatures. Bottom side of the PBGA should be
thermally connected to the metal chassis in order
to propagate the heat flow through the metal.
Thermally connecting also the top side will
improve furthermore the heat dissipation. Figure
6-35 illustrates such an implementation.
The thickness of the copper on PCB layers is
typically 34 µm for external layers and 17 µm for
internal layers. This means that thermal
dissipation is not good; high board temperatures
are concentrated around the devices and these fall
quickly with increased distance.
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Where possible, place a metal layer inside the
PCB; this improves dramatically the spread of heat
and hence the thermal dissipation of the board.
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Figure 6-35. Use of Metal Plate for Thermal Dissipation
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Metal planes
Thermal conductor
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STPC® ATLAS
As the PCB acts as a heat sink, the layout of top
and ground layers must be done with care to
maximize the board surface dissipating the heat.
The only limitation is the risk of losing routing
channels. Figure 6-36 and Figure 6-37 show a
routing with a good thermal dissipation thanks to
an optimized placement of power and signal vias.
The ground plane should be on bottom layer for
the best heat spreading (thicker layer than internal
ones) and dissipation (direct contact with air). .
Figure 6-36. Layout for Good Thermal Dissipation - top layer
1
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STPC ball
GND ball
Via
3.3V ball
Not Connected ball
2.5V ball (Core / PLLs)
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STPC® ATLAS
Figure 6-37. Recommend signal wiring (top & ground layers) with corresponding heat flow
GND
Power
GND
Power
Power/GND balls
Internal row
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Signal balls
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External row
Keep-Out = 6 mils
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Power/GND balls
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STPC® ATLAS
6.6. DEBUG METHODOLOGY
In order to bring a STPC-based board to life with
the best efficiency, it is recommended to follow the
check-list described in this section.
6.6.1. POWER SUPPLIES
In parallel with the assembly process, it is useful to
get a bare PCB to check the potential short-circuits
between the various power and ground planes.
This test is also recommended when the first
boards are back from assembly. This will avoid
bad surprises in case of a short-circuit due to a
bad soldering.
When the system is powered, all power supplies,
including the PLL power pins must be checked to
be sure the right level is present. See Table 4-2 for
the exact supported voltage range:
PCI_CLKI and PCI_CLKO must be connected as
described in Figure 6-29 and not be higher than
33MHz. Their speed depends on HCLK and on the
divider ratio defined by the MD[4] and MD[17] strap
options as described in Section 3.
To ensure a correct behaviour of the device, the
PCI deskewing logic must be configured properly
by the MD[7:6] strap options according to Section
3. For timings constraints, refers to Section 4.
1) MCLKI and MCLKO must be connected as
described in Figure 6-5 to Figure 6-7 depending on
the SDRAM implementation. The memory clock
must run at HCLK speed when in synchronous
mode and must not be higher than 90MHz in any
case. The MCLK interface will run 100MHz
operation is possible but board layout is so critical
that 90MHz maximum operation is recommended.
6.6.2.4. Reset output
)
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If SYSRSTI# and all clocks are correct, then the
SYSRSTO# output signal should behave as
described in Figure 4-3.
VDD_CORE: 2.5V
VDD_xxxPLL: 2.5V
VDD: 3.3V
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6.6.2. BOOT SEQUENCE
6.6.3. ISA MODE
6.6.2.1. Reset input
Prior to check the ISA bus control signals,
PCI_CLKI, ISA_CLK, ISA_CLK2X, and DEV_CLK
must be running properly. If it is not the case, it is
probably because one of the previous steps has
not been completed.
The checking of the reset sequence is the next
step. The waveform of SYSRSTI# must complies
with the timings described in Figure 4-3. This
signal must not have glitches and must stay low
until the 14.31818MHz output (OSC14M) is at the
right frequency and the strap options are stabilized
to a valid configuration.
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In case this clock is not present, check the 14MHz
oscillator stage (see Figure 6-4).
6.6.2.2. Strap options
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The STPC has been designed in a way to allow
configurations for test purpose that differs from the
functional configuration. In many cases, the
troubleshootings at this stage of the debug are the
resulting of bad strap options. This is why it is
mandatory to check they are properly setup and
sampled during the boot sequence.
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The list of all the strap options is summarized at
the beginning of Section 3.
6.6.2.3. Clocks
Once OSC14M is checked and correct, the next
signals to measure are the Host clock (HCLK), PCI
clocks (PCI_CLKO, PCI_CLKI) and Memory clock
(MCLKO, MCLKI).
HCLK must run at the speed defined by the
corresponding strap options (see Table 3-1). In x2
CPU clock mode, this clock must be limited to
66MHz.
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6.6.3.1. First code fetches
When booting on the ISA bus, the two key signals
to check at the very beginning are RMRTCCS#
and FRAME#.
The first one is a Chip Select for the boot flash and
is multiplexed with the IDE interface. It should
toggle together with ISAOE# and MEMRD# to
fetch the first 16 bytes of code. This corresponds
to the loading of the first line of the CPU cache.
In case RMRTCCS# does not toggle, it is then
necessary to check the PCI FRAME# signal.
Indeed the ISA controller is part of the South
Bridge and all ISA bus cycles are visible on the
PCI bus.
If there is no activity on the PCI bus, then one of
the previous steps has not been checked properly.
If there is activity then there must be something
conflicting on the ISA bus or on the PCI bus.
6.6.3.2. Boot Flash size
The ISA bus supports 8-bit and 16-bit memory
devices. In case of a 16-bit boot flash, the signal
MEMCS16#
must
be
activated
during
RMRTCCS# cycle to inform the ISA controller of a
16-bit device.
STPC® ATLAS
6.6.3.3. POST code
Once the 16 first bytes are fetched and decoded,
the CPU core continue its execution depending on
the content of these first data. Usually, it
corresponds to a JUMP instruction and the code
fetching continues, generating read cycles on the
ISA bus.
Most of the BIOS and boot loaders are reading the
content of the flash, decompressing it in SDRAM,
and then continue the execution by jumping to the
entry point in RAM. This boot process ends with a
JUMP to the entry point of the OS launcher.
These various steps of the booting sequence are
codified by the so-called POST codes (Power-On
Self-Test). A 8-bit code is written to the port 80H at
the beginning of each stage of the booting process
(I/O write to address 0080H) and can be displayed
on two 7-segment display, enabling a fast visual
check of the booting completion level.
Usually, the last POST code is 0x00 and
corresponds to the jump into the OS launcher.
When the execution fails or hangs, the lastest
written code stays visible on that display,
indicating either the piece of code to analyse,
either the area of the hardware not working
properly.
6.6.4. LOCAL BUS MODE
)
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When booting on the Local Bus, the key signal to
check at the very beginning is FCS0#. This signal
is a Chip Select for the boot flash and should
toggle together with PRD# to fetch the first 16
bytes of code. This corresponds to the loading of
the first line of the CPU cache.
In case FCS0# does not toggle, then one of the
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Check:
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Power
supplies
2
14.318 MHz
3
SYSRSTI#
(Power Good)
1
6.6.4.2. Boot Flash size
The Local Bus support 8-bit and 16-bit boot
memory devices only.
6.6.4.3. POST code
Like in ISA mode, POST codes can be
implemented on the Local Bus. The difference is
that an IOCS# must be programmed at I/O
address 80H prior to writing these code, the POST
display being connected to this IOCS# and to the
lower 8 bits of the bus.
6.6.5. SUMMARY
Here is a check-list for the STPC board debug
from power-on to CPU execution.
)
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For each step, in case of failure, verify first the
corresponding balls of the STPC:
- check if the voltage or activity is correct
- search for potential shortcuts.
For troubleshooting in steps 5 to 10, verify the
related strap options:
- value & connection. Refer to Section 3.
- see Figure 4-3 for timing constraints
Steps 8a and 9a are for debug in ISA mode while
steps 8b and 9b are for Local Bus mode.
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As the Local Bus controller is located into the Host
interface, there is no access to the cycles on the
PCI, reducing the amount of signals to check.
6.6.4.1. First code fetches
previous steps has not been done properly, like
HCLK speed and CPU clock multiplier (x1, x2).
How?
6.6.6. PCMCIA mode
As the STPC uses the RMRTCCS# signal for
booting in that mode, the methodology is the same
as for the ISA bus. The PCMCIA cards being 3.3V
or 5V, the boot flash device must be 5V tolerant
when directly connected on the address and data
busses. An other solution is to isolate the flash
from the PCMCIA lines using 5V tolerant LVTTL
buffers.
Troubleshooting
Verify that voltage is within specs:
- this must include HF & LF noise
- avoid full range sweep
Refer to Table 4-1 for values
Measure voltage near STPC balls:
- use very low GND connection.
Add some decoupling capacitor:
- the smallest, the nearest to STPC balls.
Verify OSC14M speed
The 2 capacitors used with the quartz must
match with the capacitance of the crystal.
Try other values.
Measure SYSRSTI# of STPC
See Figure 4-3 for waveforms.
Verify reset generation circuit:
- device reference
- components value
105/108
STPC® ATLAS
5
6
Check:
How?
HCLK
Measure HCLK is at selected frequency
25MHz < HCLK < 66MHz
HCLK wire must be as short as possible
PCI clocks
Measure PCICLKO:
- maximum is 33MHz by standard
- check it is at selected frequency
- it is generated from HCLK by a division
(1/2, 1/3 or 1/4)
Check PCICLKI equals PCICLKO
Verify PCICLKO loops to PCICLKI.
Verify maximum skew between any PCI clock
branch is below 2ns.
In Synchronous mode, check MCLKI.
Measure MCLKO:
- use a low-capacitance probe
- maximum is 90MHz
- check it is at selected frequency
- In SYNC mode MCLK=HCLK
- in ASYNC mode, default is 66MHz
Check MCLKI equals MCLKO
Verify load on MCLKI.
Verify MCLK programming (BIOS setting).
Measure SYSRSTO# of STPC
See Figure 4-3 for waveforms.
Verify SYSRSTI# duration.
Verify SYSRSTI# has no glitch
Verify clocks are running.
Check PCI signals are toggling:
- FRAME#, IRDY#, TRDY#, DEVSEL#
- these signals are active low.
Check, with a logic analyzer, that first
PCI cycles are the expected ones:
memory read starting at address with
lower bits to 0xFFF0
Verify PCI slots
If the STPC don’t boot
- verify data read from boot memory is OK
- ensure Flash is correctly programmed
- ensure CMOS is cleared.
Memory
clocks
7
4
SYSRSTO#
8a
PCI cycles
9a
ISA
cycles
to
boot memory
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10
Local Bus
cycles
to
boot memory
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Check RMRTCCS# & MEMRD#
Check directly on boot memory pin
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8b
9b
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Troubleshooting
Verify MEMCS16#:
- must not be asserted for 8-bit memory
Verify IOCHRDY is not be asserted
Verify ISAOE# pin:
- it controls IDE / ISA bus demultiplexing
Check FCS0# & PRD#
Check directly on boot memory pin
Verify HCLK speed and CPU clock mode.
Check, with a logic analyzer, that first
Local Bus cycles are the expected one:
memory read starting at the top of boot
memory less 16 bytes
If the STPC don’t boot
- verify data read from boot memory is OK
- ensure Flash is correctly programmed
- ensure CMOS is cleared.
The CPU fills its first cache line by fetching 16 bytes from boot memory.
Then, first instructions are executed from the CPU.
Any boot memory access done after the first 16 bytes are due to the instructions executed by the CPU
=> Minimum hardware is correctly set, CPU executes code.
Please have a look to the Bios Writer’s Guide or Programming Manual to go further with your board testing.
106/108
STPC® ATLAS
7 ORDERING DATA
7.1. ORDERING CODES
ST
PC
I2
H
E
Y
C
STMicroelectronics
Prefix
Product Family
PC: PC Compatible
Product ID
I2: Atlas
Core Speed
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G: 120 MHz
H: 133 MHz
Memory Speed
D: 90 MHz
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E: 100 MHz
Package
Y: 516 Overmoulded BGA
Temperature Range
C: Commercial
Tcase = 0 to +85°C
I: Industrial
Tcase = -40 to +115°C
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7.2 AVAILABLE PART NUMBERS
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Part Number
Core Frequency
(MHz)
133
120
CPU Mode
Memory Interface
Speed (MHz)
90
90
Tcase Range
(C)
0°C to +85°C
-40°C to +115°C
Operating Voltage
(V)
2.45 - 2.7
X2
STPCI2HEYC1
STPCI2GDYI
X2
3.0 - 3.6
Note 1:
The STPC Atlas MClock signal can run up to 100MHz reliably, but PCB layout is so critical that the maximum guaranteed
speed is 90MHz
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STPC® ATLAS
8 REVISION HISTORY
Date
Revision
Mar 04
1.1
Jan 05
3
Description of Changes
Second release
Revision number incremented from 1.1 to 3 due to Internal Document
Management System change
Modified Figure 6-9.PCI clock routing with zero-delay clock buffer
Added two capacitors (100pF) in Figure 6-16.Typical USB implementation.
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
t
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The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2005 STMicroelectronics - All rights reserved
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