STV8162

STV8162 +5 V, +5 V and +8 V triple voltage regulator with disable and reset functions Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Figure 1. STV8162 and STV8162D Input voltage range between 7 V and 18 V Output currents up to 600 mA Fixed precision output 1 voltage of 5 V ± 2% Fixed precision output 2 voltage of 5 V ± 2% Fixed precision output 3 voltage of 8 V ± 2% Output 1 with reset facility Outputs 2 and 3 can be disabled by digital input Short circuit protection on each output Thermal protection Low dropout voltages Clipwatt 11 Description The STV8162 and STV8162D are monolithic triple positive voltage regulators designed to provide three fixed precision output voltages of 5 V, 5 V and 8 V for currents up to 0.6 A. An internal reset circuit generates a reset pulse when the voltage of output 1 drops below the regulated voltage value. Outputs 2 and 3 can be disabled by a digital input. Short-circuit and thermal protections are included in all versions. GROUND GROUND GROUND O GROUND GROUND GROUND GROUND GROUND GROUND bs let o 10 11 12 13 14 15 16 17 18 Pr e du o (s) ct so Ob Table 1. STV8162 te le Power DIP18 (9 + 9) ro P Tray Tray uc d s) t( Device summary Packaging Order code STV8162D 9 8 7 6 5 4 3 2 1 DISABLE INPUT3 OUTPUT3 INPUT2 OUTPUT2 INPUT1 OUTPUT1 DELAY CAPACITOR RESET Top View 11 10 9 8 7 6 5 4 3 2 1 NC DISABLE INPUT3 OUTPUT3 INPUT2 GROUND OUTPUT2 INPUT1 OUTPUT1 DELAY CAPACITOR RESET March 2009 Rev 2 1/14 www.st.com 1 Contents STV8162 Contents 1 2 3 4 5 6 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Application diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Power dissipation and layout indications . . . . . . . . . . . . . . . . . . . . . . . . 9 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6.1 Environmentally-friendly packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 bs O let o Pr e du o (s) ct so Ob - te le ro P uc d s) t( 2/14 STV8162 Description 1 Description Figure 2. STV8162 block diagram DELAY CAPACITOR 2 1 Reference RESET INPUT1 4 Regulator 1 Protections 3 OUTPUT1 INPUT2 7 Regulator 2 5 OUTPUT2 INPUT3 9 Regulator 3 8 OUTPUT3 DISABLE 10 6 GROUND Figure 3. STV8162D block diagram bs O let o Pr e INPUT1 4 od ct u Reference (s) so Ob 2 Regulator 1 te le ro P 11 Not Connected uc d s) t( DELAY CAPACITOR 1 RESET 3 Protections OUTPUT1 INPUT2 6 Regulator 2 5 OUTPUT2 INPUT3 8 DISABLE 9 Regulator 3 7 OUTPUT3 GROUND Pins 10 to 18 3/14 Electrical characteristics STV8162 2 Electrical characteristics Table 2. Symbol VIN VDIS VRST IOUTPUT Pt TSTG TJ Absolute maximum ratings Parameter DC input voltage at pins INPUT1, INPUT2 and INPUT3 Disable input voltage at pin DISABLE Output voltage at pin RESET Output currents Power dissipation Storage temperature Junction temperature 20 20 20 Internally limited Internally limited -65 to +150 0 to +150 °C °C Value V V V Unit Table 3. Symbol RthJC RthJA TJ TOPER Thermal data Parameter Junction-to-case thermal resistance Junction-to-ambient thermal resistance (1) STV8162 STV8162D STV8162 STV8162D Value Maximum recommended junction temperature Operating free air temperature range 1. Mounted on board. For more information, refer to Section 5. Table 4. Symbol VOUT1 VOUT2 VOUT3 VOUT1 Electrical characteristics Parameter Output voltage Output voltage bs O VOUT2 VOUT3 VIO1 VIO2 VIO3 let o Output voltage Output voltage Output voltage Output voltage ro P e du (s) ct Ob - so Pr te le ≥10 56 140 Min. 4.90 4.90 7.84 4.80 4.80 7.68 3 15 od uc s) t( °C °C Unit °C/W °C/W 0 to +70 Test conditions Typ. 5.00 5.00 8.00 Max. 5.10 5.10 8.16 5.20 5.20 8.32 V V V V V V V V V Unit IOUT1 = 10 mA IOUT2 = 10 mA IOUT3 = 10 mA 7 V < VIN1 < 12 V 5 mA < IOUT1 < 600 mA 7 V < VIN2 < 12 V 5 mA < IOUT2 < 600 mA 10 V < VIN3 < 15 V 5 mA < IOUT3 < 600 mA IOUT1 = 0.6 A IOUT2 = 0.6 A IOUT3 = 0.6 A Dropout voltage Dropout voltage Dropout voltage 1 1 1 1.4 1.4 1.4 4/14 STV8162 Table 4. Symbol VOUT1LI VOUT2LI VOUT3LI Electrical characteristics Electrical characteristics (continued) Parameter Line regulation Line regulation Line regulation Test conditions 7 V < VIN1 < 12 V, IOUT1 = 200 mA 7 V < VIN2 < 12 V, IOUT2 = 200 mA 10 V < VIN3 < 15 V, IOUT3 = 200 mA 5 mA < IOUT1 < 600 mA 5 mA < IOUT2 < 600 mA 5 mA < IOUT3 < 600 mA IOUT1 = 10 mA Outputs 2 and 3 disabled K = VOUT1 See circuit description. Ce = 100 nF See circuit description. IRESET = 5 mA VRESET = 10 V TJ = 0 to 125°C 6 Δ V OUT ⋅ 10 K OUT = ---------------------------------Δ T ⋅ V OUT VIN1 = 7 V K-0.4 30 2.2 K-0.25 75 25 Min. Typ. Max. 50 50 80 100 100 160 3.0 Unit mV mV mV mV mV mV mA VOUT1LO Load regulation VOUT2LO Load regulation VOUT3LO Load regulation IQ VO1RST VRTH tRD VRL IRH KOUT1 KOUT2 KOUT3 IOUT1SC IOUT2SC IOUT3SC VDISH VDISL IDIS TJSD TSDH Quiescent current Reset threshold voltage Reset threshold hysteresis Reset pulse delay Saturation voltage in reset condition Leakage current in normal condition, at RESET pin Output voltage thermal drift Short circuit output current Short circuit output current Short circuit output current K-0.10 V 120 Voltage high level at DISABLE pin (Outputs 2 and 3 active) Voltage low level at DISABLE pin (Outputs 2 and 3 disabled) Bias current at DISABLE pin Junction temperature for thermal shutdown bs O let o Thermal shutdown temperature hysteresis Pr e du o (s) ct VIN1 = 7 V VIN3 = 10 V Ob - so eP let 0.8 0.8 0.8 2 od r 100 1.3 1.3 1.3 uc 0.4 10 s) t( mV ms V μA ppm/° C 1.8 1.8 1.8 A A A V 0.8 -100 150 15 2 V μA °C °C 0 V < VDISABLE < 7 V 5/14 Circuit description STV8162 3 Circuit description The STV8162 and STV8162D are triple-voltage regulators with reset and disable functions. The three regulation parts are supplied from a single voltage reference circuit trimmed by zener zapping during EWS testing. Since the supply voltage of this voltage reference is connected to pin INPUT1 (VIN1), the second and third regulators will not work if pin INPUT1 is not supplied. The output stages are designed using a Darlington configuration with a typical dropout voltage of 1.0 V. In all applications, all three inputs must be polarized. If outputs 2 or 3 are not used, the corresponding inputs must be connected to Input 1. The disable circuit will switch off pins OUTPUT2 and OUTPUT3 if a voltage less than 0.8 V is applied to pin DISABLE. The reset circuit checks the voltage at pin OUTPUT1. If this voltage drops below VOUT1-0.25 V (4.75 V Typ.), the "a" comparator (Figure 4) rapidly discharges the external capacitor (Ce) and the reset output immediately switches to low. When the voltage at pin OUTPUT1 exceeds VOUT1-0.175 V (4.825 V Typ.), the VCe voltage increases linearly to the reference voltage (VREF = 2.5 V) corresponding to a reset pulse delay (tRD)as shown in Figure 5. C e × 2.5V t RD = -------------------------10 μA Afterwards, the reset output returns to high. To avoid glitches in the reset output, the second comparator "b" has a large hysteresis (1.9 V). bs O let o Pr e du o (s) ct so Ob - te le ro P uc d s) t( 6/14 STV8162 Application diagrams 4 Application diagrams Figure 4. Reset diagram 10 µA VREF OUTPUT1 REG VREF = 2.5 V +a 3 Ce VREF 0.6V + b RESET Figure 5. Internal reset diagram VOUT1 K VO1RST VRTH RESET K = Actual Value of VOUT1 Power On tRD Figure 6. STV8162 typical application C1 to C6 = 10 µF bs O let o VIN1 VIN2 Pr e C1 du o C2 (s) ct Ob 1 RESET so te le 0.1 µF ro P uc d s) t( tRD Power Off Ce 2 DELAY CAPACITOR OUTPUT1 3 OUTPUT2 5 OUTPUT3 8 4 INPUT1 7 INPUT2 9 INPUT3 VOUT1 VOUT2 VOUT3 C4 C5 C6 VIN3 C3 GROUND DISABLE 6 10 NC 11 7/14 Application diagrams Figure 7. STV8162D typical application 0.1 µF STV8162 C1 to C6 = 10 µF Ce 1 RESET 2 DELAY CAPACITOR OUTPUT1 3 OUTPUT2 5 OUTPUT3 7 VIN1 VIN2 VIN3 C1 C2 C3 4 INPUT1 6 INPUT2 8 INPUT3 VOUT1 VOUT2 VOUT3 C4 C5 C6 GROUND DISABLE 9 Pins 10 to 18 bs O let o Pr e du o (s) ct so Ob - te le ro P uc d s) t( 8/14 STV8162 Power dissipation and layout indications 5 Power dissipation and layout indications The power is mainly dissipated by the three device buffers. It can be calculated by the equation: P = (VIN1-VOUT1) x IOUT1 + (VIN2-VOUT2) x IOUT2 + (VIN3-VOUT3) x IOUT3 The following table lists the different RthJA values of these packages with or without a heat sink and the corresponding maximum power dissipation assuming: ● ● Maximum ambient temperature = 70° C Maximum junction temperature = 140° C Power dissipation Heat Sink No 50 15 56 to 40 32 RthJA in °C/W 1.4 4.6 1.25 to 1.75 2.2 PMAX in W Table 5. Device STV8162 Yes No STV8162D Yes Figure 8. Thermal resistance (junction-to-ambient) of DIP18 package without heatsink To optimize the thermal conductivity of the copper layer and the exchanges with the air, the solder must cover the maximum amount of this area. Test Board with “On Board” square heat sink area. 60 RthJA °C/W 55 50 45 40 6 0 2 4 8 10 12 Copper area (cm²) (35 µm plus solder) Board is face-down bs O let o Figure 9. Pr e du o (s) ct so Ob - te le ro P uc d s) t( Metal plate mounted near STV8162D for heatsinking Top View Bottom View 9/14 Package mechanical data STV8162 6 Package mechanical data Figure 10. 11-pin plastic Clipwatt package C A H1 H3 L D L1 B L2 E F M1 M Table 6. Dim. 11-pin plastic Clipwatt package dimensions mm Min. A B C D E O bs let o F G H1 H2 H3 L L1 L2 L3 ro P e 0.49 0.80 1.57 19.85 uc d 0.15 1.50 (s) t Typ. so Ob Max. 3.20 1.05 eP let G1 Min. ro uc d G s) t( Inches Typ. Max. 0.126 0.041 0.006 0.059 0.55 0.91 1.70 12.00 18.60 1.83 0.019 0.031 0.062 0.002 0.036 0.067 0.480 0.732 0.072 0.781 17.90 14.45 0.700 0.569 11.20 0.421 0.433 0.217 0.441 10.70 11.00 5.50 10/14 STV8162 Table 6. Dim. Min. M M1 2.54 2.54 Number of pins N 11 Typ. Max. Min. Package mechanical data 11-pin plastic Clipwatt package dimensions (continued) mm Inches Typ. 0.100 0.100 Max. Figure 11. 18-pin plastic dual in-line power package E A2 A1 A L b D1 b3 D b2 e 18 1 Table 7. bs O let o A A1 A2 b b2 b3 c D Dim. od Pr e Min. 0.38 2.92 0.36 1.14 0.76 0.20 22.35 18-pin pastic dual in-line power package dimensions mm Typ. Max. 5.33 0.015 3.30 0.46 1.52 0.99 0.25 22.86 4.95 0.56 1.78 1.14 0.36 23.37 0.115 0.014 0.045 0.030 0.008 0.880 0.130 0.018 0.060 0.039 0.010 0.900 0.195 0.022 0.070 0.045 0.014 0.920 Min. Inches Typ. Max. 0.210 ct u (s) so Ob 10 9 te le E1 ro P uc d eB s) t( c 11/14 Package mechanical data Table 7. Dim. Min. D1 e eB E E1 L 7.62 6.10 2.92 7.87 6.35 3.30 0.13 2.54 10.92 8.26 7.11 3.81 0.300 0.240 0.115 0.310 0.250 0.130 Typ. Max. Min. 0.005 0.100 Typ. STV8162 18-pin pastic dual in-line power package dimensions (continued) mm Inches Max. 0.430 0.325 0.280 0.150 6.1 Environmentally-friendly packages In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. bs O let o Pr e du o (s) ct so Ob - te le ro P uc d s) t( 12/14 STV8162 Revision history 7 Revision history Table 8. Date January 2000 November 2002 04-Mar-2009 Document revision history Revision 0.2 0.3 2.0 Initial release. Addition of PDIP18 pakage New template applied, Section 6.1 added Changes bs O let o Pr e du o (s) ct so Ob - te le ro P uc d s) t( 13/14 STV8162 Please Read Carefully: Information in this document is provided solely in connection with ST products. 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