STW81101-EVB4G

STW81101 Multi-band RF frequency synthesizer with integrated VCOs Preliminary Data Feature summary ■ ■ Integer-N Frequency Synthesizer Dual differential integrated VCOs with automatic center frequency calibration: – 3300 - 3900 MHz (Direct output) – 3800 - 4400 MHz (Direct output) – 1650 - 1950 MHz (Internal divider by 2) – 1900 - 2200 MHz (Internal divider by 2) – 825 - 975 MHz (Internal divider by 4) – 950 - 1100 MHz (Internal divider by 4) Excellent integrated phase noise Fast lock time: 150µs Dual modulus programmable prescaler (16/17 or 19/20) 2 programmable counters to achieve a feedback division ratio from 256 to 65551 (prescaler 16/17) and from 361 to 77836 (prescaler 19/20). Programmable reference frequency divider (10 bits) Phase frequency comparator and charge pump Programmable charge pump current Digital Lock Detector Dual Digital Bus Interface: SPI and I2C bus with 3 bit programmable address (1100A2A1A0) 3.3V Power Supply Power down mode (HW and SW) Small size exposed pad VFQFPN28 package 5x5x1.0mm Process: BICMOS 0.35µm SiGe VFQFPN28 Applications ■ ■ ■ ■ ■ ■ 2.5G and 3G Cellular Infrastructure Equipment CATV Equipment ■ Instrumentation and Test Equipment ■ Other Wireless Communication Systems Description The STMicroelectronics STW81101 is an integrated RF synthesizer with voltage controlled oscillators (VCOs). Showing high performance, high integration, low power, and multi-band performances, STW81101 is a low cost one chip alternative to discrete PLL and VCOs solutions. STW81101 includes an Integer-N frequency synthesizer and two fully integrated VCOs featuring low phase noise performance and a noise floor of -154dBc/Hz. The combination of wide frequency range VCOs (thanks to centerfrequency calibration over 32 sub-bands) and multiple output options (direct output, divided by 2 or divided by 4) allows to cover the 825MHz1100MHz, the 1650MHz-2200MHz and the 3300MHz-4400MHz bands. The STW81101 is designed with STMicroelectronics advanced 0.35µm SiGe process. ■ ■ ■ ■ ■ ■ ■ ■ ■ Order codes Part number STW81101AT STW81101ATR Temp range, °C -40 to 85 -40 to 85 Package VFQFPN28 VFQFPN28 Packing Tray Tape & Reel March 2006 Rev 1 1/42 www.st.com 1 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. Contents STW81101 Contents 1 Block diagram and pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 1.2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 2.2 2.3 2.4 2.5 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Digital logic levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Phase noise specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3 4 Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.1 Circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.1.1 4.1.2 4.1.3 4.1.4 4.1.5 4.1.6 4.1.7 4.1.8 Reference input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Reference divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 A and B counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Phase frequency detector (PFD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Lock detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Voltage controlled oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 VCO Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 VCO Frequency Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 VCO Voltage Amplitude Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 5 I2C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.1 General features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.1.1 5.1.2 5.1.3 5.1.4 5.1.5 Power ON reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 START condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 STOP condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Byte format and acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2/42 STW81101 5.1.6 5.1.7 5.1.8 5.1.9 Contents Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Single-byte write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Multi-byte write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Current byte address read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.2 5.3 Timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.2.1 Ack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 I2C registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.3.1 5.3.2 5.3.3 5.3.4 5.3.5 5.3.6 5.3.7 FUNCTIONAL_MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 B_COUNTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 A_COUNTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 REF_DIVIDER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 CALIBRATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 READ-ONLY register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.4 VCO calibration procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6 SPI digital interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.1 6.2 6.3 6.4 General features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Bits table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 VCO calibration procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.1 7.2 7.3 7.4 Direct Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Divided by 2 Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Divided by 4 Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Evaluation Kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8 9 10 Application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3/42 List of tables STW81101 List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Digital logic levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Phase noise specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Current value vs selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Voltage level expected on the resonator nodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Single-byte write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Multi-byte write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Current Byte Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Data and clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Start and stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Ack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Write-only registers list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Different functional mode of the FUNCTIONAL_MODE register . . . . . . . . . . . . . . . . . . . . 25 SPI data structure (MSB is sent first) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Address decoder and outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 SPI Timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Order code of the evaluation kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4/42 STW81101 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 VCO A (Direct output) closed loop phase noise at 3.6GHz with FSTEP=400KHz (FPFD=400KHz). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 VCO B (Direct output) closed loop phase noise at 4.0GHz with FSTEP=400KHz (FPFD=400KHz). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 VCO A (Div. by 2 output) closed loop phase noise at 1.8GHz with FSTEP=200KHz (FPFD=400KHz). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 VCO B (Div. by 2 output) closed loop phase noise at 2.0GHz with FSTEP=200KHz (FPFD=400KHz). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 VCO A (Div. by 4 output) closed loop phase noise at 900MHz with FSTEP=100KHz (FPFD=400KHz). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 VCO B (Div. by 4 output) closed loop phase noise at 1.0GHz with FSTEP=100KHz (FPFD=400KHz). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 PFD Frequency Spurs (Div. by 2 Output; FPFD=400KHz) . . . . . . . . . . . . . . . . . . . . . . . . . 15 PFD Frequency Spurs (Div. by 4 Output; FPFD=400KHz) . . . . . . . . . . . . . . . . . . . . . . . . . 15 Reference Frequency Input Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 VCO Divider Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 PFD diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Loop filter connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 VCO Sub-Bands Frequency Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Start and Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Byte format and acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Data and clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Start and stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Ack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 SPI input and output bit order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 SPI Timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Differential/single ended output network in the 3.3 - 4.4GHz range (MATCH_LC_LUMP_4G_DIFF.dsn). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 LC lumped balun and matching network (MATCH_LC_LUMP_4G.dsn) . . . . . . . . . . . . . . 35 Microstrip line and lumped matching network (MATCH_4G_HYBRID.dsn) . . . . . . . . . . . . 35 Differential/single ended output network in the 1.65 - 2.2GHz range (MATCH_LC_LUMP_2G_DIFF.dsn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 LC lumped balun for divided by 2 output (MATCH_LC_LUMP_2G.dsn) . . . . . . . . . . . . . . 36 Lumped output matching for divided by 2 output (MATCH_LC_BAL_2G.dsn) . . . . . . . . . 37 LC lumped balun for the divided by 4 output (MATCH_LC_LUMP_1G.dsn) . . . . . . . . . . . 37 Lumped output matching for divided by 4 output (MATCH_LC_BAL_1G.dsn) . . . . . . . . . 38 Application diiagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 VFQFPN28 Mechanical Data & Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5/42 Block diagram and pin configuration STW81101 1 1.1 Figure 1. Block diagram and pin configuration Block diagram Block diagram OUTBUFP OUTBUFN REF_CLK VDD_PLL VSS_PLL REXT VDD_OUTBUF VSS_OUTBUF BUF VDD_DIV4 VSS_DIV4 VCO BUF DIV4 BUF DIV2 BUF VSS_CP VDD_DIV2 VSS_DIV2 REF Divider P F D VCO Divider UP DN DIV4 DIV2 VDD_CP VDD_BUFVCO VSS_BUFVCO C P ICP BUF EXTVCO_INP EXTVCO_INN EXT VCO BUF LOCK_DET DBUS_SEL SCL / CLK SDA / DATA ADD0 / LOAD ADD1 ADD2 DBUS VCO BUFF VDD_VCOA VSS_VCOA VDD_VCOB VSS_VCOB VDD_ESD VSS_ESD VCO Calibrator VDD_DBUS VSS_DBUS EXT_PD TEST1 TEST2 VCTRL 6/42 STW81101 Block diagram and pin configuration 1.2 Pin configuration Figure 2. Pin connection (top view) ADD0/LOAD SDA/DATA VDD_DBUS DBUS_SEL VDD_BUFVCO EXTVCO_INP EXTVCO_INN SCL/CLK VDD_VCOA VDD_DIV2 VDD_OUTBUF OUTBUFP OUTBUFN VDD_DIV4 VDD_VCOB VDD_ESD VFQFPN28 EXT_PD ADD2 ADD1 VDD_PLL REF_CLK TEST2 LOCK_DET VDD_CP VCTRL Table 1. Pin No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Pin description Name VDD_VCOA VDD_DIV2 VDD_OUTBUF OUTBUFP OUTBUFN VDD_DIV4 VDD_VCOB VDD_ESD VCTRL ICP REXT VDD_CP TEST1 LOCK_DET Description VCOA power supply Divider by 2 power supply Output buffer power supply LO buffer positive output LO buffer negative output Divider by 4 power supply VCOB power supply ESD positive rail power supply VCO control voltage PLL charge pump output External resistance connection for PLL charge pump Power supply for charge pump Test input 1 Lock detector Test purpose only; must be connected to GND CMOS Output Open collector Open collector Observation TEST1 REXT ICP 7/42 Block diagram and pin configuration Table 1. Pin No 15 16 17 18 19 20 21 22 23 24 25 26 27 28 TEST2 REF_CLK VDD_PLL EXTVCO_INN EXTVCO_INP VDD_BUFVCO DBUS_SEL VDD_DBUS EXT_PD SDA/DATA SCL/CLK ADD0/LOAD ADD1 ADD2 STW81101 Pin description (continued) Name Test input 2 Reference clock input PLL digital power supply External VCO negative input External VCO positive input VCO buffer power supply Digital Bus Interface select SPI and I 2C Description Observation Test purpose only; must be connected to GND Test purpose only; must be connected to GND Test purpose only; must be connected to GND CMOS Input bus power supply CMOS Input CMOS Bidir Schmitt triggered CMOS Input CMOS Input CMOS Input CMOS Input Power down hardware I2CBUS/SPI data line I2CBUS/SPI clock line I2CBUS address select pin/ SPI load line I2CBUS address select pin I2CBUS address select pin 8/42 STW81101 Electrical specifications 2 2.1 Table 2. Symbol AVCC DVCC Tstg Electrical specifications Absolute maximum ratings Absolute maximum ratings Parameter Analog Supply voltage Digital Supply voltage Storage temperature Electrical Static Discharge - HBM(1) - CDM-JEDEC Standard - MM Values 0 to 4.6 0 to 4.6 +150 4 1.5 0.2 Unit V V °C ESD KV 1. The maximum rating of the ESD protection circuitry on pin 4 and pin 5 is 1KV. 2.2 Table 3. Symbol AVCC DVCC ICC Tamb Tj Rth j-amb Operating conditions Operating conditions Parameter Analog Supply voltage Digital Supply voltage Current Consumption Operating ambient temperature Maximum junction temperature Junction to ambient package thermal resistance Multilayer JEDEC board 35 -40 Test conditions Min 3.0 3.0 Typ 3.3 3.3 Max 3.6 3.6 100 85 125 Unit V V mA °C °C °C/W 2.3 Table 4. Symbol Vil Vih Vhyst Vol Voh Digital logic levels Digital logic levels Parameter Low level input voltage High level input voltage Schmitt trigger hysteresis Low level output voltage High level output voltage 0.85*Vdd 0.8*Vdd 0.8 0.4 Test conditions Min Typ Max 0.2*Vdd Unit V V V V V 9/42 Electrical specifications STW81101 2.4 Table 5. Symbol Electrical characteristics Electrical characteristics All the Electrical Specifications are intended at 3.3V supply Voltage. Parameter Test conditions Min Typ Max Unit OUTPUT FREQUENCY RANGE Direct Output Output Frequency Range with Divider by 2 VCOA Divider by 4 Direct Output Output Frequency Range with Divider by 2 VCOB Divider by 4 3300 1650 825 3800 1900 950 3900 1950 975 4400 2200 1100 MHz MHz MHz MHz MHz MHz FOUTA FOUTB VCO DIVIDERS N VCO Divider Ratio Prescaler 16/17 Prescaler 19/20 256 361 65551 77836 REFERENCE CLOCK and PHASE FREQUENCY DETECTOR fref R fPFD Reference input frequency Reference input sensitivity Reference Divider Ratio PFD input frequency Prescaler 16/17 fstep Frequency step(1) Prescaler 19/20 CHARGE PUMP ICP VOCP ICP sink/source(2) Output voltage compliance range Direct Output Spurious(3) Divider by 2 Divider by 4 VCOs Sub-Band 00000 KVCOA VCOA sensitivity(4) Sub-Band 01111 Sub-Band 11111 Sub-Band 00000 KVCOB VCOB sensitivity(4) (4) 10 0.35 2 1 200 1.5 1023 16 MHz Vpeak MHz Hz Hz FOUT/ 65551 FOUT/ 77836 FOUT/ 256 FOUT/ 361 3bit programmable 0.4 -76 -82 -88 5 Vdd-0.3 mA V dBc dBc dBc 90 55 35 90 55 35 105 70 45 105 70 45 8 8 115 85 55 115 85 55 12 12 MHz/V MHz/V MHz/V MHz/V MHz/V MHz/V MHz/V MHz/V Sub-Band 01111 Sub-Band 11111 VCO A Pushing VCO B Pushing(4) 10/42 STW81101 Table 5. Symbol VCTRL Electrical specifications Electrical characteristics (continued) All the Electrical Specifications are intended at 3.3V supply Voltage. Parameter VCO control voltage(4) LO Harmonic Spurious (4) Test conditions Min 0.4 Typ Max 3 -20 Unit V dBc mA mA mA mA VCO current consumption VCO buffer consumption DIVIDER by 2 consumption DIVIDER by 4 consumption LO OUTPUT BUFFER Output level Return Loss (4) 25 15 18 14 0 Matched to 50ohm DIV4 Buff 15 26 23 37 dBm dB mA mA mA Current Consumption DIV2 Buff Direct Output EXTERNAL VCO (Test purpose only) Frequency range Input level Current Consumption PLL MISCELLANEOUS Current Consumption Lock up time (4) Input Buffer, Prescaler, Digital Dividers, misc. 40 KHz PLL bandwidth; within 1 ppm of frequency error 12 mA VCO Internal Buffer 3.3 0 15 4.4 +6 GHz dBm µA 150 µs 1. The frequency step is related to the PFD input frequency as follows: - fstep = fPFD for Direct Output - fstep = fPFD/2 for Divided by 2 Output - fstep = fPFD/4 for Divided by 4 Output 2. see relationship between ICP and REXT in the Circuit Description section (Charge Pump) 3. PFD frequency leakage (400KHz) and harmonics 4. Guaranteed by design and characterization. 2.5 Table 6. Phase noise specification Phase noise specification Parameter Test conditions Min Typ Max Unit PHASE NOISE PERFORMANCE(1) In Band Phase Noise Floor – Closed Loop(2) Normalized In Band Phase Noise Floor ICP=4mA, PLL BW = 50KHz; including reference clock contribution -220 dBc/Hz 11/42 Electrical specifications Table 6. Phase noise specification (continued) Parameter In Band Phase Noise Floor Direct Output In Band Phase Noise Floor Divider by 2 In Band Phase Noise Floor Divider by 4 PLL Integrated Phase Noise – Direct Output Integrated Phase Noise 100Hz to 40MHz FOUT = 4 GHz, fPFD = 400KHz, fSTEP =400 KHz, PLL BW = 35KHz, ICP=4mA -38 1.0 ICP=4mA, PLL BW = 50KHz; including reference clock contribution Test conditions Min Typ Max STW81101 Unit dBc/Hz dBc/Hz dBc/Hz -220+20log(N)+10log(fPFD) -226+20log(N)+10log(fPFD) -232+20log(N)+10log(fPFD) dBc ° rms PLL Integrated Phase Noise – Divider by 2 Integrated Phase Noise 100Hz to 40MHz FOUT = 2 GHz, fPFD = 400KHz, fSTEP =200 KHz, PLL BW = 35KHz, ICP=4mA -44 0.5 dBc ° rms PLL Integrated Phase Noise – Divider by 4 Integrated Phase Noise 100Hz to 40MHz FOUT = 1 GHz, fPFD = 400KHz, fSTEP =100 KHz, PLL BW = 35KHz, ICP=4mA -50 0.25 dBc ° rms VCO A Direct (3300MHz-3900MHz) – Open Loop(3) Phase Noise @ 1 KHz Phase Noise @ 10 KHz Phase Noise @ 100 KHz Phase Noise @ 1 MHz Phase Noise @ 10 MHz Phase Noise @ 40 MHz VCO B Direct (3800MHz-4400MHz) – Open Loop(3) Phase Noise @ 1 KHz Phase Noise @ 10 KHz Phase Noise @ 100 KHz Phase Noise @ 1 MHz Phase Noise @ 10 MHz Phase Noise @ 40 MHz VCO A with divider by 2 (1650MHz-1950MHz) – Open Loop(3) Phase Noise @ 1 KHz Phase Noise @ 10 KHz Phase Noise @ 100 KHz Phase Noise @ 1 MHz -62 -89 -111 -134 dBc/Hz dBc/Hz dBc/Hz dBc/Hz -55 -82 -104 -127 -147 -155 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz -56 -83 -105 -128 -148 -156 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz 12/42 STW81101 Table 6. Phase noise specification (continued) Parameter Phase Noise @ 10 MHz Phase Noise @ 20 MHz Phase Noise Floor @ 40 MHz VCO B with divider by 2 (1900MHz-2200MHz) – Open Loop(3) Phase Noise @ 1 KHz Phase Noise @ 10 KHz Phase Noise @ 100 KHz Phase Noise @ 1 MHz Phase Noise @ 10 MHz Phase Noise @ 20 MHz Phase Noise Floor @ 40 MHz VCO A with divider by 4 (825MHz-975MHz) – Open Loop(3) Phase Noise @ 1 KHz Phase Noise @ 10 KHz Phase Noise @ 100 KHz Phase Noise @ 1 MHz Phase Noise @ 10 MHz Phase Noise Floor @ 40 MHz VCO B with divider by 4 (950MHz-1100MHz) – Open Loop Phase Noise @ 1 KHz Phase Noise @ 10 KHz Phase Noise @ 100 KHz Phase Noise @ 1 MHz Phase Noise @ 10 MHz (3) Electrical specifications Test conditions Min Typ -150 -152 -154 Max Unit dBc/Hz dBc/Hz dBc/Hz -61 -88 -110 -133 -150 -152 -154 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz -68 -95 -117 -139 -151 -154 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz -67 -94 -116 -138 -151 -154 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz Phase Noise Floor @ 40 MHz 1. Phase Noise SSB. VCO amplitude setting to value [10]. All the closed-loop performances are specified using a Reference Clock signal at 76.8 MHz with phase noise of -135dBc/Hz @1KHz offset, -145dBc/Hz @10KHz offset and -149.5dBc/Hz of noise floor. 2. Normalized PN = Measured PN – 20log(N) – 10log(fPFD) where N is the VCO divider ratio (N=B*P+A) and fPFD is the comparison frequency at the PFD input 3. Typical Phase Noise at centre band frequency Upon request an Evaluation Kit is available including a powerful simulation tool (STWPLLSim) which allows to estimate very accurately the Phase Noise of the device according to the desired project parameters (VCO Frequency, Selected Output Stage, Reference Clock, Frequency Step, …); refer to the Application Information (Section 7) for more details. 13/42 Typical performance characteristics STW81101 3 Typical performance characteristics The phase noise is measured with the Agilent E5052A Signal Source Analyzer. All the closed-loop measurements are done with fPFD = 400 KHz and using a Reference Clock signal at 76.8 MHz with phase noise of -135dBc/Hz @1KHz offset, -145dBc/Hz @10KHz offset and -149.5dBc/Hz @1KHz of noise floor. Figure 3. VCO A (Direct output) closed loop phase noise at 3.6GHz with FSTEP=400KHz (FPFD=400KHz) Figure 4. VCO B (Direct output) closed loop phase noise at 4.0GHz with FSTEP=400KHz (FPFD=400KHz) 0.9° rms 1.0° rm s Figure 5. VCO A (Div. by 2 output) closed loop phase noise at 1.8GHz with FSTEP=200KHz (FPFD=400KHz) Figure 6. VCO B (Div. by 2 output) closed loop phase noise at 2.0GHz with FSTEP=200KHz (FPFD=400KHz) 0.45° rms 0.5° rm s 14/42 STW81101 Figure 7. VCO A (Div. by 4 output) closed loop phase noise at 900MHz with FSTEP=100KHz (FPFD=400KHz) Figure 8. Typical performance characteristics VCO B (Div. by 4 output) closed loop phase noise at 1.0GHz with FSTEP=100KHz (FPFD=400KHz) 0.24° rms 0.25° rms Figure 9. PFD Frequency Spurs (Div. by 2 Output; FPFD=400KHz) Figure 10. PFD Frequency Spurs (Div. by 4 Output; FPFD=400KHz) -82 dBc @400KHz -89 dBc @400KHz 15/42 General description STW81101 4 General description The block diagram of Figure 1 shows the different blocks, which have been integrated to achieve an integer-N PLL frequency synthesizer. The STW81101 consists of 2 internal low-noise VCOs with buffer blocks, a divider by 2, a divider by 4, a low-noise PFD (Phase Frequency Detector), a precise charge pump, a 10-bit programmable reference divider, two programmable counters and a programmable dualmodulus prescaler. The A-counter (5 bits) and B counter (12 bits) counters, in conjunction with the dual modulus prescaler P/P+1 (16/17 or 19/20), implement an N integer divider, where N = B*P +A. The division ratio of both reference and VCO dividers is controlled through the selected digital interface (I2C bus or SPI). The selection of the digital interface type is done by the proper hardware connection of the pin DBUS_SEL (0 V for I2C bus, 3.3 V for SPI). All devices operate with a power supply of 3.3 V and can be powered down when not in use. 4.1 4.1.1 Circuit description Reference input stage The reference input stage is shown in Figure 11. The resistor network feeds a DC bias at the Fref input while the inverter used as the frequency reference buffer is AC coupled. Figure 11. Reference Frequency Input Buffer VDD Fref INV BUF Power Down 4.1.2 Reference divider The 10-bit programmable reference counter allows the input reference frequency to be divided to produce the input clock to the PFD. The division ratio is programmed through the digital interface. 4.1.3 Prescaler The dual-modulus prescaler P/P+1 takes the CML clock from the VCO buffer and divides it down to a manageable frequency for the CMOS A and B counters. The modulus (P) is programmable and can be set to 16 or 19. It is based on a synchronous 4/5 core which division ratio depends on the state of the modulus input. 16/42 STW81101 General description 4.1.4 A and B counters The A (5 bits) and B (12 bits) counters, in conjunction with the selected dual modulus (16/17 or 19/20) prescaler make it possible to generate output frequencies which are spaced only by the reference frequency divided by the reference division ratio. Thus, the division ratio and the VCO output frequency are given by these formulas: N=B·P+A ( B ⋅ P + A ) ⋅ F ref F vco = -----------------------------------------R where: Fvco: output frequency of VCO. P: modulus of dual modulus prescaler (16 or 19 selected through the digital interface). B: division ratio of the main counter. A: division ratio of the swallow counter. Fref: input reference frequency. R: division ratio of reference counter. N: division ratio of PLL For a correct work of the VCO divider, B must be strictly higher than A. A can take any value ranging from 0 to 31. The range of the N number can vary from 256 to 65551 (P=16) or from 361 to 77836 (P=19). Figure 12. VCO Divider Diagram VCOBUF- Prescaler 16/17 or 19/20 VCOBUF+ modulus To PFD 5 bit A counter 12 bit B counter 4.1.5 Phase frequency detector (PFD) The PFD takes inputs from the reference and the VCO dividers and produces an output proportional to the phase error. The PFD includes a delay gate that controls the width of the anti-backlash pulse. This pulse ensures that there is no dead zone in the PFD transfer function. Figure 13 is a simplified schematic of the PFD. 17/42 General description Figure 13. PFD diagram VDD STW81101 D FF Fref Up R Delay R D FF Down ABL Fref VDD 4.1.6 Lock detect This signal indicates that the difference between rising edges of both UP and DOWN PFD signals is found to be shorter than the fixed delay (roughly 5 ns). Lock Detect signal is high when the PLL is locked. When Power Down is activated, Lock Detect is let to high level (Lock Detect consumes current only during PLL transients). 4.1.7 Charge pump This block drives two matched current sources, Iup and Idown, which are controlled respectively by UP and DOWN PFD outputs. The nominal value of the output current is controlled by an external resistor (to be connected to the REXT input pin) and a selection among 8 by a 3 bit word. The minimum value of the output current is: IMIN = 2*VBG/REXT (VBG~1.17 V) Table 7. CPSEL2 0 0 0 0 1 1 1 1 Current value vs selection CPSEL1 0 0 1 1 0 0 1 1 CPSEL0 0 1 0 1 0 1 0 1 Current IMIN 2*IMIN 3*IMIN 4*IMIN 5*IMIN 6*IMIN 7*IMIN 8*IMIN Value for REXT=4.7 KΩ 0.5 mA 1.0 mA 1.5 mA 2.0 mA 2.5 mA 3.0 mA 3.5 mA 4.0 mA Note: The current is output on pin ICP. During the VCO auto calibration, ICP and VCTRL pins are forced to VDD/2 18/42 STW81101 Figure 14. Loop filter connection VDD VCTRL General description BUF Charge Pump ICP C3 R3 R1 C1 BUF Cal bit C2 4.1.8 Voltage controlled oscillators VCO Selection Within STW81101 two low-noise VCOs are integrated to cover a wide band from 3300MHz to 4400MHz (direct output), from 1650MHz to 2200MHz (selecting divider by 2) and from 825MHz to 1100MHz (selecting divider by 4). VCO A frequency range 3300MHz-3900MHz VCO B frequency range 3800MHz-4400MHz VCO Frequency Calibration Both VCOs can operate on 32 frequency ranges that are selected by adding or subtracting capacitors to the resonator. These frequency ranges are intended to cover the wide band of operation and compensate for process variation on the VCO center frequency. An automatic selection of the range is performed when the bit SERCAL rises from "0" to "1". The charge pump is inhibited and the pins ICP & VCTRL are at VDD/2 volts. Then the ranges are tested to select the one which with this VCO input voltage is the nearest to the desired output frequency (Fout = N*Fref/R). When this selection is achieved the signal ENDCALB (which means End of Calibration) falls to "0", then the charge pump is enabled again and SERCAL should be reset to "0" before the next channel step. The PLL has just to perform fine adjustment around VDD/2 on the loop filter to reach Fout, which enables a fast settle. Figure 15. VCO Sub-Bands Frequency Characteristics 19/42 General description STW81101 The SERCAL bit should be set to "1" at each division ratio change. It should be noted that in order to reset the autocalibrator State Machine after a power-up, and anyway before the first calibration, the INITCAL bit should be set to "1" and back to "0" (this operation is automatically performed by the Power On Reset circuitry). The calibration takes approximately 7 periods of the PFD Frequency. The maximum allowed fPFD to perform the calibration process is 1 MHz. Using an higher FPFD the following procedure should be adopted: 1. 2. Calibrate the VCO at the desired frequency with an fPFD less than 1 MHz Set the A, B and R dividers ratio for the desired fPFD VCO Voltage Amplitude Control The bits A0 and A1 control the voltage swing of the VCO. The following table gives the voltage level expected on the resonator nodes. Table 8. Voltage level expected on the resonator nodes Code A[1:0] 00 01 10 11 Differential output voltage (Vp) 1.1 1.3 1.9 2.1 20/42 STW81101 I2C bus interface 5 I2C bus interface The I2C bus interface is selected by hardware connection of the pin #21 (DBUS_SEL) to 0 V. Data transmission from microprocessor to the STW81101 takes place through the 2 wires (SDA and SCL) I2C-BUS interface. The STW81101 is always a slave device. The I2C-bus protocol defines any device that sends data on to the bus as a transmitter and any device that reads the data as receiver. The device that controls the data transfer is known as the Master and the others as the slave. The master will always initiate the transfer and will provide the serial clock for synchronization. 5.1 5.1.1 General features Power ON reset The device at Power ON is able to configure itself to a fixed configuration, with all programmable bits set to factory default setting. 5.1.2 Data validity Data changes on the SDA line must only occur when the SCL is LOW. SDA transitions while the clock is HIGH are used to identify START or STOP condition. Figure 16. Data validity SDA SCL DATA LINE STABLE DATA VALID CHANGE DATA ALLOWED 5.1.3 START condition A Start condition is identified by a HIGH to LOW transition of the data bus SDA while the clock signal SCL is stable in the HIGH state. A Start condition must precede any command for data transfer. 5.1.4 STOP condition A LOW to HIGH transition of the data bus SDA identifies stop while the clock signal SCL is stable in the HIGH state. A STOP condition terminates communications between the STW81101 and the Bus Master. 21/42 I2C bus interface Figure 17. Start and Stop condition STW81101 SCL SDA START STOP 5.1.5 Byte format and acknowledge Every byte transferred on the SDA line must contain bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first. An acknowledge bit is used to indicate a successful data transfer. The bus transmitter, either master or slave, will release the SDA bus after sending 8 bits of data. During the 9th clock pulse the receiver pulls the SDA low to acknowledge the receipt of 8 bits data. Figure 18. Byte format and acknowledge SCL 1 2 3 // 7 8 9 SDA START MSB // ACKNOWLEDGMENT FROM RECEIVER 5.1.6 Device addressing To start the communication between the Master and the STW81101, the master must initiate with a start condition. Following this, the master sends onto the SDA line 8 bits (MSB first) corresponding to the device select address and read or write mode. The first 7 MSB's are the device address identifier, corresponding to the I2C-Bus definition. For the STW81101 the address is set as "1100A2A1A0", 3bits programmable. The 8th bit (LSB) is the read or write operation bit (RW; set to 1 in read mode and to 0 in write mode). After a START condition the STW81101 identifies on the bus the device address and, if matched, it will acknowledge the identification on SDA bus during the 9th clock pulse. 5.1.7 Single-byte write mode Following a START condition the master sends a device select code with the RW bit set to 0. The STW81101 gives an acknowledge and waits for the internal sub-address (1 byte). This byte provides access to any of the internal registers. After the reception of the sub-address internal byte the STW81101 again responds with an acknowledge. A single-byte write to sub-address 00H will change the "FUNCTIONAL_MODE" register, so a single-byte write with sub-address 04H will change the "CONTROL" register and so on. 22/42 STW81101 Table 9. S I2C bus interface Single-byte write mode 1100A2A1A0 0 ack sub-address byte ack DATA IN ack P 5.1.8 Multi-byte write mode The multi-byte write mode can start from any internal address. The master sends the data bytes and each one is acknowledged. The master terminates the transfer by generating a STOP condition. The sub-address decides the starting byte. A multi-byte with sub-address 01H and 2 DATA_IN bytes will change the "B_COUNTER" and "A_COUNTER" registers (01H,02H), so a multi-byte with sub-address 00H and and 6 DATA_IN bytes will change all the STW81101 registers. Table 10. S Multi-byte write mode 0 ack sub-address byte ack DATA IN ack .... DATA IN ack P 1100A2A1A0 5.1.9 Current byte address read In the current byte address read mode, following a START condition, the master sends the device address with the rw bit set to 1 (No sub-address is needed as there is only 1 byte read register). The STW81101 acknowledges this and outputs the data byte. The master does not acknowledge the received byte, but terminates the transfer with a STOP condition. Table 11. S Current Byte Address Read 1100 A2 A1 A0 1 ack DATA OUT No ack P 5.2 Timing specification Figure 19. Data and clock SDA SCL tcwl tcs tch tcwh Table 12. Data and clock Parameter Data to clock set up time Data to clock hold time Clock pulse width high Clock pulse width low Minimum time (ns) 2 2 10 5 Tcs Tch Symbol Tcwh Tcwl 23/42 I2C bus interface Figure 20. Start and stop STW81101 Table 13. Start and stop Parameter Clock to data start time Data to clock down stop time Minimum time (ns) 2 2 Symbol Tstart Tstop 5.2.1 Ack Figure 21. Ack SDA SCL 8 9 td1 td2 Table 14. Ack Parameter Ack begin delay Ack end delay Minimum time (ns) 2 2 Td1 Td2 Symbol 24/42 STW81101 I2C bus interface 5.3 I2C registers STW81101 has 6 write-only registers and 1 read-only register. The following table gives a short description of the write-only registers list. Table 15. Write-only registers list DEC CODE 0 1 2 3 4 5 DESCRIPTION FUNCTIONAL_MODE B_COUNTER A_COUNTER REF_DIVIDER CONTROL CALIBRATION HEX CODE 0x00 0x01 0x02 0x03 0x04 0x05 5.3.1 FUNCTIONAL_MODE MSB b7 PD6 b6 PD5 b5 PD4 b4 PD3 b3 PD2 b2 PD1 b1 PD0 LSB b0 B11 FUNCTIONAL_MODE register is used to select different functional mode for the STW81101 synthesizer according to the following table: Table 16. Different functional mode of the FUNCTIONAL_MODE register Description Power down mode Enable VCO A, output frequency divided by 2 Enable VCO B, output frequency divided by 2 Enable external VCO, output frequency divided by 2 Enable VCO A, output frequency divided by 4 Enable VCO B, output frequency divided by 4 Enable external VCO, output frequency divided by 4 Enable VCO A, direct output Enable VCO B, direct output Enable external VCO, direct output Decimal value 0 1 2 3 4 5 6 7 8 9 25/42 I2C bus interface STW81101 5.3.2 B_COUNTER MSB b7 B10 b6 B9 b5 B8 b4 B7 b3 B6 b2 B5 b1 B4 LSB b0 B3 B[10:3]. Counter value (bit B11 in the previous register, bits B[2:0] in the next register) 5.3.3 A_COUNTER MSB b7 B2 b6 B1 b5 B0 b4 A4 b3 A3 b2 A2 b1 A1 LSB b0 A0 Bits B[2:0] for B Counter, A Counter value. 5.3.4 REF_DIVIDER MSB b7 R9 b6 R8 b5 R7 b4 R6 b3 R5 b2 R4 b1 R3 LSB b0 R2 Reference Clock divider ratio R[9:1] (bits R1, R0 in the next register). 5.3.5 CONTROL MSB b7 R1 b6 R0 b5 PLL_ A1 b4 PLL_ A0 b3 CP SEL2 b2 CP SEL1 b1 CP SEL0 LSB b0 PSC_ SEL The CONTROL register is used to set the Charge Pump current, the VCO output voltage amplitude and the Prescaler Modulus. PLL_A[1:0]: VCO amplitude CPSEL[2:0]: Charge Pump output current PSC_SEL: Prescaler Modulus select ('0' for P=16, '1' for P=19) The LO output frequency is programmed by setting the proper value for A,B and R according to the following formula: F REF_CLK F OUT = D R ⋅ ( B ⋅ P + A ) ⋅ --------------------------R 26/42 STW81101 I2C bus interface where DR equals { 1 0.5 0.25 for Direct Output for Output Divided by 2 for Output Divided by 4 and P is the selected Prescaler Modulus 5.3.6 CALIBRATION MSB b7 INIT CAL b6 SER CAL b5 SEL EXT CAL b4 CAL4 b3 CAL3 b2 CAL2 b1 CAL1 LSB b0 CAL0 This register controls VCO calibrator. INITCAL: resets the auto-calibrator State Machine (writing to "1" and back to "0") SERCAL: at "1" starts the VCO auto-calibration (should be reset to "0" at the end of calibration) SELEXTCAL: test purpose only; must be set to '0' CAL[4:0]: test purpose only; must be set to '0' 5.3.7 READ-ONLY register MSB b7 DEV_ID1 b6 DEV_ID0 b5 LOCK_ DET b4 INT CAL4 b3 INT CAL3 b2 INT CAL2 b1 INT CAL1 LSB b0 INT CAL0 This register is automatically addressed in the 'current byte address read mode'. DEV_ID[1:0]: device identifier bits; returns '00' LOCK_DET: "1" when PLL is locked INTCAL[4:0]: internal value of the VCO control word 5.4 VCO calibration procedure The calibration of the VCO center frequency is activated by a '0' to '1' transition of the SERCAL bit (CALIBRATION Register bit[6]). In order to program properly the device, ensuring the VCO calibration, the following procedure is required before every channel change: a) Program all the Registers using a multi-byte write sequence with the desired settings (Functional Mode, B and A counters, R counter, VCO amplitude, Charge 27/42 I2C bus interface STW81101 Pump, Prescaler Modulus) and all the bits of the "CALIBRATION" Register (05H) set to '0' b) Program the "CALIBRATION" Register using a single-byte write sequence (subaddress 05H) with the SERCAL bit set to '1' The maximum allowed PFD frequency (fPFD) to perform the calibration process is 1 MHz; if the desired fPFD is higher than 1MHz the following steps are needed: – – Perform all the steps of the calibration procedure programming the desired VCO frequency with a proper setting of R, B and A counter so that fPFD is ≤ 1MHz. Program the device with the proper setting for the desired VCO and PFD frequencies according to the above step a) only. 28/42 STW81101 SPI digital interface 6 6.1 SPI digital interface General features The SPI digital interface is selected by hardware connection of the pin #21 (DBUS_SEL) to 3.3V. The STW81101 IC is programmed by means of a high-speed serial-to-parallel interface with write option only. The 3-wires bus can be clocked at a frequency as high as 100MHz to allow fast programming of the registers containing the data for RF IC configuration. The programming of the chip is done through serial words with whole length of 26 bits. The first 2 MSB represent the address of the registers. The others 24 LSB represent the value of the registers. Each Data bit is stored in the internal shift register on the rising edge of the CLOCK signal. On the rising edge of the LOAD signal the outputs of the selected register are sent to the device. Figure 22. SPI input and output bit order 29/42 SPI digital interface Table 17. MSB Address Data for Register (24 bits) STW81101 SPI data structure (MSB is sent first) LSB A1 A0 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Table 18. Address decoder and outputs Outputs A0 DATABITS D23-D0 24 24 24 24 No Name Function Reference divider, VCO amplitude, VCO Calibration, Charge Pump current, Prescaler Modulus Functional modes, VCO dividers Reserved Reserved Address A1 0 0 1 1 0 1 0 1 0 1 2 3 ST1 ST2 ST3 ST4 6.2 Timing specification Figure 23. SPI Timing specification Table 19. Parameter tsetup thold tclk tload tclk_loadr tclk_loadf SPI Timing specification Description DATA to CLOCK setup time DATA to clock hold time CLOCK cycle period LOAD pulse width CLOCK to LOAD rising edge CLOCK to LOAD falling edge Min. 0.8 0.2 10 3 2 0.5 Typ. Max. Unit ns ns ns ns ns ns 30/42 STW81101 SPI digital interface 6.3 Bits table Table 20. Bits Register name = ST1 Description Serial Interface Address = 00h Bit [23] [22] [21] [20] [19] [18] [17] [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] Name R9 R8 R7 R6 R5 REFERENCE CLOCK DIVIDER RATIO R4 R3 R2 R1 R0 PLL_A1 VCO Amplitude Control PLL_A0 CPSEL2 CPSEL1 CPSEL0 PSC_SEL INITCAL SERCAL SELEXTCAL CAL4 CAL3 CAL2 CAL1 CAL0 Prescaler Modulus select (‘0’ for P=16, ‘1’ for P=19) test purpose only; must be set to ‘0’ Enable VCO calibration (see paragraph xxx) test purpose only; must be set to ‘0’ test purpose only; must be set to ‘0’ Charge Pump output current Control 31/42 SPI digital interface Table 20. Bits (continued) Register name = ST1 Description STW81101 Serial Interface Address = 00h Bit [23] [22] [21] [20] [19] [18] Name PD6 PD5 PD4 PD3 PD2 PD1 [17] PD0 DEVICE FUNCTIONAL MODES 0. Power down 1. Enable VCO A, output frequency divided by 2 2. Enable VCO B, output frequency divided by 2 3. Enable external VCO, output frequency divided by 2 4. Enable VCO A, output frequency divided by 4 5. Enable VCO B, output frequency divided by 4 6. Enable external VCO, output frequency divided by 4 7. Enable VCO A, direct output 8. Enable VCO B, direct output 9. Enable external VCO, direct output [16] [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] B11 B10 B9 B8 B7 B6 B Counter Bits B5 B4 B3 B2 B1 B0 A4 A3 A2 A1 A0 A Counter Bits The LO output frequency is programmed by setting the proper value for A,B and R according to the following formula: F REF_CLK F OUT = D R ⋅ ( B ⋅ P + A ) ⋅ --------------------------R where DR equals { 1 0.5 0.25 for Direct Output for Output Divided by 2 for Output Divided by 4 and P is the selected Prescaler Modulus 32/42 STW81101 SPI digital interface 6.4 VCO calibration procedure The calibration of the VCO center frequency is activated by a '0' to '1' transition of the SERCAL bit (ST1 Register bit[6]). In order to program properly the device, ensuring the VCO calibration, the following procedure is required before every channel change: a) b) c) Program the ST1 Register with the desired settings (R counter, VCO amplitude, Charge Pump, Prescaler Modulus) and SERCAL bit set to '0' Program the ST2 Register with the desired settings (Functional mode, B and A counters) Program the ST1 Register with the desired settings (R counter, VCO amplitude, Charge Pump, Prescaler Modulus) and SERCAL bit set to '1' The maximum allowed PFD frequency (fPFD) to perform the calibration process is 1 MHz; if the desired fPFD is higher than 1MHz the following steps are needed: – – Perform all the steps of the calibration procedure programming the desired VCO frequency with a proper setting of R, B and A counter so that fPFD is ≤ 1MHz. Program the device with the proper setting for the desired VCO and PFD frequencies according to the above step a) and b) only. 33/42 Application information STW81101 7 Application information The STW81101 features three different alternatively selectable bands: direct output (3.3 to 4.4GHz), divided by 2 (1.65 to 2.2GHz) and divided by 4 (850 to 1100MHz). In order to achieve a suitable power level, a good matching network is needed to adapt the output stage to a 50Ω load. Moreover, since most of commercial RF components have single ended input and output terminations, a differential to single ended conversion could be required. Below different matching configurations for the three bands are suggested as a guideline for the design of own application board. The user can find in the Evaluation Kit the ADS Design for each matching configuration suggested in this section. The name of the corresponding ADS Design is reported below each figure. 7.1 Direct Output If a differential to single conversion is not needed it is possible to match the output buffer of the STW81101 in the simple way shown in Figure 24. Figure 24. Differential/single ended output network in the 3.3 - 4.4GHz range (MATCH_LC_LUMP_4G_DIFF.dsn) VCC 50 O hm 2 nH 50 O hm R FO UTP 10pF R F O UTN 50 O hm 10pF 50 O hm 2nH VCC Since most of discrete components for microwave applications are single ended, the user can easily use one of the two outputs and terminate the other one to 50Ω with a 3dB power loss. Alternatively it is possible to combine the 2 outputs in different ways. A first topology for the direct output (3.3GHz to 4.4GHz) is suggested in Figure 25. It basically consists of a simple LC balun and a matching network to adapt the output to a 50Ω load. The two LC networks shift output signal phase of -90° and +90° thus combining the 2 outputs. This topology, designed for a center frequency of 4GHz, is intrinsically narrow band, since the LC balun is tuned at a single frequency. If the application requires a different sub-band, the LC combiner could be easily adjusted to be tuned at the frequency of interest. 34/42 STW81101 Application information Figure 25. LC lumped balun and matching network (MATCH_LC_LUMP_4G.dsn) V CC 3.6nH 1.1nH 6.8nH 0.7pF RF O UTP 0.3pF 0.7pF 3.6nH 50 O hm 3.5nH RF O UTN 1.1nH 0.3pF The 6.8nH shunt inductor works as a DC feed for one of the open collector terminal as well as a matching element along with the other components. The 1.1nH series inductors are used to resonate the parasitic capacitance of the chip. For an optimum output matching it is recommended to use 0402 Murata or AVX capacitors and 0403 or 0604 HQ Coilcraft inductors. It is also advisable to use short interconnection paths to minimize losses and undesired impedance shift. An alternative topology, which allows for a more broadband matching and balanced to unbalanced conversion, is shown it Figure 26. Figure 26. Microstrip line and lumped matching network (MATCH_4G_HYBRID.dsn) VCC L=1.5nH C=0.7pF RFOUTP C=8pF W=16mil L=400mil 2:1 50Ohm load RFOUTN C=0.7pF L=1.5nH VCC Those results have been achieved on an FR4 substrate with a thickness of 350um. By using this topology the STW81101 is capable to deliver an almost flat power to a 50Ω load with a return loss grater than 10dB over the whole frequency band (3.3 to 4.4GHz). For the differential to single conversion the 50 to 100Ω Johanson balun is recommended (3700BL15B100). 35/42 Application information STW81101 7.2 Divided by 2 Output If the user's application does not require a balanced to unbalanced conversion, the output matching reduces to the simple circuit shown below (Figure 27). This solution can be easily used to provide one single ended output just terminating the other output at 50Ω with a 3dB power loss. Figure 27. Differential/single ended output network in the 1.65 - 2.2GHz range (MATCH_LC_LUMP_2G_DIFF.dsn) VCC 50 O hm 22nH 50 Ohm RFOUTP 10pF RFOUTN 50 O hm 10pF 50 Ohm 22nH VCC A first solution to combine the differential outputs is the lumped LC type balun tuned in the 2GHz band (Figure 28). Figure 28. LC lumped balun for divided by 2 output (MATCH_LC_LUMP_2G.dsn) VCC 5.5nH 3nH 1nH RFOUTP 1pF 2.8pF 5.5nH 2nH 50 O hm RFO UTN 3nH 1pF The same recommendation for the SMD components applies also for the divided by 2 output. Another topology suitable to combine the two outputs for the divided by 2 frequencies is represented in Figure 29. 36/42 STW81101 Figure 29. Lumped output matching for divided by 2 output (MATCH_LC_BAL_2G.dsn) VCC 50 O hm 22nH Application information RFO UTP 10pF 10pF 2:1 RFO UTN 50 Ohm 10pF 50 Ohm 22nH VCC For the differential to single conversion the 50 to 100Ω Johanson balun (1600BL15B100) is recommended. 7.3 Divided by 4 Output The same topology, components values and considerations of Figure 27, applies also for the divided by 4 output (MATCH_LC_LUMP_1G_DIFF.dsn). As for the previous sections, a solution to combine the differential outputs is the lumped LC type balun tuned in the 1GHz band (Figure 30). Figure 30. LC lumped balun for the divided by 4 output (MATCH_LC_LUMP_1G.dsn) VCC 25 Ohm 5.5nH 4pF 5.5nH RFOUTP 4pF 6pF 5.5nH 14nH 50 Ohm RFOUTN 4pF 25 Ohm 5.5nH 4pF VCC If the user prefers to use an RF balun it is possible to adopt the same topology depicted in Figure 29, just changing the balun and the resistor value (Figure 31). The suggested balun for the 0.8 - 1.1GHz frequency range is the 1:1 Johanson 900BL15C050. 37/42 Application information Figure 31. Lumped output matching for divided by 4 output (MATCH_LC_BAL_1G.dsn) STW81101 VCC 25 Ohm 22nH RFOUTP 10pF 10pF 1:1 RFOUTN 25 Ohm 10pF 50 Ohm 22nH VCC 7.4 Evaluation Kit Upon request an Evaluation Kit can be delivered. It includes: ● ● ● ● ● Evaluation Board GUI (Graphical User Interface) to program the device Measured S parameters of the RF output ADS2005 schematics providing guidelines for application board design STWPLLSim software for PLL loop filter design and noise simulation Three different Evaluation Kits are available, one optimized for 1GHz frequency range, one for 2GHz frequency range and the last one for 4GHz range. While ordering please specify the following order codes: Table 21. Order code of the evaluation kit Part Number STW81101-EVB1G STW81101-EVB2G STW81101-EVB4G Description 1GHz frequency range - Divider by 4 output optimized 2GHz frequency range - Divider by 2 output optimized 4GHz frequency range - Direct output optimized The three Evaluation Kits differ only regarding the output balun and the choke inductors of the related Evaluation Board; each Evaluation Kit is provided with the needed components (baluns and inductors) in order to easily adapt the output stage to a different frequency range. 38/42 STW81101 Application diagram 8 Application diagram Figure 32. Application diiagram From/to µ-controller 100 100 100 15p 15p 15p AD D0/LOAD SCL/CLK 1n 22p 10µ SDA/DATA EXT_PD ADD2 ADD1 VDD 1 VDD_DBUS I2C VDD_VCOA VDD_DIV2 DBUS_SEL VDD_BUFVCO SPI VDD 1 VDD_OUTBUF EXTVCO_INP 1n OUTBUFP VDD 2 22p 10µ RF Out 1:2 STW81101 EXTVCO_INN OUTBUFN VDD_PLL ref clk VDD_DIV4 VDD _CP REF_CLK LOCK_DET TEST2 1.8n 51 VDD 1 VDD 1 1n 22p 10µ VD D_ESD VCTR L ICP REXT 4.7K VDD 1 2.2K 8.2K 220p 6.8n 1n 22p 10µ loop filter 150p TEST1 VDD_VCOB to µ-controller Note: 1 2 3 See Application Information (Section 7) for further information on Output Matching topology. EXT_PD, ADD2, ADD1 (and ADD0 when I2C Bus is selected) can be hard wired directly on the board. Loop Filter values are for fPFD = 400KHz and ICP = 4mA. 39/42 Package information STW81101 9 Package information In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: http://www.st.com. Figure 33. VFQFPN28 Mechanical Data & Package Dimensions REF. A A1 A2 A3 b D D1 D2 E E1 E2 e L P K ddd 0.350 2.550 2.550 4.850 0.180 4.850 mm MIN. 0.800 TYP. 0.900 0.020 0.650 0.200 0.250 5.000 4.750 2.700 5.000 4.750 2.700 0.500 0.550 0.750 0.60 14˚ 0.080 0.014 2.850 0.100 2.850 5.150 0.100 0.191 0.300 5.150 MAX. 1.000 0.050 1.000 MIN. 0.031 inch TYP. 0.035 MAX. 0.039 OUTLINE AND MECHANICAL DATA 0.0008 0.0019 0.025 0.0078 0.007 0.0098 0.012 0.191 0.197 0.187 0.106 0.197 0.187 0.106 0.020 0.022 0.029 0.0236 14˚ 0.003 0.113 0.113 0.203 0.203 0.039 Notes: 1) VFQFPN stands for Thermally Enhanced Very thin Fine pitch Quad Packages No lead. Very thin: A = 1.00 Max. 2) The pin #1 identifier must be existed on the top surface of the package by using indentation mark or other feature of package body. Exact shape and size of this feature is optional. VFQFPN-28 (5x5x1.0mm) Very Fine Quad Flat Package No lead 7655832 A 40/42 STW81101 Revision history 10 Revision history Table 22. Date 06-Mar-2006 Document revision history Revision 1 Initial release. Changes 41/42 STW81101 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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