TDA7309D

TDA7309 DIGITAL CONTROLLED STEREO AUDIO PROCESSOR WITH LOUDNESS 1 FEATURES Figure 1. Packages ■ INPUT MULTIPLEXER: 3 STEREO INPUTS ■ RECORD OUTPUT FUNCTION ■ LOUDNESS FUNCTION ■ VOLUME CONTROL IN 1dB STEPS ■ INDEPENDENT LEFT AND RIGHT VOLUME CONTROL ■ SOFT MUTE FUNCTION ■ ALL FUNCTIONS PROGRAMMABLE VIA SERIAL I2C BUS 2 DIP20 SO20 Table 1. Order Codes DESCRIPTION The TDA7309 is a control processor with independent left and right volume control for quality audio applications. Selectable external loudness and soft mute functions are provided. Control is accomplished by serial I2C bus microprocessor interface. Part Number Package TDA7309 DIP20 TDA7309D SO20 TDA7309D013TR Tape & Reel The AC signal setting is obtained by resistor networks and switches combined with operational amplifiers. Thanks to the used BIPOLAR/CMOS Technology, Low Distortion, Low Noise and Low DC stepping are obtained. Figure 2. Block Diagram 100nF Recout(L) 3x 2.2µF 1 LOUD(L) 19 17 18 LEFT INPUTS VOLUME + LOUDNESS 20 2 OUT LEFT MUTE 6 INPUT SELECTOR 4 3x 2.2µF 5 SERIAL BUS DECODER + LATCHES 14 8 DIGGND SDA SCL BUS ADDR 13 RIGHT INPUTS VOLUME + LOUDNESS 11 SOFT MUTE TDA7309 SUPPLY 3 CSM 9 OUT RIGHT MUTE 16 VS 7 15 AGND CREF 10 Recout(R) D93AU045A 22µF March 2006 12 LOUD(R) 100nF Rev. 6 1/14 TDA7309 Figure 3. Pin Description RecoutL 1 20 IN3L OUTL 2 19 LOUDL CSM 3 18 IN2L SDA 4 17 IN1L SCL 5 16 VS DGND 6 15 CREF GND 7 14 IN1R ADD 8 13 IN2R OUTR 9 12 LOUDR 10 11 IN3R RecoutR D94AU058A Table 2. Absolute Maximum Ratings Symbol VS Parameter Value Unit 10.5 V –40 to 85 °C –55 to +150 °C Operating Supply Voltage Tamb Operating Ambient Temperature Tstg Storage Temperature Range Table 3. QUICK REFERENCE DATA Symbol Parameter Test Condition Min. VS Operating Supply Voltage 6 VCL Max. Input Signal Handling 2 THD S/N Total Harmonic Distortion Signal to Noise Ratio Sc V = 1Vrms, f = 1KHz Typ. Max. 10 0.1 100 Volume Control 1.0dB step % dB dB –95 Soft Mute Attenuation Direct Mute Attenuation V Vrms 0.01 106 Channel Separation f = 1KHz Unit 0 60 100 dB dB dB Table 4. Thermal Data Symbol Rth j-pins Parameter Thermal resistance Junction to Pins SO20 DIP20 Unit 150 100 °C/W Figure 4. Test Circuit IN1L IN2L IN3L RecoutL IN1R IN2R IN3R RecoutR 17 3 2 20 1 TDA7309 14 13 11 19 10 LL 12 LR 5 4 6 SCL SDA DIGGND OUTL 16 VS 15 CREF 7 AGND 9 OUTR 8 ADD D94AU057A 2/14 CSM 18 TDA7309 Table 5. Electrical Characteristcs (Refer to the test circuit, Tamb = 25°C, VS = 9V, RL = 10KΩ, RG = 50Ω, all controls flat (G = 0), f = 1KHz unless otherwise specified.) Symbol Parameter Test Condition Min. Typ. Max. Unit 5 (*) 9 10 V 7 10 mA 60 85 SUPPLY VS IS SVR Supply Voltage Supply Current Ripple Rejection dB INPUT SELECTORS RI Input Resistance 35 50 65 KΩ Sin Input Separation 80 90 dB 92 dB VOLUME CONTROL CRANGE Control Range AVMAX Max. Attenuation 87 92 95 dB ASTEP Step resolution 0.5 1 1.5 dB -1.2 1.2 dB -3 2 dB 2 dB EA Attenuation Set Error AV = 0 to -24dB AV = -24 to -56dB ET VDC Tracking Error DC Steps adjacent attenuation steps from 0dB to AV max Amute Output Mute Attenuation 80 0 3 mV 0.5 5 mV 100 dB Fast Mode 1 ms Slow Mode 20 ms 2.6 Vrms SOFT MUTE Td Delay Time Csmute = 22nF; 0 to –20dB AUDIO OUTPUTS VCLIP RL Clipping Level d = 0.3% Output Load Resistance Rout Output Impedance VDC DC Voltage Level 2 2 100 KΩ 200 300 Ω 3.8 V 2.5 µV GENERAL eNO Et S/N d SC Output Noise BW = 20-20KHz, flat; output muted all gains = 0dB 5 A curve all gains = 0dB 3 Total Tracking Error AV = 0 to –24dB AV = -24 to –56dB 0 0 Signal to Noise Ratio all gains = 0dB; VO = 1Vrms 95 Distortion 80 µV µV 1 2 106 0.01 Channel Separation 15 dB dB dB 0.1 100 % dB BUS INPUTS VIL Input Low Voltage VIH Input High Voltage IIN Input Current Vin = 0.4V VO Output Voltage SDA Acknowledge IO = 1.6mA 1 V +5 µA 0.8 V 3 V -5 0.4 (*) Hedevice work until 5V but no guarantee about SVR 3/14 TDA7309 Figure 5. Noise vs. Volume Setting. Figure 8. THD vs. RLOAD. Figure 6. SVRR vs. Frequency. Figure 9. Channel Separation vs. Frequency. Figure 7. THD vs. frequency Figure 10. Output Clip Level vs. Supply Voltage. 4/14 TDA7309 Figure 11. Quiescen Current vs. Supply Voltage Figure 13. Loudness vs. Frequency (CLOAD = 100nF) vs. Volume Figure 12. Loudness vs. Volume Attenuation Figure 14. Loudness vs. External Capacitors 5/14 TDA7309 3 I2C BUS INTERFACE Data transmission from microprocessor to the TDA7313 and viceversa takes place thru the 2 wires I2C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be connected). 3.1 Data Validity As shown in fig. 11, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW. 3.2 Start and Stop Conditions As shown in fig. 16 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. 3.3 Byte Format Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first. 3.4 Acknowledge The master (µP) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 17). The peripheral (audioprocessor) that acknowledges has to pull-down (LOW) the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during this clock pulse. The audioprocessor which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer. 3.5 Transmission without Acknowledge Avoiding to detect the acknowledge of the audioprocessor, the µP can use a simplier transmission: simply it waits one clock without checking the slave acknowledging, and sends the new data. This approach of course is less protected from misworking and decreases the noise immunity. Figure 15. Data Validity on the I2CBUS SDA SCL DATA LINE STABLE, DATA VALID CHANGE DATA ALLOWED D99AU1031 Figure 16. Timing Diagram of I2CBUS SCL I2CBUS SDA START 6/14 D99AU1032 STOP TDA7309 Figure 17. Acknowledge on the I2CBUS SCL 1 2 3 7 8 9 SDA MSB START ACKNOWLEDGMENT FROM RECEIVER D99AU1033 Table 6. SDA, SCL I2CBUS Timing Symbol Parameter Min. Typ. Max. Unit 400 kHz fSCL SCL clock frequency tBUF Bus free time between a STOP and START condition 1.3 µs Hold time (repeated) START condition. After this period, the first clock pulse is generated 0.6 µs tLOW LOW period of the SCL clock 1.3 µs tHIGH HIGH period of the SCL clock 0.6 µs tSU:STA Set-up time for a repeated START condition 0.6 µs tHD:DA Data hold time 0.300 µs tSU:DAT Data set-up time 100 ns tR Rise time of both SDA and SCL signals 20 300 ns (*) tF Fall time of both SDA and SCL signals 20 300 ns (*) Set-up time for STOP condition 0.6 tHD:STA tSU:STO 0 µs All values referred to VIH min. and VIL max. levels (*) Must be guaranteed by the I2C BUS master. Figure 18. Definition of Timing on the I2C-bus SDA tBUF tR tF tHIGH tHD;STA tSP tSU;STO SCL tLOW P S tHD;STA tHD;DAT tF tSU;STA tSU;DAT Sr D95AU314 P P = STOP S = START 7/14 TDA7309 4 SOFTWARE SPECIFICATION 4.1 Interface Protocol The interface protocol comprises: ■ A start condition (s) ■ A chip address byte, containing the TDA7309 address (the 8th bit of the byte must be 0). The TDA7309 must always acknowledge at the end of each transmitted byte. ■ A sequence of data (N-bytes + acknowledge) ■ A stop condition (P) Figure 19. ACK = Acknowledge S = Start P = Stop MAX CLOCK SPEED 400kbits/s Table 7. Chip address MSB LSB 0 0 1 1 0 0 1 0 pin address open 0 0 1 1 0 0 0 0 pin address close to ground Table 8. Function Codes MSB F6 F5 F4 F3 F2 F1 LSB VOLUME 0 X X X X X X X MUTE/LOUD 1 0 0 X X X X X INPUTS 1 0 1 X X X X X CHANNEL 1 1 0 X X X X X Table 9. Channel Abilitation Codec 8/14 MSB F6 F5 1 1 0 F4 F3 F2 F1 LSB FUNCTION channel X X X 0 0 RIGHT X X X 0 1 LEFT X X X 1 0 BOTH X X X 1 1 BOTH TDA7309 4.2 Power on reset condition 11111110 Table 10. Volume Codes MSB F6 F5 F4 F3 F2 F1 LSB 0 0 0 0dB 0 0 1 -1dB 0 1 0 -2dB 0 1 1 -3dB 1 0 0 -4dB 1 0 1 -5dB 1 1 0 -6dB 1 1 1 0 FUNCTION step 1dB 0 -7dB step 8dB 0 0 0 0 0dB 0 0 0 1 -8dB 0 0 1 0 -16dB 0 0 1 1 -24dB 0 1 0 0 -32dB 0 1 0 1 -40dB 0 1 1 0 -48dB 0 1 1 1 -56dB 1 0 0 0 -64dB 1 0 0 1 -72dB 1 0 1 0 -80dB 1 0 1 1 -88dB 1 1 X X MUTE Table 11. Mute Loudness Codes MSB F6 F5 1 0 0 F4 F3 F2 F1 LSB FUNCTION mute/loud X 0 0 slow soft mute on X 0 1 fast soft mute on 1 soft mute off 1 LOUD OFF X 0 0 loud on (10dB) X 1 0 loud on (20dB) 9/14 TDA7309 Table 12. Input Multiplexer Codes MSB F6 F5 1 0 1 F4 F3 F2 F1 LSB FUNCTION inputs X X X 0 0 MUTE X X X 0 1 IN2 X X X 1 0 IN3 X X X 1 1 IN1 Purchase of I2C Components of STMicrolectronics, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specifications as defined by Philips. 10/14 TDA7309 Figure 20. DIP20 Mechanical Data & Package Dimensions mm DIM. MIN. a1 0.254 B 1.39 TYP. inch MAX. MIN. TYP. MAX. 0.010 1.65 0.055 0.065 b 0.45 0.018 b1 0.25 0.010 D 25.4 1.000 E 8.5 0.335 e 2.54 0.100 e3 22.86 0.900 F 7.1 0.280 I 3.93 0.155 L OUTLINE AND MECHANICAL DATA 3.3 0.130 DIP20 Z 1.34 0.053 11/14 TDA7309 Figure 21. SO20 Mechanical Data & Package Dimensions mm inch DIM. MIN. TYP. MAX. MIN. TYP. MAX. A 2.35 2.65 0.093 0.104 A1 0.10 0.30 0.004 0.012 B 0.33 0.51 0.013 0.200 C 0.23 0.32 0.009 0.013 D (1) 12.60 13.00 0.496 0.512 E 7.40 7.60 0.291 0.299 e 1.27 0.050 H 10.0 10.65 0.394 0.419 h 0.25 0.75 0.010 0.030 L 0.40 1.27 0.016 0.050 k ddd OUTLINE AND MECHANICAL DATA 0˚ (min.), 8˚ (max.) 0.10 0.004 (1) “D” dimension does not include mold flash, protusions or gate burrs. Mold flash, protusions or gate burrs shall not exceed 0.15mm per side. SO20 0016022 D 12/14 TDA7309 Table 13. Revision History Date Revision Description of Changes January 2004 5 First Issue in EDOCS DMS March 2006 6 Modified on the page 8/14 the “MAX CLOCK SPEED” to 400kbits/s. 13/14 TDA7309 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZE REPRESENTATIVE OF ST, ST PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS, WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2006 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 14/14