TDA7463AD

TDA7463AD LOW VOLTAGE TONE CONTROL DIGITALLY CONTROLLED AUDIO PROCESSOR 1 ■ ■ ■ ■ ■ ■ ■ ■ ■ 2 Figure 1. Package FEATURES 2 STEREO INPUT 1 STEREO OUTPUT TREBLE BOOST BASS CONTROL BASS AUTOMATIC LEVEL CONTROL VOLUME CONTROL IN 1dB STEPS MUTE STAND-BY FUNCTION SOFTWARE CONTROLLED ALL FUNCTION ARE PROGRAMMABLE VIA SERIAL BUS SSO20P Table 1. Order Codes ct TREBLE-R C1 0.47µF amplifiers. IN2-R u d o 18 50K r P e C2 0.47µF IN1-R 19 INPUT SELECT o r P e t le Thanks to the used BIPOLAR/CMOS Technology, Low Distortion, Low Noise and DC stepping are obtained. o s b O R5 5.6K 100nF BASSI-R 17 ) s t( The AC signal setting is obtained by resistor networks and switches combined with operational Bass ALC (Automatic Level Control) function can be adjusted by a dedicated pin. (s) SSO20P c u d The TDA7463AD is a volume tone (bass and treble) processor for quality audio applications in Low voltage supply portable systems. C14 3.3nF Package TDA7463AD The control of all the functions is accomplished by serial bus. DESCRIPTION Figure 2. Block Diagram Part Number 100nF C13 C12 16 BASSO-R 15 RB -63dB CONTROL 0/-10dB x1 BASS TREBLE 14 OUT-R x5 50K t e l o C3 0.47µF s b O ALC 20 VS BASS_ALC CONTROL HALF_WAVE RECTIFIER C4 0.47µF 9 SDA 3 BASS VS 2 3 DGND SCL SDA OUT-L 7 x1 -63dB CONTROL 1 4 x5 TREBLE C5 0.47µF R4 1KΩ I2C BUS DECODER + LATCHES + 2 50K 0/-10dB 50K RB 4 C6 3.3nF 6 BASSI-L C7 100nF 11 BASSO-L C8 100nF R2 5.6K VS SUPPLY VREF 5 TREBLE-L D99AU1049 November 2005 SCL R1 1M IN1-L IN2-L 10 I2C VS R3 1KΩ GND VS 1 C10 100nF 12 C11 100µF CREF C9 22µF REV. 4 1/13 TDA7463AD Table 2. Absolute Maximum Ratings Symbol VS Parameter Value Unit 5 V Operating Supply Voltage Tamb Operating Ambient Temperature -10 to 85 °C Tstg Storage Temperature Range -55 to 150 °C Figure 3. Pin Connection (Top view) VS 1 20 ALC IN1-L 2 19 IN1-R IN2-L 3 18 IN2-R TREBLE-L 4 17 TREBLE-R BASSI-L 5 16 BASSI-R BASSO-L 6 15 BASSO-R OUT-L 7 14 OUT-R N.C. 8 13 N.C. SDA 9 12 CREF SCL 10 11 GND c u d D99AU1050 e t le Table 3. Thermal Data Symbol Rth j-pin Parameter Thermal Resistance Junction-pins ) s ( ct Table 4. Quick Reference Data Symbol o r P e du o s b O - Parameter VS Supply Voltage VCL Max. input signal handling Value Unit 85 °C/W Typ Max Unit 1.8 2.4 3 V 0.2 Vrms THD Total Harmonic Distortion V = 0.1Vrms; f = 1KHz S/N Signal to Noise Ratio V out = 0.1Vrms (mode = OFF) 80 dB Channel Separationf = 1KHz 80 dB bs SC 0.1 % Volume Control (1dB step) -63 0 dB -10dB damping -10 0 dB 14dB 0 14 dB Treble Control 0 8 dB Bass Control 0 14 dB Mute Attenuation 2/13 o r P Min t e l o O ) s t( 100 dB TDA7463AD Table 5. ELECTRICAL CHARACTERISTCS (refer to the test circuit Tamb = 25°C, VS =2.4V, RL = 10KΩ, RG = 600Ω, all controls flat, unless otherwise specified) Symbol Parameter Test Condition Min. Typ. Max. 1.8 2.4 3 Unit SUPPLY VS Supply Voltage IS Supply Current 4 mA IST-BY Stand-By Current 50 µA SVR Ripple Rejection 70 dB V INPUT STAGE RIN Input Resistance VCL Clipping Level 35 THD = 0.3% 50 65 0.2 K& Vrms VOLUME CONTROL CRANGE Control Range 63 dB ) s t( AV MIN Min Attenuation -1 0 1 AV MAX Max. Attenuation 62 63 64 dB ASTEP Step Resolution 1 dB Amute Mute Attenuation uc A-10dB -10dB damping G14dB 14dB gain 80 BASS CONTROL (1) Gb Control Range RB Internal Feedback Resistance TREBLE CONTROL (1) Control Range Gt RL d = 0.3% Output Load Resistance DC Voltage Level u d o GENERAL Output Noise ENO Et s b O d r P e Signal to Noise Ratio 14 dB 14 dB 45 56.25 dB KΩ dB 0.2 VRMS 10 K& 0.8 V Outout Muted All gains = 0dB; BW = 20Hz to 20KHz flat 5 8 µV µV All gains 0dB; VO = 0.1VRMS ; 80 dB 80 dB 0 Channel Separation Left/Right Distortion od dB 10 8 Total Tracking Error t e l o S/N SC ) s ( ct Clipping Level VDC o s b O - 33.75 Max. Boost on AUDIO OUTPUTS VCLIP e t le Max. Boost/on Pr 100 dB AV = 0; VI = 0.1VRMS ; 1 0.1 dB % BUS INPUT VIL Input Low Voltage VIH Input High Voltage 0.5 IIN Input Current VIN = 0.4V VO Output Voltage SDA Acknowledge IO = 1.6mA 1.9 -5 V V 5 µA 0.4 V Note: 1. BASS and TREBLE response: The center frequency and the response quality can be chosen by the external circuitry. 3/13 TDA7463AD 3 I2C BUS INTERFACE Data transmission from microprocessor to the TDA7463AD and vice versa takes place through the 2 wires I2C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be connected). 3.1 Data Validity As shown in fig. 4, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW. 3.2 Start and Stop Conditions As shown in fig.5 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. 3.3 Byte Format Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first. ) s t( 3.4 Acknowledge The master (µP) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 6). The peripheral (audio processor) that acknowledges has to pull-down (LOW) the SDA line during this clock pulse. The audio processor which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer. c u d e t le o r P o s b O - 3.5 Transmission without Acknowledge Avoiding to detect the acknowledge of the audio processor, the µP can use a simpler transmission: simply it waits one clock without checking the slave acknowledging, and sends the new data. This approach of course is less protected from misworking. ) s ( ct Figure 4. Data Validity on the I2CBUS u d o SDA r P e SCL t e l o s b O DATA LINE STABLE, DATA VALID CHANGE DATA ALLOWED D99AU1031 Figure 5. Timing Diagram of I2CBUS SCL I2CBUS SDA START 4/13 D99AU1032 STOP TDA7463AD Figure 6. Acknowledge on the I2CBUS SCL 1 2 3 7 8 9 SDA MSB START 4 ACKNOWLEDGMENT FROM RECEIVER D99AU1033 SOFTWARE SPECIFICATION 4.1 Interface Protocol The interface protocol comprises: ■ A start condition (S) ■ A chip address byte, containing the TDA7463AD address ■ A subaddress bytes ■ A sequence of data (N byte + acknowledge) ■ A stop condition (P) c u d Figure 7. CHIP ADDRESS SUBADDRESS MSB S 1 LSB 0 0 0 1 0 0 0 MSB ACK X X B D96AU420 ACK = Acknowledge S = Start P = Stop A = Address B = Auto Increment 5 ) s ( ct o r P DATA 1 to DATA n e t le LSB X ) s t( MSB so DATA ACK LSB DATA ACK P b O - u d o DATA BYTES r P e Address = (HEX) 10001000 t e l o 5.1 FUNCTION SELECTION: The first byte (subaddress) s b O MSB D7 LSB SUBADDRESS D6 D5 D4 D3 D2 D1 D0 X X B 0 0 0 0 STAND-BY & TREBLE & OTHERS X X B 0 0 0 1 BASS X X B 0 0 1 0 VOLUME B = 1 incremental bus; active B = 0 no incremental bus; X = indifferent 0,1 5/13 TDA7463AD 5.1.1 STAND_BY & TREBLE & OTHERS MSB D7 LSB D6 D5 D4 D3 D2 D1 D0 STAND-BY 1 ALL CIRCUITS STOP TREBLE 1 STAND-BY (Treble block stops) 1 0 BOOST OFF 0 0 BOOST ON 1 0 0 High Boost (+8dB) 0 0 0 Low Boost (+4dB) MUTE 1 Input Mute ON 0 Input Mute OFF 1 Output Mute ON 0 Output Mute OFF BASS c u d ) s t( o r P 1 Release Current Circuit ON 0 Release Current Circuit OFF e t le INPUT Select so 1 0 5.1.2 BASS MSB D7 D6 D5 D4 D3 ct u d o r P e t e l o s b O 0 0 1 1 6/13 0 1 0 1 1 0 1 0 0 0 0 1 1 0 1 1 (s) D2 b O D1 1 0 0 0 LSB D0 1 INPUT 1 INPUT 2 BASS STAND-BY (Bass block stops) BASS (boost OFF) BASS (boost ON) High boost (Ex. + 14dB) Low boost (Ex. + 6dB) ALC mode OFF (ALC block stops) ALC mode ON Attack time resistor (12.5K&) Release current (0.4 A) Attack time resistor (25K&) Release current (0.2 A) Attack time resistor (50K&) Release current (0.1 A) Attack time resistor (100K&) Release current (0.05 A) Threshold1 (0.2Vrms) Threshold2 (0.14Vrms) Threshold3 (0.1Vrms) Threshold4 (0.07Vrms) TDA7463AD 5.1.3 VOLUME MSB D7 D6 D5 D4 D3 LSB VOLUME 1 dB STEPS D2 D1 D0 0 0 0 0 0 0 1 -1 0 1 0 -2 0 1 1 -3 1 0 0 -4 1 0 1 -5 1 1 0 -6 1 1 1 -7 8 dB STEPS 0 0 0 0 0 0 1 -8 0 1 0 -16 0 1 1 -24 1 0 0 1 0 1 1 1 0 1 1 1 1 0 1 0 t e l o o r P e c u d (t s) e t le c u d ) s t( o r P -32 b O - so -40 -48 -56 OUTPUT GAIN 0dB +14dB OUTPUT ATTENUATION 0dB -10dB VOLUME: 0 ~ -63dB s b O 7/13 TDA7463AD 5.2 ALC IN general: 5.2.1 VOLUME setting with ALC Target Volume [dB] Volume [dB] Output Gain 0/+14dB 0/+14dB Output Attenuation 0/-10dB [dB] 0 -14 +14 0 -1 -15 -2 -16 -3 -17 -4 -18 -5 -19 -6 -20 -7 -21 -8 -22 -9 -23 -10 -24 -11 -25 -12 -26 -13 -27 -14 -14 -15 -15 -16 -16 -17 -17 -18 -18 -19 -19 ) s ( ct -20 -20 -21 -22 o r P e -23 -24 -25 t e l o -26 s b O 8/13 du c u d e t le 0 o r P 0 o s b O - -21 -22 -23 -14 -15 -16 -27 -17 : : : : -70 -60 -71 -61 -72 -62 -73 -63 0 -10 ) s t( TDA7463AD Figure 8. PIN: IN-L, IN-R Figure 11. PIN: OUT-L, OUT-R VS VS 20µA 20µA 10Ω 50K GND GND Vref D99AU1107 D99AU1106 Figure 9. PIN: TREBLE-L, TREBLE-R Figure 12. PIN: SCL, SDA c u d VS 20µA e t le 25K GND ) s ( ct D99AU1108 du Figure 10. PIN: BASSI-L, BASSI-R o r P e VS t e l o s b O GND o s b O - ) s t( o r P GND D99AU1109 Figure 13. PIN: BASSO-L, BASSO-R VS 20µA 20µA 45K 45K GND BASSO-L,BASSO-R D99AU1110 BASSI-L,BASSI-R D99AU1111 9/13 TDA7463AD Figure 14. PIN: ALC Figure 16. BASS ALC: Threshold Curve VO (Vrms) VS D99AU1115 Bass boost without ALC VS=1.8V; f=100Hz; Volume=-14dB; Output gain=+14dB Intern. release circuit=ON Bass boost with ALC 20µA Threshold: 8dB 11dB 14dB 0.1 17dB 100K Bass= +14dB boost flat GND D99AU1112 0.01 0.01 Figure 15. PIN: CREF 0.1 Figure 17. BAS ALC: THD THD V =1.8V; f=100Hz; S (%) Volume=-14dB; 1 Threshold o s b O - 14d B 1K e t le Bass boost with ALC 0.1 (s) GND D99AU1113 ct u d o r P e s b O 10/13 17dB D99AU1114 o r P 8dB 20µA Output gain=+14dB Intern. release circuit=ON c u d ) s t( B 10 11d VS t e l o VI(Vrms) Bass boost without ALC 0.01 0.001 0.01 flat 0.1 VI(Vrms) TDA7463AD Figure 18. SSOP20 Mechanical Data & Package Dimensions mm inch DIM. MIN. TYP. A MAX. MIN. TYP. 2.000 A1 0.050 A2 1.650 b MAX. 0.079 0.002 1.850 0.065 0.220 0.380 0.009 0.015 c 0.090 0.250 0.005 0.010 D (1) 6.900 7.200 7.500 0.272 0.283 0.295 E 7.400 7.800 8.200 0.291 0.307 0.323 E1 (1) 5.000 5.300 5.600 0.197 0.209 0.220 e (2) L 1.750 0.650 0.550 L1 0.750 0.069 0.073 0.026 0.950 0.022 1.250 k OUTLINE AND MECHANICAL DATA 0.029 0.037 0.049 c u d ddd 0˚ (min.), 4˚ (typ.), 8˚ (max.) 0.100 0.004 Notes: 1. D and E1 does not include mold flash or protrusions, but do include mold mismatch and are measured at datum plane “H”. Mold flash or potrusions shall not exceed 0.20mm (.008inch) both side. 2. “b” dimensions does not include dambar protusion/intrusion. ) s ( ct e t le ) s t( o r P SSOP20 o s b O - u d o r P e t e l o s b O 0061436 C (Jedec MO-150-AE) 11/13 TDA7463AD Table 6. Revision History Date Revision Description of Changes January 2004 2 First Issue in EDOCS DMS June 2004 3 Changed the Style-sheet in compliance to the new “Corporate Technical Pubblications Design Guide” November 2005 4 Add section 3 and 4 c u d e t le ) s ( ct u d o r P e t e l o s b O 12/13 o s b O - o r P ) s t( TDA7463AD c u d e t le ) s ( ct ) s t( o r P o s b O - u d o r P e t e l o s b O Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners © 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 13/13