TDA8215B

TDA8215B HORIZONTAL AND VERTICAL DEFLECTION CIRCUIT FEATURES SUMMARY ■ DIRECT LINE DARLINGTON DRIVE Figure 1. Package ■ DIRECT FRAME-YOKE DRIVE (± 1A) ■ COMPOSITE VIDEO SIGNAL INPUT CAPABILITY ■ FRAME OUTPUT PROTECTION AGAINST SHORT CIRCUITS ■ PLL ■ VIDEO IDENTIFICATION CIRCUIT ■ SUPER SANDCASTLE OUTPUT ■ VERY FEW EXTERNAL COMPONENTS ■ VERY LOWCOST POWER PACKAGE POWERDIP 16 + 2 + 2 (Plastic Package) DESCRIPTION The TDA8215B is an horizontal and vertical deflection circuit with super sandcastle generator and video identification output. Used with TDA8213 (Video & Sound IF system) and TDA8217 (Pal decoder and video processor), this IC permits a complete low-cost solution for PAL applications. The TDA8215B has been specially designed for direct drive of line DARLINGTON transistors. Figure 2. Pin Connections VCC1 1 20 VIDEO INPUT FRAME OSCILLATOR 2 19 SUPER SANDCASTLE OUTPUT VCC2 3 18 LINE FLYBACK INPUT FRAME FLYBACK GENERATOR 4 17 LINE OUTPUT GROUND 5 16 GROUND GROUND 6 15 GROUND POWER AMPLIFIER INPUT 7 14 RC NETWORK VIDEO IDENTIFICATION OUTPUT 8 13 LINE SAWTOOTH INPUT FRAME POWER SUPPLY 9 12 PHASE DETECTOR 10 11 LINE OSCILLATOR FRAME OUTPUT REV. 2 May 2004 1/15 TDA8215B Figure 3. Block Diagram VCC2 VCC1 Video Identification 1 2 9 8 Frame blanking detector Frame oscillator 19 Σ 3 4 + Power stage Flyback generator - YOKE 10 Video Input 2µs 20 18 7 Frame-Synchro generator Line flyback detector Output stage 17 Phase detector Input stage Line oscillator Burst gate pulse generator 2µs 14 13 12 11 Line Flyback VCC1 VCC1 Table 1. Absolute Maximum Ratings Symbol Parameter Value Unit VCC1 Supply Voltage 30 V VCC2 Flyback Generator Supply Voltage 35 V Frame Power Supply Voltage 60 V ± 1.5 A V9 I10NR Frame Output Current (non repetitive) I10 Frame Output Current (continuous) ±1 A V17 Line Output Voltage (external) 60 V Ip17 Line Output Peak Current 0.8 A IC17 Line Output Continuous Current 0.4 A TSTG Storage Temperature –40 to 150 °C Max Operating Junction Temperature + 150 °C Operating Ambient Temperature 0 to 70 °C Value Unit TJ TAMB Table 2. Thermal Data Symbol Parameter RTH(j-c) Max Junction-case Thermal Resistance 10 °C/W RTH(j-a) Typical Junction-ambient Thermal Resistance (Soldered on a 35µm thick 45cm2 PC Board copper area) 40 °C/W Max Recommended Junction Temperature 120 °C TJ 2/15 TDA8215B ELECTRICAL CHARACTERISTICS VCC1 = 10V, TAMB = 25°C (unless otherwise specified) Table 3. Supply (Pin 1) Symbol Parameter ICC1 Supply Current VCC1 Supply Voltage Min. Typ. Max. 15 Unit mA 9 10 10.5 V Min. Typ. Max. Unit Reference Voltage (I20 = -1µA) 1.4 1.75 2 V Minimum Width of Frame Pulse (When synchronized with TTL signal) 50 Table 4. Video Input (Pin 20) Symbol V20 MWF Parameter µs Table 5. Line Oscillator (Pin 11) Symbol Parameter Min. Typ. Max. Unit LT11 Low Threshold Voltage 2.8 3.2 3.6 V HT11 High Threshold Voltage 5.4 6.6 7.8 V BI11 Bias Current DR11 Discharge Impedance 1.0 1.4 1.8 kΩ FLP1 Free Running Line Period (R = 34.9kΩ Tied to VCC1, C = 2.2nF Tied to Ground) 62 64 66 µs FLP2 Free Running Line Period (R = 13.7KΩ, C = 2.2nF) 27 µs OT11 Oscillator Threshold for Line Output Pulse Triggering 4.6 V 2 Hz/°C ∆F ------∆0 100 Horizontal Frequency Drift with Temperature (see application) nA Table 6. Line Output (Pin 17) Symbol Parameter LV17 Saturation Voltage (I17 = 800mA during 2µs) OPW Output Pulse width (line period = 64µs, negative pulse) Min. Typ. Max. 2.2 Unit V 19 21 23 µs Min. Typ. Max. Unit Table 7. Line Sawtooth Input (Pin 13) Symbol Parameter V13 Bias Voltage 1.8 2.4 3.2 V Z13 Input Impedance 4.5 5.8 8 kΩ 3/15 TDA8215B Table 8. Phase Detector (Pin 12) Symbol Min. Typ. Max. Unit Output Current During Synchro Pulse 250 350 500 µA RI12 Current Ratio (positive/negative) 0.95 1 1.05 LI12 Leakage Current CV12 Control Voltage Range I12 Parameter –2 +2 µA 2.60 7.10 V Table 9. Video Identification (Pin 8) Symbol Parameter Min. Typ. Max. Unit 4.5 6.3 0.9 V 0.6 0.9 V Min. Typ. Max. Unit Low Level Output when the line synchro tip is centered in the line retrace VH8 Without Video Signal (I8 = -500µA) VL8 With Video Signal (I8 = 50µA) Table 10. Frame Oscillator (Pin 2) Symbol Parameter LT2 Low Threshold Voltage 1.6 2.0 2.3 V HT2 High Threshold Voltage 2.6 3.1 3.6 V DIF2 LT2 - HT2 1.0 V BI2 Bias Current 30 nA DR2 Discharge Impedance 300 470 700 Ω FFP1 Free Running Frame Period (R = 845kΩ Tied to VCC1, C = 180nF Tied to Ground) 20.5 23 25 ms MFP Minimum Frame Period (I20 = –100µA) with the Same RC 12.8 ms FFP2 Free Running Frame Period (R = 408kΩ, C = 220nF) 14.3 ms FPR Frame Period Ratio = FFP/MFP FG Frame Saw-tooth Gain Between Pin 1 and non Inverting Input of the Frame Amplifier ∆F ------∆0 Vertical Frequency Drift with Temperature (see application) 1.7 1.8 1.9 –0.4 Hz/°C 4.10–3 Table 11. Frame Power Supply (Pin 9) Symbol Parameter V9 Operating Voltage (with flyback Generator) I9 Supply Current (V9 = 30V) Min. Typ. Max. Unit 58 V 11 22 mΑ Typ. Max. Unit 30 V 10 Table 12. Flyback Generator Supply (Pin 3) Symbol VCC2 4/15 Parameter Operating Voltage Min. 10 TDA8215B Table 13. Frame Output (Pin 10) Symbol Parameter Min. Typ. Max. Unit Saturation Voltage to Ground (V9 = 30V) LV10A I10 = 0.1A 0.06 0.6 V LV10B I10 = 1A 0.37 1 V Saturation Voltage to V9 (V9 = 30V) HV10A I10 = –0.1A 1.3 1.6 V HV10B I10 = –1A 1.7 2.4 V Saturation Voltage to V9 in Flyback Mode (V10 > V9) FV10A I10 = 0.1A 1.6 2.1 V FV10B I10 = 1A 2.5 4.5 V Typ. Max. Unit Table 14. Flyback Generator (Pin 3 and Pin 4) Symbol Parameter Min. Flyback Transistor on (output = high state), VCC2 = 30V, V4/3 with F2DA I4 →3 = 0.1A 1.5 2.1 V F2DB I4 →3 = 1A 3.0 4.5 V Flyback Transistor on (output = high state), VCC2 = 30V, V3/4 with FSVA I3 →4 = 0.1A 0.8 1.1 V FSVB I3 →4 = 1A 2.2 4.5 V 170 µA Flyback Transistor off (output = V9 - 8V), V9 - VCC2 = 30V FCI Leakage Current Pin 3 Table 15. Super Sandcastle Output (Pin 19) Symbol Parameter Min. Typ. Max. Unit Output Voltages (R load = 2.2kΩ) SANDT2 Frame blanking pulse level 2 2.5 3 V SANDL2 Line blanking pulse level 4 4.5 5 V Burst key pulse level 8 9 BG2 V Pulses width and timing SC3 Delay between middle of sync pulse and leading edge of burst key pulse 2.3 2.7 3.1 µs SC2 Duration of burst key pulse Vertical blanking pulse width 3.7 4 Note 1 5 µs Note: 1. Width of vertical blanking pulse on SSC output is proportional to the frame flyback time, the switching level is VCC2 -2VBE and the other input of the comparator is tied to the frame amplifier output. Application circuit uses the frame flyback generator. 5/15 TDA8215B Table 16. Line Flyback Input (Pin 18) Symbol Parameter Typ. Max. Unit Switching level 2 V Maximum input current at VPEAK = 800V 8 mA 4.3 V 6 µs Limiting voltage at maximum current τ Min. RC network time constant (Note 1) Note: 1. An RC network is connected to this input. Typical value for the resistor is 27kΩ and 220pF for the capacitor. A different time constant for RC changes the delay between the middle of the line synchro pulse and the leading edge of the burst key pulse but also the duration of the burst key pulse. 6/15 TDA8215B GENERAL DESCRIPTION The TDA8215B performs all the video and power functions required to provide signals for the line driver and frame yoke. It contains: – A synchronization separator – An integrated frame separator without external components – A saw-tooth generator for the frame – A power amplifier for direct drive of frame yoke (short circuit protected) – An open collector output for the line darlington drive – A line phase detector and a voltage control oscillator – A super sandcastle generator – Video identification output. The slice level of sync-separation is fixed by value of the external resistors R1 and R2. VR is an internally fixed voltage. The sync-pulse allows the discharge of the capacitor by a 2 x I current. A line sync-pulse is not able to discharge the capacitor under VZ/2. A frame sync-pulse permits the complete discharge of the capacitor, so during the frame sync-pulse Q3 and Q4 provide current for the other parts of the circuit. Figure 4. Synchronization Separator Circuit SL1 SL2 VR 20 R1 Video R2 Figure 5. Frame Separator VZ Q3 Q4 l ST1 ST2 VZ/2 SL1 3l 7/15 TDA8215B Figure 6. Line Oscillator VCC1 R5 11 Phase comparator output R4 The oscillator thresholds are internally fixed by resistors. The discharge of the capacitor depends on the internal resistor R4. The control voltage is applied on resistor R5. The sync-pulse drives the current in the comparator. The line flyback integrated by the external net work gives on pin 13 a saw tooth, the DC offset of this saw tooth is fixed by VC. The comparator output provides a positive current for the part of the signal on pin 13 greater than to VC and a negative current for the other part.When the line flyback and the video signal are synchronized, the output of the comparator is an alternatively negative and positive current. The frame sync-pulse inhibits the comparator to prevent frequency drift of the line oscillator on the frame beginning. 8/15 Figure 7. Phase Comparator Line Flyback Integrated Flyback Sinc pulse Output Current VC TDA8215B Figure 8. Line output (Pin 17) It is an open-collector output. The output negative pulse time is 22µs for a 64µs period. The oscillator thresholds are internally fixed by resistors. The oscillator is synchronized during the last half free run period. The input current during the charge of the capacitor is less than 100nA. VCC1 12 13 VC SL2 ST1 Figure 9. Frame Oscillator VCC1 INPUT CURRENT COMPENSATION 2 Frame sync pulse To frame amplifier Frame output amplifier This amplifier is able to drive directly the frame yoke. Its output is short circuit and overload protected; it contains also a thermal protection. The frame blanking is detected by the frame flyback generator. When the output voltage of the frame amplifier exceeds VCC2-2VBE, the pulse is detected. The line flyback detection is provided by a comparator which compares the input line flyback pulse to an internal reference. The burst gate pulse position is fixed by the external RC network (Pin 14). It is referenced to the middle of the line flyback. This stage will detect the coincidence between the line sync pulse (if present) and a 2µs sampling pulse. This 2µs pulse is positioned at the center of line sync pulse when the phase loop is locked. This sampled detection is stored by an external capacitor Pin 8. The identification output level is high when video signal is present. Important remark: minimum saw-tooth amplitude on Pin 13 has to be 2VPP (typ.: 2.5VPP). 9/15 TDA8215B Figure 10. Super Sandcastle Generator VCC1 Line Flyback Input 18 Frame Output 10 VCC1 Line Flyback Detection Σ Frame Blanking Detection Burst gate pulse generator RC 19 SSC Output 400µA YOKE RC Network 14 Figure 11. Video Identification Circuit (Pin 8) VH 2.75V Line retrace + 12µs 5.8Ω 13 Line Flyback VR 2.5V + VL 2.25V Integrated Flyback - VR VL VCC1 VCC1 10kΩ Video Ident. Output VH Sampling Pulse 1N4148 1kΩ + Line Sync. VR1 8 BC547 10µF with video VR1 - l8 Line Sync. without video 10/15 TDA8215B Figure 12. Typical Application 4.7kΩ VCC +24V VCC1 470µF 100nF 100µF 100nF VCC1 IN4002 820kΩ 10kΩ IN4148 27kΩ Video Identification BC547 10µF 180nF 220pF 47µF IN4148 100nF 2.2kΩ 2 Video Input 1.5kΩ 120pF Line Flyback 220nF 1 8 3 9 4 14 10 560kΩ 20 Frame Yoke 30 mH, 15Ω lpp = 840mA TDA 8215B 15kΩ 22nF 13 68pF 22nF 7 220kΩ 18 12 100kΩ 270Ω 11 5 6 15 16 19 17 680pF 100kΩ 220kΩ 1000µF 220pF 22k 180pF 4.7k 1µF 2.2nF 12nF 22kΩ 22kΩ VCC1 100Ω Horizontal Frequency SSC 1Ω 100Ω 2.2kΩ VCC1 10µF Line Yoke 193mH, 22Ω, ipp = 4A Line Darlington SGSD00055 11/15 TDA8215B PART NUMBERING Table 17. Order Codes 12/15 Part Number Package Temperature Range TDA8215B PDIP20 -0 to 70 °C TDA8215B PACKAGE MECHANICAL Table 18. PLASTIC POWERDIP Mechanical Data millimeters Symbol Min a1 0.51 B 0.85 inches Typ Max Min Typ 1.4 b 0.033 0.055 0.5 b1 Max 0.020 0.020 0.38 0.5 D 0.015 0.020 24.8 0.976 E 8.8 0.346 e 2.54 0.100 e3 22.86 0.900 F 7.1 0.280 i 5.1 0.201 L 3.3 0.130 Z 1.27 0.050 Figure 13. PLASTIC POWERDIP Package Dimensions e4 R1 N N N K1 I K K2 A a1 b B b1 C L R1 e Z F e3 E D Tie Bar Center 20 11 1 10 R2 Note: Drawing is not to scale. 13/15 TDA8215B REVISION HISTORY Table 19. Revision History Date Revision September-1993 1 First Issue 17-May-2004 2 Stylesheet update. No content change. 14/15 Description of Changes TDA8215B Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners © 2004 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States www.st.com 15/15