TS4984EIJT

TS4984FC 1.2W Stereo Audio Power Amplifier with Active Low Standby Mode ■ ■ Operating from VCC = 2.2V to 5.5V 1.2W output power per channel @ VCC = 5V, THD+N = 1%, RL = 8Ω 10nA standby current 62dB PSRR @ 217Hz with grounded inputs High SNR: 106dB(A) typ. Near-zero pop & click Available in a 15-bump flip-chip (lead-free) TS4984 - flip-chip 15 bumps ■ ■ ■ ■ ■ Pin connections (top view) VCC IN2+ Description The TS4984 has been designed for top-class stereo audio applications. Thanks to its compact and power dissipation efficient flip-chip package, it suits various applications. With a output BTL configuration, this audio power amplifier is capable of delivering 1.2W per channel of continuous RMS output power into an 8Ω load @ 5V. An externally-controlled standby mode reduces the supply current to less than 10nA per channel. The device also features an internal thermal shutdown protection. The gain of each channel can be configured by external gain setting resistors. VCC BYPASS IN2- VOUT1+ VOUT1STDBY VOUT2+ VOUT2- IN1+ GND IN1- BYPASS GND Applications ■ ■ ■ ■ Cellular mobile phones Notebook & PDA computers LCD monitors & TVs Portable audio devices Order Codes Part Number TS4984EIJT TS4984EIKJT -40, +85°C Temperature Range Package Lead free flip-chip Lead free flip-chip + back coating Packing Tape & Reel Marking A84 November 2005 Rev 2 1/30 www.st.com 30 Typical Application Schematic TS4984FC 1 Typical Application Schematic Figure 1 show a typical application schematic for the TS4984FC. Figure 1. Application information Cfeed1 Rfeed1 22k VCC Cs A5 B6 + U1 VCC A1 INPUT1 Cin1 IN1- 100nF Rin1 22k VCC VOUT1B2 A3 IN1+ + OUTPUT1 + AV = -1 C5 + VOUT1+ B4 BYPASS + Cb StandBy Control C3 STDBY Bias W ire optional Internal connection D6 IN2+ + VOUT2E3 E5 IN2- OUTPUT2 INPUT2 Cin2 Rin2 22k C1 + AV = -1 BYPASS + VOUT2+ D4 100nF GND 22k Rfeed2 Cfeed2 Table 1. External component descriptions Functional Description Inverting input resistors which sets the closed loop gain in conjunction with Rfeed . These resistors also form a high pass filter with Cin = 1/2 x Pi x R in x Cin)) Input coupling capacitors which blocks the DC voltage at the amplifier input terminal Feedback resistors which sets the closed loop gain in conjunction with Rin Supply Bypass capacitor which provides power supply filtering Bypass pin capacitor which provides half supply filtering Closed loop gain in BTL configuration = 2 x (Rfeed / Rin) on each channel Components Rin L,R Cin L,R R feed L,R Cs Cb AV L, R 2/30 D2 E1 GND TS4984FC Absolute Maximum Ratings 2 Absolute Maximum Ratings Table 2. Symbol VCC Vi Toper Tstg Tj Rthja Pdiss ESD ESD Supply voltage (1) Input Voltage (2) Operating Free Air Temperature Range Storage Temperature Maximum Junction Temperature Thermal Resistance Junction to Ambient for Flip-chip15 Power Dissipation Human Body Model (3) Machine Model Latch-up Immunity 1. All voltages values are measured with respect to the ground pin 2. The magnitude of input signal must never exceed VCC + 0.3V / GND - 0.3V 3. All voltage values are measured from each pin with respect to supplies Key parameters and their absolute maximum ratings Parameter Value 6 GND to VCC -40 to + 85 -65 to +150 150 180 Internally Limited 2 200 200mA kV V Unit V V °C °C °C °C/W Table 3. Symbol VCC VICM VSTBY RL ROUTGND TSD Rthja 1. Operating conditions Parameter Supply Voltage Common Mode Input Voltage Range Standby Voltage Input: Device ON Device OFF Load Resistor Resistor Output to GND (VSTBY = GND) Thermal Shutdown Temperature Thermal Resistance Junction to Ambient Flip-chip15(1) Value 2.2 to 5.5 1.2V to VCC 1.35 ≤ V STBY ≤ VCC GND ≤ VSTBY ≤ 0.4 ≥4 ≥1 150 110 Unit V V V Ω MΩ °C °C/W When mounted on a 4-layer PCB 3/30 Electrical Characteristics TS4984FC 3 Table 4. Symbol ICC ISTBY VOO Pout THD + N Electrical Characteristics VCC = +5V, GND = 0V, Tamb = 25°C (unless otherwise specified) Parameter Supply Current Standby Current (1) Output Offset Voltage Output Power Total Harmonic Distortion + Noise Conditions No input signal, no load No input signal, V STBY = GND, RL = 8 Ω No input signal, R L = 8Ω THD = 1% Max, F = 1kHz, R L = 8Ω Pout = 1Wrms, AV = 2 20Hz ≤ F ≤ 20kHz, R L = 8Ω R L = 8Ω, AV = 2, Vripple = 200mVpp, Input Grounded, F = 217Hz R L = 8Ω, AV = 2, Vripple = 200mVpp, Input Grounded, F = 1kHz R L = 8Ω, F = 1kHz 55 55 0.9 Min. Typ. 7.4 10 1 1.2 0.2 Max. 12 1000 10 Unit mA nA mV W % PSRR Power Supply Rejection Ratio (2) 62 dB 64 107 dB 82 90 10 1.3 0.4 130 ms µs V V Degrees dB MHz Crosstalk Channel Separation, twu tstby VSTBYH VSTBYL ΦM GM GBP Wake-Up Time Standby Time Standby Voltage Level High Standby Voltage Level Low Phase Margin at Unity Gain Gain Margin Gain Bandwidth Product R L = 8Ω, F = 20Hz to 20kHz C b = 1µF C b = 1µF R L = 8Ω, C L = 500pF R L = 8Ω, C L = 500pF R L = 8Ω 65 15 1.5 1. Standby mode is activated when VSTBY is tied to Gnd. 2. All PSRR data limits are guaranteed by production sampling tests. Dynamic measurements - 20*log(rms(Vout)/rms(Vripple)). Vripple is the sinusoidal signal superimposed upon VCC. 4/30 TS4984FC Table 5. Symbol ICC ISTBY VOO Pout THD + N Electrical Characteristics VCC = +3.3V, GND = 0V, Tamb = 25°C (unless otherwise specified) Parameter Min. No input signal, no load No input signal, V STBY = GND, RL = 8Ω No input signal, R L = 8Ω THD = 1% Max, F = 1kHz, R L = 8Ω Pout = 400mWrms, AV = 2 20Hz ≤ F ≤ 20kHz, RL = 8Ω RL = 8Ω, AV = 2, Vripple = 200mVpp, Input Grounded, F = 217Hz RL = 8Ω, AV = 2, Vripple = 200mVpp, Input Grounded, F = 1kHz RL = 8Ω, F = 1kHz 55 55 375 Typ. 6.6 10 1 500 0.1 Max. 12 1000 10 Unit mA nA mV mW % Supply Current Standby Current (1) Output Offset Voltage Output Power Total Harmonic Distortion + Noise PSRR Power Supply Rejection Ratio (2) 61 dB 63 107 dB 82 110 10 1.2 0.4 140 ms µs V V Degrees dB MHz Crosstalk Channel Separation, twu tstby VSTBYH VSTBYL ΦM GM GBP Wake-Up Time Standby Time Standby Voltage Level High Standby Voltage Level Low Phase Margin at Unity Gain Gain Margin Gain Bandwidth Product RL = 8Ω, F = 20Hz to 20kHz Cb = 1µF Cb = 1µF RL = 8Ω, CL = 500pF RL = 8 Ω, CL = 500pF RL = 8Ω 65 15 1.5 1. Standby mode is activated when VSTBY is tied to Gnd. 2. All PSRR data limits are guaranteed by production sampling tests. Dynamic measurements - 20*log(rms(Vout)/rms(Vripple )). Vripple is the sinusoidal signal superimposed upon VCC. 5/30 Electrical Characteristics Table 6. Symbol ICC ISTBY VOO Pout THD + N TS4984FC VCC = +2.6V, GND = 0V, Tamb = 25°C (unless otherwise specified) Parameter Supply Current Standby Current (1) Output Offset Voltage Output Power Total Harmonic Distortion + Noise No input signal, no load No input signal, VSTBY = GND, RL = 8Ω No input signal, RL = 8Ω THD = 1% Max, F = 1kHz, RL = 8 Ω Pout = 200mWrms, AV = 2 20Hz ≤ F ≤ 20kHz, RL = 8Ω RL = 8Ω, AV = 2, Vripple = 200mVpp, Input Grounded, F = 217Hz RL = 8Ω, AV = 2, Vripple = 200mVpp, Input Grounded, F = 1kHz RL = 8Ω, F = 1kHz 55 55 220 Min. Typ. 6.2 10 1 300 0.1 Max. 12 1000 10 Unit mA nA mV mW % PSRR Power Supply Rejection Ratio (2) 60 dB 62 107 dB 82 125 10 1.2 0.4 150 ms µs V V Degrees dB MHz Crosstalk Channel Separation, twu tstby VSTBYH VSTBYL ΦM GM GBP Wake-Up Time Standby Time Standby Voltage Level High Standby Voltage Level Low Phase Margin at Unity Gain Gain Margin Gain Bandwidth Product RL = 8Ω, F = 20Hz to 20kHz Cb = 1µF Cb = 1µF RL = 8Ω, CL = 500pF RL = 8Ω, CL = 500pF RL = 8 Ω 65 15 1.5 1. Standby mode is activated when VSTBY is tied to Gnd. 2. All PSRR data limits are guaranteed by production sampling tests. Dynamic measurements - 20*log(rms(Vout)/rms(Vripple )). Vripple is the sinusoidal signal superimposed upon VCC. 6/30 TS4984FC Table 7. Index of graphics Description Open Loop Frequency Response Power Supply Rejection Ratio (PSRR) vs. Frequency Power Supply Rejection Ratio (PSRR) vs. DC Output Voltage Power Supply Rejection Ratio (PSRR) at F=217Hz vs. Bypass Capacitor Output Power vs. Power Supply Voltage Output Power vs. Load Resistor Power Dissipation vs. Output Power Clipping Voltage vs. Power Supply Voltage and Load Resistor Current Consumption vs. Power Supply Voltage Current Consumption vs. Standby Voltage Power Derating Curves THD+N vs. Output Power THD+N vs. Frequency Crosstalk vs. Frequency SIgnal to Noise Ratio vs. Power Supply with Unweighted Filter (20Hz to 20kHz) SIgnal to Noise Ratio vs. Power Supply with A-weighted Filter Output Noise Voltage, Device ON Output Noise Voltage, Device in Standby Electrical Characteristics Figure Page Figure 2 to 7 Figure 8 to 13 Figure 14 to 22 Figure 23 Figure 24 to 27 Figure 28 to 30 Figure 31 to 33 Figure 34, Figure 35 Figure 36 Figure 37 to 39 Figure 40 Figure 41 to 49 Figure 50 to 52 Figure 53 to 55 Figure 56, Figure 57 Figure 58, Figure 59 Figure 60 Figure 61 page 8 page 9 page 10 to page 11 page 11 page 11 to page 12 page 12 page 12 to page 13 page 13 page 13 page 13 to page 14 page 14 page 14 to page 15 page 16 page 16 page 17 page 17 page 17 page 17 7/30 Electrical Characteristics Figure 2. Open loop frequency response Figure 3. TS4984FC Open loop frequency response 60 40 20 Gain (dB) 0 Gain -40 Phase (°) 100 80 60 Gain (dB) 0 Gain -40 Phase (°) Phase (°) Phase (°) Phase -80 40 Phase 20 0 -80 0 -120 -20 -40 -60 0.1 Vcc = 5V RL = 8Ω Tamb = 25°C 1 10 100 1000 -160 -120 -20 -200 10000 -40 0.1 Vcc = 5V CL = 560pF Tamb = 25°C 1 10 100 1000 -160 -200 10000 Frequency (kHz) Frequency (kHz) Figure 4. Open loop frequency response Figure 5. Open loop frequency response 60 Gain 40 20 Gain (dB) 0 100 80 Gain 0 -40 60 Gain (dB) -40 Phase -80 Phase (°) 40 Phase 20 0 -80 0 -120 -20 -40 -60 0.1 Vcc = 3.3V RL = 8Ω Tamb = 25°C 1 10 100 1000 -160 -120 -20 -200 10000 -40 0.1 Vcc = 3.3V CL = 560pF Tamb = 25°C 1 10 100 1000 -160 -200 10000 Frequency (kHz) Frequency (kHz) Figure 6. Open loop frequency response Figure 7. Open loop frequency response 60 Gain 40 20 Gain (dB) 0 100 80 60 Gain 0 -40 Phase Phase (°) -40 Gain (dB) -80 40 Phase 20 0 -80 0 -120 -20 -40 -60 0.1 Vcc = 2.6V RL = 8Ω Tamb = 25°C 1 10 100 1000 -160 -120 -20 -200 10000 -40 0.1 Vcc = 2.6V CL = 560pF Tamb = 25°C 1 10 100 1000 -160 -200 10000 Frequency (kHz) Frequency (kHz) 8/30 TS4984FC Figure 8. Power supply rejection ratio (PSRR) Figure 9. vs. frequency Electrical Characteristics Power supply rejection ratio (PSRR) vs. frequency 0 -10 -20 PSRR (dB) 0 Vripple = 200mVpp Rfeed = 22kΩ Input = Floating Cb = 0.1µF RL >= 4Ω Tamb = 25°C Vcc = 2.2, 2.6, 3.3, 5V -10 -20 PSRR (dB) -30 -40 -50 -60 -70 -80 -30 -40 -50 -60 -70 Vripple = 200mVpp Av = 2 Input = Grounded Cb = Cin = 1µF RL >= 4Ω Tamb = 25°C Vcc : 2.2V 2.6V 3.3V 5V 100 1000 10000 Frequency (Hz) 100000 100 1000 10000 Frequency (Hz) 100000 Figure 10. Power supply rejection ratio (PSRR) Figure 11. Power supply rejection ratio (PSRR) vs. frequency vs. frequency 0 -10 -20 PSRR (dB) 0 Vripple = 200mVpp Rfeed = 22kΩ Input = Floating Cb = 1µF RL >= 4Ω Tamb = 25°C Vcc = 2.2, 2.6, 3.3, 5V -10 -20 -30 -40 -50 Vripple = 200mVpp Av = 5 Input = Grounded Cb = Cin = 1µF RL >= 4Ω Tamb = 25°C Vcc : 2.2V 2.6V 3.3V 5V -30 -40 -50 -60 -70 -80 PSRR (dB) -60 100 1000 10000 Frequency (Hz) 100000 100 1000 10000 Frequency (Hz) 100000 Figure 12. Power supply rejection ratio (PSRR) Figure 13. Power supply rejection ratio (PSRR) vs. frequency vs. frequency 0 -10 -20 -30 -40 -50 Vripple = 200mVpp Av = 2 Input = Grounded Cb = 0.1µF, Cin = 1µF RL >= 4Ω Tamb = 25°C 0 Vripple = 200mVpp Av = 10 Input = Grounded Cb = Cin = 1µF RL >= 4Ω Tamb = 25°C Vcc : 2.2V 2.6V 3.3V 5V -10 PSRR (dB) PSRR (dB) -20 -30 Vcc = 5, 3.3, 2.5 & 2.2V -40 -50 -60 100 1000 10000 Frequency (Hz) 100000 100 1000 10000 Frequency (Hz) 100000 9/30 Electrical Characteristics TS4984FC Figure 14. Power supply rejection ratio (PSRR) Figure 15. Power supply rejection ratio (PSRR) vs. DC output voltage vs. DC output voltage 0 -10 -20 PSRR (dB) 0 Vcc = 5V Vripple = 200mVpp RL = 8Ω Cb = 1µF AV = 2 Tamb = 25°C -10 -20 -30 -40 -50 -60 -5 Vcc = 5V Vripple = 200mVpp RL = 8Ω Cb = 1µF AV = 5 Tamb = 25°C -30 -40 -50 -60 -70 -5 -4 -3 -2 -1 0 1 2 3 Differential DC Output Voltage (V) 4 5 PSRR (dB) -4 -3 -2 -1 0 1 2 3 Differential DC Output Voltage (V) 4 5 Figure 16. Power supply rejection ratio (PSRR) Figure 17. Power supply rejection ratio (PSRR) vs. DC output voltage vs. DC output voltage 0 Vcc = 5V Vripple = 200mVpp RL = 8Ω Cb = 1µF AV = 10 Tamb = 25°C 0 -10 -20 Vcc = 3.3V Vripple = 200mVpp RL = 8Ω Cb = 1µF AV = 2 Tamb = 25°C -10 PSRR (dB) -20 PSRR (dB) 4 5 -30 -40 -50 -30 -40 -60 -50 -5 -4 -3 -2 -1 0 1 2 3 Differential DC Output Voltage (V) -70 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 Differential DC Output Voltage (V) Figure 18. Power supply rejection ratio (PSRR) Figure 19. Power supply rejection ratio (PSRR) vs. DC output voltage vs. DC output voltage 0 -10 -20 -30 -40 -50 -60 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 Differential DC Output Voltage (V) Vcc = 3.3V Vripple = 200mVpp RL = 8Ω Cb = 1µF AV = 5 Tamb = 25°C 0 Vcc = 3.3V Vripple = 200mVpp RL = 8Ω Cb = 1µF AV = 10 Tamb = 25°C -10 PSRR (dB) PSRR (dB) -20 -30 -40 -50 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 Differential DC Output Voltage (V) 10/30 TS4984FC Electrical Characteristics Figure 20. Power supply rejection ratio (PSRR) Figure 21. Power supply rejection ratio (PSRR) vs. DC output voltage vs. DC output voltage 0 -10 -20 Vcc = 2.6V Vripple = 200mVpp RL = 8Ω Cb = 1µF AV = 2 Tamb = 25°C 0 -10 -20 -30 -40 -50 -60 -2.5 -2.0 -1.5 -1.0 -0.5 Vcc = 2.6V Vripple = 200mVpp RL = 8Ω Cb = 1µF AV = 5 Tamb = 25°C PSRR (dB) -30 -40 -50 -60 -70 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 PSRR (dB) 0.0 0.5 1.0 1.5 2.0 2.5 Differential DC Output Voltage (V) Differential DC Output Voltage (V) Figure 22. Power supply rejection ratio (PSRR) Figure 23. Power supply rejection ratio (PSRR) vs. DC output voltage at F = 217Hz vs. bypass capacitor 0 Vcc = 2.6V Vripple = 200mVpp RL = 8Ω Cb = 1µF AV = 10 Tamb = 25°C -30 PSRR at 217Hz (dB) -10 -40 Av=10 Vcc: 2.6V 3.3V 5V PSRR (dB) -20 -50 Av=2 Vcc: 2.6V 3.3V 5V -30 -60 -40 -70 Av=5 Vcc: 2.6V 3.3V 5V 1 Bypass Capacitor Cb ( F) Tamb=25°C -50 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 -80 0.1 Differential DC Output Voltage (V) Figure 24. Output power vs. power supply voltage Figure 25. Output power vs. power supply voltage 11/30 Electrical Characteristics Figure 26. Output power vs. power supply voltage TS4984FC Figure 27. Output power vs. power supply voltage Figure 28. Output power vs. load resistor Figure 29. Output power vs. load resistor Figure 30. Output power vs. load resistor Figure 31. Power dissipation vs. output power per channel 12/30 TS4984FC Electrical Characteristics Figure 32. Power dissipation vs. output power Figure 33. Power dissipation vs. output power per channel per channel Figure 34. Clipping voltage vs. power supply voltage and load resistor Figure 35. Clipping voltage vs. power supply voltage and load resistor Figure 36. Current consumption vs. power supply voltage Figure 37. Current consumption vs. standby voltage at V CC = 5V No Loads Tamb=25°C Vcc = 5V No Loads Tamb=25°C 13/30 Electrical Characteristics Figure 38. Current consumption vs. standby voltage at VCC = 3.3V TS4984FC Figure 39. Current consumption vs. standby voltage at V CC = 2.6V Vcc = 3.3V No Loads Tamb=25°C Vcc = 2.6V No Loads Tamb=25°C Figure 40. Power derating curves Figure 41. THD + N vs. output power Figure 42. THD + N vs. output power Figure 43. THD + N vs. output power 14/30 TS4984FC Figure 44. THD + N vs. output power Electrical Characteristics Figure 45. THD + N vs. output power Figure 46. THD + N vs. output power Figure 47. THD + N vs. output power Figure 48. THD + N vs. output power Figure 49. THD + N vs. output power 15/30 Electrical Characteristics Figure 50. THD + N vs. frequency Figure 51. THD + N vs. frequency TS4984FC Figure 52. THD + N vs. frequency Figure 53. Crosstalk vs. frequency 0 Vcc = 2.6V − 20 Pout = 200mW RL = 8 Ω − 40 Av = 2 BW < 125kHz − 60 Tamb = 25°C − 80 − 100 − 120 − 140 OUT2 to OUT1 Cr osst k ( ) al dB OUT1 to OUT2 100 1000 Fr equency ( z) H 10000 Figure 54. Crosstalk vs. frequency Figure 55. Crosstalk vs. frequency 0 Vcc = 3.3V − 20 Pout = 400mW RL = 8 Ω − 40 Av = 2 BW < 125kHz − 60 Tamb = 25°C − 80 − 100 − 120 − 140 OUT2 to OUT1 0 Vcc = 5V − 20 Pout = 1W RL = 8 Ω − 40 Av = 2 BW < 125kHz − 60 Tamb = 25°C − 80 − 100 − 120 − 140 OUT2 to OUT1 Cr osst k ( ) al dB OUT1 to OUT2 Cr osst k ( ) al dB OUT1 to OUT2 100 1000 Fr equency ( z) H 10000 100 1000 Fr equency ( z) H 10000 16/30 TS4984FC Electrical Characteristics Figure 56. Signal to noise ratio vs. power Figure 57. Signal to noise ratio vs. power supply with unweighted filter (20Hz supply with unweighted filter (20Hz to 20kHz) to 20kHz) Figure 58. Signal to noise ratio vs. power supply with A weighted filter Figure 59. Signal to noise ratio vs. power supply with A weighted filter Figure 60. Output noise voltage, device ON Figure 61. Output noise voltage, device in standby 17/30 Application Information TS4984FC 4 Application Information The TS4984 integrates two monolithic power amplifiers with a BTL (Bridge Tied Load) output type (explained in more detail in Section 4.1). For this discussion, only the left-channel amplifier will be referred to. Referring to the schematic in Figure 62, we assign the following variables and values: Vin = Vin1Vout1 = VOUT1+ Vout2 = VOUT1Rin = Rin1 Rfeed = Rfeed1 Cfeed = Cfeed1 Figure 62. Typical application schematic - left channel Cfeed = Cfeed1 Rfeed = Rfeed1 VCC + Cs 1u TS4984 VCC - Cin = Cin1 IN1 GND 2 1 Vin- = VIN1Rin = Rin1 Vin+ = VIN1+ VCC Vout1 = VOUT1+ + RL STDBY BYPASS + Bias AV = -1 + Vout2 = VOUT1- Cb 1u 4.1 BTL configuration principle BTL (Bridge Tied Load) means that each end of the load is connected to two single-ended output amplifiers. Thus, we have: Single-ended output 1 = Vout1 = Vout (V), Single-ended output 2 = Vout2 = -Vout (V), Vout1 - Vout2 = 2Vout (V) 18/30 TS4984FC The output power is: ( 2V outR MS ) P out = --------------------------------RL 2 Application Information For the same power supply voltage, the output power in a BTL configuration is four times higher than the output power in a single-ended configuration. 4.2 Gain in typical application schematic The typical application schematic (Figure 62) is shown on page 18. In the flat region (no Cin effect), the output voltage of the first stage is: R feed V out1 = ( – V in ) -------------R in (V) For the second stage: Vout2 = -Vout1 (V) The differential output voltage is: R feed V out 2 – V out1 = 2V in ------------R in (V) The differential gain, referred to as Gv for greater convenience, is: R f eed V out2 – V o ut 1 G v = ---------------------------------- = 2 ------------R in V in Vout2 is in phase with Vin and Vout1 is phased 180° with Vin. This means that the positive terminal of the loudspeaker should be connected to Vout2 and the negative to Vout1. 4.3 Low and high frequency response In the low frequency region, Cin starts to have an effect. Cin forms with Rin a high-pass filter with a -3dB cut-off frequency: 1 F CL = -----------------------2 π R in C in (Hz) In the high frequency region, you can limit the bandwidth by adding a capacitor (Cfeed) in parallel with Rfeed. It forms a low-pass filter with a -3dB cut-off frequency. FCH is in Hz. 1 F C H = -----------------------------------2 π R f eed C f eed (Hz) 19/30 Application Information The following graph (Figure 63) shows an example of Cin and Cfeed influence. Figure 63. Frequency response gain versus Cin & Cfeed TS4984FC 10 5 0 Gain (dB) Cfeed = 330pF Cfeed = 680pF Cin = 470nF Cin = 22nF Cin = 82nF Rin = Rfeed = 22kΩ Tamb = 25°C 10000 Cfeed = 2.2nF -5 -10 -15 -20 -25 10 100 1000 Frequency (Hz) 4.4 Power dissipation and efficiency Hypotheses: ● ● Voltage and current in the load are sinusoidal (Vout and Iout). Supply voltage is a pure DC source (VCC). V out = V PEAK sin ω t Regarding the load we have: (V) and V out I out = -----------RL (A) and V PEAK 2 P out = ---------------------2R L V PEAK = 2 ---------------πR L (W) Therefore, the average current delivered by the supply voltage is: I CC AVG (A) The power delivered by the supply voltage is: P supply = V CC ⋅ I C C AVG (W) Then, the power dissipated by each amplifier is: P diss = P supply – P out (W) (W) 2 2V CC P diss = ---------------------- ⋅ P out – P out π RL 20/30 TS4984FC and the maximum value is obtained when: ∂ P diss ------------------ = 0 ∂ P out Application Information and its value is: 2 2V cc P dissmax = ------------2R πL (W) Note: This maximum value is only depending on power supply voltage and load values. The efficiency, η, is the ratio between the output power and the power supply: P out π V PEAK η = ------------------ = ---------------------P supply 4V CC The maximum theoretical value is reached when VPEAK = VCC, so that: π ---- = 78.5% 4 The TS4984 has two independent power amplifiers, and each amplifier produces heat due to its power dissipation. Therefore, the maximum die temperature is the sum of the each amplifier’s maximum power dissipation. It is calculated as follows: Pdiss1 = Power dissipation due to the 1st channel power amplifier. Pdiss2 = Power dissipation due to the 2nd channel power amplifier. Total Pdiss = Pdiss1 + Pdiss2 (W) In most cases, Pdiss1 = Pdiss2, giving: Total P diss = P diss1 = P diss2 (W) or, stated differently: 4 2V CC Total P diss = ---------------------- P out – 2P out π RL (W) 4.5 Decoupling the circuit Two capacitors are needed to correctly bypass the TS4984. A power supply bypass capacitor CS and a bias voltage bypass capacitor C b. CS has particular influence on the THD+N in the high frequency region (above 7kHz) and an indirect influence on power supply disturbances. With a value for CS of 1µF, you can expect similar THD+N performances to those shown in the datasheet. For example: ● ● In the high frequency region, if CS is lower than 1µF, it increases THD+N and disturbances on the power supply rail are less filtered. On the other hand, if CS is higher than 1µF, those disturbances on the power supply rail are more filtered. Cb has an influence on THD+N at lower frequencies, but its function is critical to the final result of PSRR (with input grounded and in the lower frequency region), in the following manner: ● If Cb is lower than 1µF, THD+N increases at lower frequencies and PSRR worsens. 21/30 Application Information ● TS4984FC If Cb is higher than 1µF, the benefit on THD+N at lower frequencies is small, but the benefit to PSRR is substantial. Note: The TS4984FC has two BYPASS pins. Cb can be connected equally to pin C5 or to pin C1. These pins are internally connected. Connecting pin C5 and pin C1 together by an external wire is optional. Cin has a non-negligible effect on PSRR at lower frequencies. The lower the value of Cin, the higher the PSRR. 4.6 Wake-up time, twu When the standby is released to put the device ON, the bypass capacitor Cb will not be charged immediately. As Cb is directly linked to the bias of the amplifier, the bias will not work properly until the Cb voltage is correct. The time required to reach this voltage is called the wake-up time or twu and specified in the tables in Chapter 3: Electrical Characteristics with C b = 1µF. If Cb has a value other than 1µF, please refer to the graph in Figure 64 to establish the wake-up time value. Due to process tolerances, the maximum value of wake-up time could be establish by the graph in Figure 65. Figure 64. Typical wake-up time vs. Cb 600 500 Startup Time (ms) Figure 65. Maximum wake-up time vs. C b Tamb=25°C Vcc=3.3V 600 Tamb=25°C Vcc=3.3V Max. Startup Time (ms) 500 Vcc=2.6V 400 300 200 Vcc=5V 100 0 0.1 400 300 200 Vcc=2.6V Vcc=5V 100 0 0.1 1 2 3 Bypass Capacitor Cb ( F) 4 4.7 1 2 3 Bypass Capacitor Cb ( F) 4 4.7 Note: Bypass capacitor Cb as also a tolerance of typically +/-20%. To calculate the wake-up time with this tolerance, refer to the previous graph (considering for example for Cb = 1µF in the range of 0.8µF ≤ 1µF ≤ 1.2µF). 4.7 Shutdown time When the standby command is set, the time required to put the two output stages in high impedance and the internal circuitry in shutdown mode is a few microseconds. Note: In shutdown mode, Bypass pin and Vin- pin are short-circuited to ground by internal switches. This allows for the quick discharge of the Cb and Cin capacitors. 22/30 TS4984FC Application Information 4.8 Pop performance Pop performance is intimately linked with the size of the input capacitor C in and the bias voltage bypass capacitor Cb. The size of Cin is dependent on the lower cut-off frequency and PSRR values requested. The size of Cb is dependent on THD+N and PSRR values requested at lower frequencies. Moreover, Cb determines the speed with which the amplifier turns ON. In order to reach near zero pop and click, the equivalent input constant time, τin = (Rin + 2kΩ) x C in (s) with Rin ≥ 5kΩ must not reach the τin maximum value as indicated in the graph below in Figure 66. Figure 66. τin max. versus bypass capacitor 160 Tamb=25°C Vcc=3.3V 120 Vcc=2.6V in max. (ms) 80 40 Vcc=5V 0 1 2 3 Bypass Capacitor Cb ( F) 4 By following the previous rules, the TS4984 can reach near zero pop and click even with high gains such as 20dB. Example calculation: With Rin = 22kΩ and a 20Hz, -3dB lower cut-off frequency, Cin = 361nF. So, Cin =390nF with standard value which gives a lower cut-off frequency equal to 18.5Hz. In this case, (Rin + 2kΩ) x Cin = 9.36ms. When referring to the previous graph, if Cb =1µF and VCC = 5V, we read 20 ms max. This value is twice as high as our current value, thus we can state that pop and click will be reduced to its lowest value. Minimizing both C in and the gain benefits both the pop phenomena, and the cost and size of the application. 23/30 Application Information TS4984FC 4.9 Application example: differential-input BTL power stereo amplifier The schematic in Figure 67 shows how to design the TS4984 to work in differential-input mode. For this discussion, only the left-channel amplifier will be referred to. Let: R1R = R2L = R1, R 2R = R2L = R2 CinR = C inL = Cin The gain of the amplifier is: R2 G Vdif = 2 ------R1 In order to reach the optimal performance of the differential function, R1 and R2 should be matched at 1% maximum. Figure 67. Differential input amplifier configuration R2L Neg. Input LEFT CinL VCC IN-L Pos. Input LEFT VO-L CinL R1L IN+L + R2L LEFT Speaker StandBy Control VCC1 VCC2 TS4984 StandBy BypassL Bias AV = -1 + VO+L 8 Ohms R2R Pos. Input RIGHT CinR R1R IN+R + VO-R IN-R Neg. Input RIGHT - CinR R1R RIGHT Speaker AV = -1 BypassR + VO+R 8 Ohms Cb + GND1 R2R The value of the input capacitor Cin can be calculated with the following formula, using the -3dB lower frequency required (where FL is the lower frequency required): 1 C in ≈ -------------------2 π R 1 FL (F) 24/30 GND2 + R1L Cs TS4984FC Note: This formula is true only if: 1 F CB = --------------------------------------2 π ( R1 + R 2 ) C b (Hz) Application Information is 5 times lower than FL. The following bill of materials is provided as an example of a differential amplifier with a gain of 2 and a -3dB lower cut-off frequency of about 80Hz. Table 8. Example of a bill of materials Designator R1L = R1R R2L = R2R CinR = C inL Cb = Cs U1 Part Type 20k Ω / 1% 20k Ω / 1% 100nF 1µF TS4984 4.10 Demoboard A demoboard for the TS4984 in flip-chip package is available. For more information about this demoboard, please refer to Application Note AN2153, which can be found on www.st.com. Figure 68 shows the component locations, and Figure 69 and Figure 70 show top layer and bottom layers of the demoboard, respectively. Figure 71 shows a schematic of the demoboard Figure 68. Component locations 25/30 Application Information Figure 69. Top layer TS4984FC Figure 70. Bottom layer 26/30 TS4984FC Figure 71. Demoboard schematic C2 1 2 Application Information 1 R2 22K 2 Cn9 Vcc GND VCC 1 1 C7 1uF 2 2 C8 100nF 1 2 2 1 U1 TS4984_FC_ADAPTER VCC1 2 1 R1 22K 1 R3 2 5 2 6 Cn1 neg. GND Input L Cn3 pos. GND C1 1 2 1 2 1 100nF C3 1 2 IN-L VO-L 4 IN+L + Jumper J1 Cn7 VCC 1 2 3 StandBy VCC2 7 STDBY Bias AV = -1 + VO+L 3 2 1 Cn2 neg. pos. OUTL Cn4 neg. GND Input R pos. GND Cn6 C4 1 2 1 2 1 2 100nF C6 1 2 1 R4 22K 1 R6 2 13 IN-R VO-R 11 2 1 Cn5 neg. pos. OUTR 2 14 IN+R + 2 1 R7 1 2 R8 8 15 AV = -1 Bypass Bypass + VO+R 12 1 C9 1uF 2 GND1 10 1 R5 22K C5 1 2 2 9 GND2 27/30 Package Mechanical Data TS4984FC 5 Package Mechanical Data Figure 72. Pinout (top view) 6 5 4 3 2 1 IN1VOUT1VCC VCC IN2+ BYPASS IN2- VOUT1+ STDBY VOUT2+ VOUT2- IN1+ GND BYPASS GND A B C D E Note: Balls are underneath Figure 73. Marking (top view) E Marking shows: ■ ■ ST Logo Product & assembly code: XXX - A84 from Tours - 848 from Singapore - 84K from Shenzhen 3-digit datecode: YWW “E” lead-free symbol The dot marks position of pin A1 XXX YWW ■ ■ ■ 28/30 TS4984FC Figure 74. Package mechanical data for 15-bump flip-chip 2.40 mm ■ 0.25m m Package Mechanical Data Die size: 2.40 x 1.90 mm ±30µm Die height (including bumps): 600µm Back Coating height (optional): 60µm±10µm Bump Diameter: 315µm ±50µm Bump Diameter Before Reflow: 300µm ±10µm Bump Height: 250µm ±40µm Die Height: 350µm ±20µm Pitch: 500µm ±50µm Coplanarity: 60µm max. ■ 0.5mm ■ ■ ■ 1.90 mm ∅ 0.3mm 0.86mm ■ 60 µm Back coating * ■ ■ ■ 600 µm * Optional Figure 75. Tape & Reel specification (top view) 4 1.5 1 A A Die size Y + 70µm 1 8 Die size X + 70µm 4 All dimensions are in mm User direction of feed 29/30 Revision History TS4984FC 6 Revision History Date 20 May 2005 Revision 1 Initial release. Typical application schematic corrected see Figure 1: Application information on page 2. Change to layout of tables in Chapter 3: Electrical Characteristics on page 4 . Minor grammatical and formatting changes throughout. Changes Nov. 2005 2 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. 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