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TS982IDW

TS982IDW

  • 厂商:

    STMICROELECTRONICS(意法半导体)

  • 封装:

    SOIC8_150MIL_EP

  • 描述:

    IC OPAMP GP 2.2MHZ RRO 8SO

  • 数据手册
  • 价格&库存
TS982IDW 数据手册
TS982 Wide bandwidth, dual bipolar operational amplifier Datasheet - production data Description The TS982 device is a dual operational amplifier able to drive 200 mA down to voltages as low as 2.7 V. The SO-8 exposed-pad package allows high current output at high ambient temperatures making it a reliable solution for automotive and industrial applications. DW SO-8 exposed-pad (plastic micropackage) The TS982 device is stable with a unity gain. Pin connections (top view) Output1 1 8 VCC + Inverting input1 2 - tin input1 3 Non-inverting + VCC - 4 7 Output2 - 6 Inverting input2 + 5 Non-inverting input2 Cross section view showing e xposed-pad c - CC) copper area on the PCB This pad can be connected to a (-V Features  Operating from VCC = 2.5 V to 5.5 V  200 mA output current on each amplifier  High dissipation package  Rail-to-rail input and output  Unity gain stable Applications  Hall sensor compensation coils  Servo amplifiers  Motor drivers  Industrial  Automotive March 2018 This is information on a product in full production. DocID009557 Rev 9 1/21 www.st.com Contents TS982 Contents 1 Absolute maximum ratings and operating conditions . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4 3.1 Exposed-pad package description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2 Exposed-pad electrical connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.3 Thermal management benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.4 Thermal management guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.5 Parallel operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1 SO-8 exposed pad package information . . . . . . . . . . . . . . . . . . . . . . . . . 17 5 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2/21 DocID009557 Rev 9 TS982 1 Absolute maximum ratings and operating conditions Absolute maximum ratings and operating conditions Table 1. Absolute maximum ratings (AMR) Symbol Parameter VCC Supply voltage(1) Vin Input voltage Value Unit 6 V -0.3 V to VCC +0.3 V V Toper Operating free-air temperature range -40 to + 125 °C Tstg Storage temperature -65 to +150 °C 150 °C 45 °C/W 10 °C/W 2 kV 1.5 kV 200 V Latch-up immunity (all pins) 200 mA Lead temperature (soldering, 10 s) 250 °C Tj Maximum junction temperature Rthja Thermal resistance junction to ambient Rthjc Thermal resistance junction to case Human body model (HBM) ESD (3) Charged device model (CDM)(4) Machine model (MM) Latch-up (2) (5) Output short-circuit duration See note (6) 1. All voltage values are measured with respect to the ground pin. 2. With two sides, two-plane PCB following the EIA/JEDEC JESD51-7 standard. 3. Human body model: A 100 pF capacitor is charged to the specified voltage, then discharged through a 1.5 kΩresistor between two pins of the device. This is done for all couples of connected pin combinations while the other pins are left floating. 4. Charged device model: all pins and the package are charged together to the specified voltage and then discharged directly to the ground through only one pin. This is done for all pins. 5. Machine model: A 200 pF capacitor is charged to the specified voltage, then discharged directly between two pins of the device with no external series resistor (internal resistor < 5 Ω). This is done for all couples of connected pin combinations while the other pins are left floating. 6. Short-circuits can cause excessive heating. Destructive dissipation can result from a short-circuit on one or two amplifiers simultaneously. Table 2. Operating conditions Symbol Parameter VCC Supply voltage Vicm Common mode input voltage range CL Load capacitor RL < 100 Ω RL > 100 Ω DocID009557 Rev 9 Value Unit 2.5 to 5.5 V GND to VCC V 400 100 pF 3/21 21 Electrical characteristics 2 TS982 Electrical characteristics Table 3. Electrical characteristics for VCC+ = +5 V, VCC- = 0 V, and Tamb = 25 °C (unless otherwise specified) Symbol Parameter Min. Typ. Max. Unit 5.5 7.2 7.2 mA 5 7 mV ICC Supply current - No input signal, no load Tmin < Top < Tmax VIO Input offset voltage (Vicm = VCC/2) Tmin < Top < Tmax 1 Input offset voltage drift 2 VIO IIB Input bias current - Vicm = VCC/2 Tmin < Top < Tmax IIO Input offset current Vicm = VCC/2 VOH VOL 200 500 500 10 High level output voltage RL = 16 Ω RL = 16 ΩTmin < Top < Tmax Iout = 200 mA 4.2 4 VCC= 4.75 V, T = 125 °C, Iout = 25 mA 4.3 Large signal voltage gain RL = 16 Ω GBP Gain bandwidth product RL = 32 Ω CMR V 4 Low level output voltage RL = 16 Ω RL = 16 Ω,Tmin < Top < Tmax Iout = 200 mA AVD nA nA 4.4 V 0.55 0.65 0.95 V 0.45 V 1 VCC = 4.75 V, T = 125 °C, Iout = 25 mA 95 dB 2.2 MHz Common mode rejection ratio 80 dB SVR Supply voltage rejection ratio 95 dB SR Slew rate, unity gain inverting RL = 16 Ω 0.7 V/µs m Phase margin at unit gain RL = 16 Ω, CL = 400 pF 56 Degrees Gm Gain margin RL = 16 , CL = 400 pF 18 dB en Equivalent input noise voltage F = 1 kHz 17 nV -----------Hz Channel separation RL = 16 , F = 1 kHz 100 dB Crosstalk 4/21 µV/°C DocID009557 Rev 9 1.35 0.45 TS982 Electrical characteristics Table 4. Electrical characteristics for VCC+ = +3.3 V, VCC- = 0 V, and Tamb = 25 °C (unless otherwise specified)(1) Symbol Parameter Min. Typ. Max. Unit 5.3 7.2 7.2 mA 5 7 mV ICC Supply current - No input signal, no load Tmin < Top < Tmax VIO Input offset voltage (Vicm = VCC/2) Tmin < Top < Tmax 1 Input offset voltage drift 2 VIO IIB Input bias current - Vicm = VCC/2 Tmin < Top < Tmax IIO Input offset current Vicm = VCC/2 VOH VOL 200 µV/°C 500 500 10 High level output voltage RL = 16 Ω RL = 16 ΩTmin < Top < Tmax Iout = 200 mA 2.68 2.64 Large signal voltage gain RL = 16 Ω GBP Gain bandwidth product RL = 32 Ω CMR nA 2.85 V 2.3 Low level output voltage RL = 16  RL = 16 Tmin < Top < Tmax Iout = 200 mA AVD nA 0.45 0.52 0.65 V 1 92 dB 2 MHz Common mode rejection ratio 75 dB SVR Supply voltage rejection ratio 95 dB SR Slew rate, unity gain inverting RL = 16 Ω 0.7 V/µs m Phase margin at unit gain RL = 16 Ω, CL = 400 pF 57 Degrees Gm Gain margin RL = 16 Ω, CL = 400 pF 16 dB en Equivalent input noise voltage F = 1 kHz 17 nV -----------Hz Channel separation RL = 16 ΩF = 1 kHz 100 dB Crosstalk 1.2 0.45 1. All electrical values are guaranteed by correlation with measurements at 2.7 V and 5 V. DocID009557 Rev 9 5/21 21 Electrical characteristics TS982 Table 5. Electrical characteristics for VCC = +2.7 V, VCC- = 0 V, and Tamb = 25 °C (unless otherwise specified) Symbol Min. Typ. Max. Unit 5.3 6.4 6.4 mA 5 7 mV ICC Supply current - No input signal, no load Tmin < Top < Tma VIO Input offset voltage (Vicm = VCC/2) Tmin < Top < Tmax 1 Input offset voltage drift 2 VIO IIB Input bias current - Vicm = VCC/2 Tmin < Top < Tmax IIO Input offset current Vicm = VCC/2 VOH VOL 200 µV/°C 500 500 10 High level output voltage RL = 16 Ω RL = 16 ΩTmin < Top < Tmax Iout = 20 mA 2.3 2.25 Large signal voltage gain RL = 16 Ω GBP Gain bandwidth product RL = 32 Ω CMR nA nA 2.85 V 2.3 Low level output voltage RL = 16 Ω RL = 16 ΩTmin < Top < Tmax Iout = 200 mA AVD 0.45 0.37 0.42 V 1 92 dB 2 MHz Common mode rejection ratio 75 dB SVR Supply voltage rejection ratio 95 dB SR Slew rate, unity gain inverting RL = 16 Ω 0.7 V/µs m Phase margin at unit gain RL = 16 Ω, CL = 400 pF 57 Degrees Gm Gain margin RL = 16 Ω, CL = 400 pF 16 dB en Equivalent input noise voltage F = 1 kHz 17 nV -----------Hz Channel separation RL = 16 ΩF = 1 kHz 100 dB Crosstalk 6/21 Parameter DocID009557 Rev 9 1.2 0.45 TS982 Electrical characteristics Figure 1. Current consumption vs. supply voltage Figure 2. Voltage drop vs. output sourcing current No load Figure 3. Voltage drop vs. output sinking current Figure 4. Voltage drop vs. supply voltage (sourcing) Figure 5. Voltage drop vs. supply voltage (sinking) Figure 6. Voltage drop vs. temperature (Iout = 50 mA) DocID009557 Rev 9 7/21 21 Electrical characteristics 8/21 TS982 Figure 7. Voltage drop vs. temperature (Iout = 100 mA) Figure 8. Voltage drop vs. temperature (Iout = 200 mA) Figure 9. Open loop gain and phase vs. frequency (VCC = 2.7 V, RL = 8 Ω) Figure 10. Open loop gain and phase vs. frequency (VCC = 5 V, RL = 8 Ω) Figure 11. Open loop gain and phase vs. frequency (VCC = 2.7 V, RL = 16 Ω) Figure 12. Open loop gain and phase vs. frequency (VCC = 5 V, RL = 16 Ω) DocID009557 Rev 9 TS982 Electrical characteristics Figure 13. Open loop gain and phase vs. frequency (VCC = 2.7 V, RL = 32 Ω) Figure 14. Open loop gain and phase vs. frequency (VCC = 5 V, RL = 32 Ω) Figure 15. Open loop gain and phase vs. frequency (VCC = 2.7 V, RL = 600 Ω) Figure 16. Open loop gain and phase vs. frequency (VCC = 5 V, RL = 600 Ω) Figure 17. Open loop gain and phase vs. frequency (VCC = 2.7 V, RL = 5 kΩ) Figure 18. Open loop gain and phase vs. frequency (VCC = 2.7 V, RL = 5 kΩ) DocID009557 Rev 9 9/21 21 Electrical characteristics TS982 Figure 20. Gain margin vs. supply voltage (RL= 8 Ω) 50 50 40 40 Gain margin (dB) Phase margin (deg.) Figure 19. Phase margin vs. supply voltage (RL = 8 Ω) 30 20 30 20 10 10 0 2.0 2.5 3.0 3.5 4.0 Power supply voltage (V ) 4.5 0 2.0 5.0 50 50 40 40 30 20 10 0 2.0 2.5 3.0 3.5 4.0 Power supply voltage (V ) 4.5 20 50 50 40 40 30 20 2.5 3.0 3.5 4.0 Power supply voltage (V ) 4.5 5.0 Figure 24. Gain margin vs. supply voltage (RL = 32 Ω) Gain margin (dB) Phase margin (deg.) 5.0 30 0 2.0 5.0 30 20 10 10 10/21 4.5 10 Figure 23. Phase margin vs. supply voltage (RL = 32 Ω) 0 2.0 3.0 3.5 4.0 Power supply voltage (V ) Figure 22. Gain margin vs. supply voltage (RL = 16 Ω) Gain margin (dB) Phase margin (deg.) Figure 21. Phase margin vs. supply voltage (RL = 16 Ω) 2.5 2.5 3.0 3.5 4.0 Power supply voltage (V ) 4.5 5.0 0 2.0 DocID009557 Rev 9 2.5 3.0 3.5 4.0 Power supply voltage (V ) 4.5 5.0 TS982 Electrical characteristics Figure 26. Gain margin vs. supply voltage (RL = 600 Ω) Figure 25. Phase margin vs. supply voltage (RL = 600 Ω) 20 70 50 Gain margin (dB) Phase margin (deg.) 60 40 30 20 10 10 0 2.0 2.5 3.0 3.5 4.0 Power supply voltage (V ) 4.5 0 2.0 5.0 Figure 27. Phase margin vs. supply voltage (RL = 5 kΩ) 2.5 3.0 3.5 4.0 Power supply voltage (V ) 4.5 5.0 Figure 28. Gain margin vs. supply voltage (RL = 5 kΩ) 70 20 50 Gain margin (dB) Phase margin (deg.) 60 40 30 20 10 10 0 2.0 2.5 3.0 3.5 4.0 Power supply voltage (V ) 4.5 Figure 29. Distortion vs. output voltage (RL = 2 Ω, F = 1 kHz, AV = +1, BW< 80 kHz) 5.0 0 2.0 2.5 3.0 3.5 4.0 Power supply voltage (V ) 4.5 5.0 Figure 30. Distortion vs. output voltage (RL = 4 Ω, F = 1 kHz, AV = +1, BW< 80 kHz) =5V = 3.3 V DocID009557 Rev 9 11/21 21 Electrical characteristics TS982 Figure 31. Distortion vs. output voltage (RL = 8 Ω, F = 1 kHz, AV = +1, BW< 80 kHz) = 2.7 V Figure 32. Distortion vs. output voltage (RL = 16 Ω, F = 1 kHz, AV = +1, BW< 80 kHz) =5V = 2.7 V = 3.3 V =5V = 3.3 V Figure 33. Crosstalk vs. frequency (RL = 8 Ω, VCC= 5 V, Pout = 100 mW, AV = -1, BW
TS982IDW 价格&库存

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