TSB571, TSB572
Datasheet
Low-power, 2.5 MHz, RR IO, 36 V BiCMOS operational amplifier
Features
TSB571
SOT23-5
TSB572
MiniSO8
SO8
DFN8 (3x3 mm)
•
•
•
•
•
•
•
•
•
•
•
•
Low-power consumption: 380 µA typ.
Wide supply voltage: 4 V - 36 V
Rail-to-rail input and output
Gain bandwidth product: 2.5 MHz
Low input bias current: 30 nA max.
No phase reversal
High tolerance to ESD: 4 kV HBM
Extended temperature range: -40 °C to 125 °C
Automotive grade
Small SMD packages
40 V BiCMOS technology
Enhanced stability vs. capacitive load
Applications
Maturity status link
For below 100 µA
solution
•
•
•
•
•
•
For a higher precision
Description
TSB571, TSB572
Related products
TSB611
TSB711
TSB712
Active filtering
Audio systems
Automotive
Power supplies
Industrial
Low/high side current sensing
The TSB571 (single) and TSB572 (dual) operational amplifiers offer an extended
voltage operating range from 4 V to 36 V and rail-to-rail input/output.
The TSB571 and TSB572 give a very good speed/power consumption ratio with a
2.5 MHz gain bandwidth product and a consumption of 380 µA typically only at 36 V
supply voltage.
Stability and robustness of these devices make them an ideal solution for a wide
voltage range of applications.
DS11248 - Rev 9 - October 2022
For further information contact your local STMicroelectronics sales office.
www.st.com
TSB571, TSB572
Package pin connections
1
Package pin connections
Figure 1. Pin connections (top view)
VCC+
OUT
VCC-
IN-
IN+
SOT23-5
Table 1. Pin description (SOT23-5)
DS11248 - Rev 9
Pin n°
Pin name
Description
1
OUT
Output channel
2
VCC-
Negative supply voltage
3
IN1+
Non-inverting input channel
4
IN-
Inverting input channel
5
VCC+
Positive supply voltage
page 2/31
TSB571, TSB572
Package pin connections
Figure 2. Pin connections for each package (top view)
Out1
VCC+
Out1
VCC+
In1-
Out2
In1-
Out2
In1+
In2-
In1+
In2-
VCC-
In2+
VCC-
In2+
SO8
MiniSO8
Out1
1
8
VCC+
In1-
2
7
Out2
In1+
3
6
In2-
VCC-
4
5
In2+
DFN8 (3 x 3)
1.
(1)
Exposed pad can be left floating or connected to ground.
Table 2. Pin description (miniSO8/SO8/DFN8)
DS11248 - Rev 9
Pin
Pin name
1
OUT1
2
IN1-
Inverting input channel 1
3
IN1+
Non-inverting input channel 1
4
VCC-
Negative supply voltage
5
IN2+
Non-inverting input channel 2
6
IN2-
Inverting input channel 2
7
OUT2
Output channel 2
8
VCC+
Positive supply voltage
Description
Output channel 1
page 3/31
TSB571, TSB572
Absolute maximum ratings and operating conditions
2
Absolute maximum ratings and operating conditions
Table 3. Absolute maximum ratings
Symbol
Parameter
Value
VCC
Supply voltage (1)
40
Vid
Differential input voltage (2)
±1
Vin
Input voltage
Iin
Input current (4)
Tstg
Tj
(3)
(VCC
Storage temperature
+ 0.2
-65 to 150
Maximum junction temperature
150
Thermal resistance junction to MiniSO8
ambient (5) (6)
DFN8 3x3
SO-8
(7)
mA
°C
250
190
40
°C/W
125
4
kV
Machine model (MM) (8)
100
V
CDM: charged device model (9)
1.5
kV
Human body model (HBM)
ESD
- 0.2 to (VCC
V
+)
10
SOT23-5
Rthja
-)
Unit
1. All voltage values, except the differential voltage are with respect to network ground terminal.
2. Differential voltages are the non-inverting input terminal with respect to the inverting input terminal.
3. VCC-Vin must not exceed 40 V, Vin must not exceed 40 V.
4. Input current must be limited by a resistor in-series with the inputs.
5. Rth are typical values.
6. Short-circuits can cause excessive heating and destructive dissipation.
7. According to JEDEC standard JESD22-A114F.
8. According to JEDEC standard JESD22-A115A.
9. According to ANSI/ESD STM5.3.1.
Table 4. Operating conditions
Symbol
DS11248 - Rev 9
Parameter
VCC
Supply voltage
Vicm
Common mode input voltage range
Toper
Operating free-air temperature range
Value
Unit
4 to 36
(VCC -) - 0.1 to (VCC +) + 0.1
-40 to 125
V
°C
page 4/31
TSB571, TSB572
Electrical characteristics
3
Electrical characteristics
Table 5. Electrical characteristics at Vcc = 4 V, Vicm = Vcc/2, Tamb = 25 °C, and RL connected to Vcc/2 (unless otherwise
specified)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
-1.5
-0.2
1.5
Unit
DC performance
Vio
ΔVio/ΔT
Iio
Iib
Input offset voltage
Input offset voltage drift
Input offset current
Input bias current
-40 °C < T < 125 °C
-2.1
-40 °C < T < 125 °C
2.1
1.5
6
2
15
-40 °C < T < 125 °C
35
8
-40 °C < T < 125 °C
30
mV
μV/°C
nA
70
CIN
Input capacitor
2
pF
RIN
Input impedance
1
TΩ
CMR
Common mode rejection
ratio 20 log (ΔVicm/ΔVio)
Avd
Large signal voltage gain
VOH
High level output voltage
(drop voltage from (VCC+))
VOL
Low level output voltage
Isink
Iout
Isource
ICC
Supply current (per channel)
Vicm = (VCC-) to (VCC+) - 1.5 V, Vout = VCC/2
90
-40 °C < T < 125 °C
80
Vicm = (VCC-) to (VCC+), Vout = VCC/2
75
-40 °C < T < 125 °C
70
RL= 10 kΩ, Vout = 0.5 to 3.5 V
90
-40 °C < T < 125 °C
85
RL = 10 kΩ
114
97
dB
100
19
-40 °C < T < 125 °C
60
80
RL = 10 kΩ
12
-40 °C < T < 125 °C
50
mV
70
Vout = VCC
20
-40 °C < T < 125 °C
5
Vout = 0 V
10
-40 °C < T < 125 °C
5
No load, Vout = VCC/2
38
mA
32
340
-40 °C < T < 125 °C
430
μA
500
AC performance
GBP
Gain bandwidth product
RL = 10 kΩ, CL = 100 pF
1.5
-40 °C < T < 125 °C
1.2
2.2
MHz
ϕm
Phase margin
RL = 10 kΩ, CL = 100 pF
45
degrees
Gm
Gain margin
RL = 10 kΩ, CL = 100 pF
5
dB
Negative slew rate
SR
Positive slew rate
en
Equivalent input noise
voltage
DS11248 - Rev 9
Vin = 3.5 to 0.5 V, Av = 1, 10 % to 90 %, RL = 10 kΩ, CL= 100 pF
0.50
-40 °C < T < 125 °C
0.37
Vin = 0.5 to 3.5 V, Av = 1, 10% to 90%, RL = 10 kΩ, CL= 100 pF
0.50
-40 °C < T < 125 °C
0.37
f = 1 kHz
0.78
0.89
20
V/μs
nV/√Hz
page 5/31
TSB571, TSB572
Electrical characteristics
Symbol
en
THD+N
Parameter
Conditions
Equivalent input noise
voltage
f = 0.1 Hz to 10 Hz
Total harmonic distortion +
noise
f = 1 kHz, Vin = 3.8 Vpp, RL = 10 kΩ, CL=100 pF
DS11248 - Rev 9
Min.
Typ.
Max.
Unit
0.7
μVpp
0.001
%
page 6/31
TSB571, TSB572
Electrical characteristics
Table 6. Electrical characteristics at Vcc = 12 V, Vicm = Vcc/2, Tamb = 25 °C, and RL connected to Vcc/2 (unless otherwise
specified)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
-1.5
-0.1
1.5
Unit
DC performance
Vio
ΔVio/ΔT
Iio
Iib
Input offset voltage
Input offset voltage drift
Input offset current
Input bias current
-40 °C < T < 125 °C
-2.1
-40 °C < T < 125 °C
2.1
1.5
6
2
15
-40 °C < T < 125 °C
35
8
-40 °C < T < 125 °C
30
mV
μV/°C
nA
70
CIN
Input capacitor
2
pF
RIN
Input impedance
1
TΩ
CMR
Common mode rejection
ratio 20 log (ΔVicm/ΔVio)
SVR
Supply voltage rejection
ratio 20 log (ΔVCC/ΔVio)
Avd
Large signal voltage gain
VOH
High level output voltage
(drop voltage from VCC+)
VOL
Low level output voltage
Isink
Iout
Isource
ICC
Supply current (per channel)
Vicm = (VCC-) to (VCC+) - 1.5 V, Vout = VCC/2
100
-40 °C < T < 125 °C
90
Vicm = (VCC-) to (VCC+), Vout = VCC/2
85
-40 °C < T < 125 °C
80
VCC = 4 to 12 V
90
-40 °C < T < 125 °C
80
RL= 10 kΩ, Vout = 0.5 to 11.5 V
95
-40 °C < T < 125 °C
90
RL = 10 kΩ
123
106
dB
99
106
38
-40 °C < T < 125 °C
100
150
RL = 10 kΩ
16
-40 °C < T < 125 °C
70
mV
90
Vout = VCC
20
-40 °C < T < 125 °C
8
Vout = 0 V
15
-40 °C < T < 125 °C
7
No load, Vout = VCC/2
42
mA
35
360
-40 °C < T < 125 °C
450
530
μA
AC performance
GBP
Gain bandwidth product
RL = 10 kΩ, CL = 100 pF
1.6
-40 °C < T < 125 °C
1.3
2.4
MHz
ϕm
Phase margin
RL = 10 kΩ, CL = 100 pF
50
degrees
Gm
Gain margin
RL = 10 kΩ, CL = 100 pF
6
dB
Negative slew rate
Vin = 10.5 to 1.5 V, Av = 1, 10 % to 90 %, RL = 10 kΩ,
CL = 100 pF
0.53
-40 °C < T < 125 °C
0.40
Vin = 1.5 to 10.5 V, Av = 1, 10 % to 90 %, RL = 10 kΩ,
CL = 100 pF
0.55
-40 °C < T < 125 °C
0.40
SR
Positive slew rate
DS11248 - Rev 9
0.82
V/μs
0.92
page 7/31
TSB571, TSB572
Electrical characteristics
Symbol
en
THD+N
Parameter
Equivalent input noise
voltage
Total harmonic distortion +
noise
DS11248 - Rev 9
Conditions
Min.
Typ.
Max.
Unit
f = 1 kHz
20
nV/√Hz
f = 0.1 Hz to 10 Hz
0.7
μVpp
0.000
5
%
f = 1 kHz, Vin = 7 Vpp, RL = 10 kΩ, CL= 100 pF
page 8/31
TSB571, TSB572
Electrical characteristics
Table 7. Electrical characteristics at Vcc = 36 V, Vicm = Vcc/2, Tamb = 25 °C, and RL connected to Vcc/2 (unless otherwise
specified)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
-1.5
0.1
1.5
Unit
DC performance
Vio
ΔVio/ΔT
ΔVio
Iio
Iib
Input offset voltage
-40 °C < T < 125 °C
-2.1
2.1
Input offset voltage drift
-40 °C < T < 125 °C
1.5
Long-term input offset voltage
drift (1)
T = 25 °C
1.5
Input offset current
Input bias current
2
-40 °C < T < 125 °C
6
-40 °C < T < 125 °C
μV/°C
µV/√month
15
35
8
mV
30
nA
70
CIN
Input capacitor
2
pF
RIN
Input impedance
1
TΩ
CMR
Common mode rejection ratio 20
log (ΔVicm/ΔVio)
SVR
Supply voltage rejection ratio 20
log (ΔVCC/ΔVio)
Avd
Large signal voltage gain
VOH
High level output voltage (drop
voltage from VCC+)
VOL
Low level output voltage
Isink
Iout
Isource
ICC
Supply current (per channel)
Vicm = (VCC-) to (VCC+) - 1.5 V, Vout = VCC/2
105
-40 °C < T < 125 °C
95
Vicm = (VCC-) to (VCC+), Vout = VCC/2
95
-40 °C < T < 125 °C
90
VCC = 4 to 36 V
90
-40 °C < T < 125 °C
85
RL= 10 kΩ, Vout = 0.5 to 35.5 V
95
-40 °C < T < 125 °C
90
RL = 10 kΩ
129
115
dB
104
114
78
-40 °C < T < 125 °C
150
200
RL = 10 kΩ
30
-40 °C < T < 125 °C
90
mV
120
Vout = VCC
25
-40 °C < T < 125 °C
10
Vout = 0 V
20
-40 °C < T < 125 °C
10
No load, Vout = VCC/2
65
mA
50
380
-40 °C < T < 125 °C
470
550
μA
AC performance
GBP
Gain bandwidth product
RL = 10 kΩ, CL = 100 pF
1.7
-40 °C < T < 125 °C
1.4
2.5
MHz
ϕm
Phase margin
RL = 10 kΩ, CL = 100 pF
50
degrees
Gm
Gain margin
RL = 10 kΩ, CL = 100 pF
8
dB
Vin = 22.5 to 13.5 V, Av = 1, 10 % to 90 %, RL = 10 kΩ,
CL = 100 pF
0.57
SR
Negative slew rate
-40 °C < T < 125 °C
0.44
DS11248 - Rev 9
0.88
V/μs
page 9/31
TSB571, TSB572
Electrical characteristics
Symbol
SR
en
THD+N
Parameter
Positive slew rate
Equivalent input noise voltage
Total harmonic distortion + noise
Conditions
Min.
Typ.
Vin = 13.5 to 22.5 V, Av = 1, 10 % to 90 %, RL = 10 kΩ,
CL = 100 pF
0.60
1.00
-40 °C < T < 125 °C
0.44
Max.
Unit
V/μs
f = 1 kHz
20
nV/√Hz
f = 0.1 Hz to 10 Hz
0.7
μVpp
0.001
%
f = 1 kHz, Vin = 7 Vpp, RL = 10 kΩ, CL = 100 pF
1. Typical value is based on the Vio drift observed after 1000h at 125 °C extrapolated to 25 °C using Arrhenius law and assuming an activation
energy of 0.7 eV. The operational amplifier is aged in follower mode configuration (see Section 4.5 Section 4.5).
DS11248 - Rev 9
page 10/31
TSB571, TSB572
Electrical characteristics
Figure 4. Input offset voltage distribution at VCC = 4 V
Figure 3. Supply current vs. supply voltage
0.5
35
T = 125 °C
0.4
T = 25°C
0.3
0.2
Vcc=4V
Vicm=2V
T=25°C
30
Population (%)
Supply Current (mA)
Vicm = Vcc/2
T = -40°C
25
20
15
10
0.1
5
0.0
0
5
10
15
20
25
30
0
-1.5
35
-1.2
-0.9
Supply Voltage (V)
0.3
0.6
0.9
1.2
1.5
35
Vcc=12V
Vicm=6V
T=25°C
30
Population (%)
Population (%)
0.0
Figure 6. Input offset voltage distribution at VCC = 36 V
35
25
20
15
20
15
10
5
5
0
-1.5
-1.2
-0.9
-0.6
-0.3
0.0
0.3
0.6
0.9
1.2
1.5
0
-1.5
-1.2
-0.9
-0.6
-0.3
0.0
0.3
0.6
0.9
1.2
1.5
Input offset voltage (mV)
Input offset voltage (mV)
Figure 7. Input offset voltage vs. temperature at
VCC = 36 V
2.5
Vcc=36V
Vicm=18V
T=25°C
25
10
Figure 8. Input offset voltage temperature variation
distribution at VCC = 36 V
Vio limit
2.0
Input offset voltage (mV)
-0.3
Input offset voltage (mV)
Figure 5. Input offset voltage distribution at VCC = 12 V
30
-0.6
1.5
1.0
0.5
0.0
-0.5
-1.0
-1.5
Vcc=36V
Vicm=18V
-2.0
-2.5
-40
DS11248 - Rev 9
-20
0
20
40
60
Temperature (°C)
80
100
120
page 11/31
TSB571, TSB572
Electrical characteristics
Figure 9. Input offset voltage vs. supply voltage
Figure 10. Input offset voltage vs. common-mode voltage
at VCC = 4 V
Input Offset Voltage (mV)
-0.2
Vicm=Vcc/2
-0.3
-0.4
-0.5
-0.6
T=25°C
T=125°C
-0.7
-0.8
4
8
12
T=-40°C
16
20
24
28
Supply voltage (V)
32
36
Figure 11. Input offset voltage vs. common-mode voltage
at VCC = 36 V
Figure 12. Input bias current vs. temperature at
VICM = VCC/2
0
Input bias current (nA)
Vicm=Vcc/2
-2
-4
-6
Vcc=4V
Vcc=12V
Vcc=36V
-8
-10
-40
-20
0
20
40
60
80
100
120
Temperature (°C)
Figure 13. Input bias current vs. common-mode voltage at
VCC = 36 V
Figure 14. Output current vs. output voltage at VCC = 4 V
50
60
T=-40°C
40
Output Current (mA)
Input bias current (nA)
Vcc=36V
T=25°C
20
T=125°C
0
-20
Sink
40 Vid=-1V
30
20
10
0
-10
T=-40°C
T=25°C
T=125°C
-20
-30
-40
-40
-60
0
5
10
15
20
25
Input Common Mode Voltage (V)
DS11248 - Rev 9
30
35
-50
0.0
Vcc=4V
0.5
1.0
1.5 2.0 2.5 3.0
Output Voltage (V)
Source
Vid=1V
3.5
4.0
page 12/31
TSB571, TSB572
Electrical characteristics
70
Output Current (mA)
56
Vcc=36V
Sink
Vid=-1V
42
28
14
0
T=125°C
T=-40°C
T=25°C
-14
-28
-42
Source
Vid=1V
-56
-70
0
5
10
15
20
25
Output Voltage (V)
30
Figure 16. Output voltage (Voh) vs. supply voltage
Output voltage drop (from Vcc+) (mV)
Figure 15. Output current vs. output voltage at VCC = 36 V
110
100
90
80
70
60
50
40
20
Vid=0.1V
Rl=10kΩ
to Vcc/2
10
0
35
T=125°C
T=25°C
T=-40°C
30
4
8
12
16
20
24
28
Power supply voltage (V)
1.2
40
Vcc=36V
Vicm=Vcc/2
Rl=10kΩ
Cl=100pF
1.0
0.8
T=-40°C
0.6
30
0.4
25
Voltage (V)
Output voltage (mV)
35
20
15
T=25°C
0.2
0.0
T=125°C
-0.2
-0.4
10
T=-40°C T=25°C
5
-0.6
T=125°C
-0.8
Vid=-0.1V
to Vcc/2
Rl=10kΩ
4
8
-1.0
12
16
20
24
28
Power supply voltage (V)
32
36
-1.2
0.0
1.0
0.6
0.4
T=-40°C
T=25°C
-0.2
Vcc=36V
Vicm=Vcc/2
Rl=10kΩ
Cl=100pF
-0.4
T=125°C
-0.6
-0.8
-1.0
-1.2
0.0
0.5
1.0
1.5
2.0
Time (µs)
DS11248 - Rev 9
2.5
3.0
3.5
4.0
Slew rate (V/µs)
0.8
0.0
1.0
1.5
2.0
2.5
3.0
3.5
4.0
Figure 20. Slew rate vs. supply voltage
1.2
0.2
0.5
Time (µs)
Figure 19. Positive slew rate at VCC = 36 V
Voltage (V)
36
Figure 18. Negative slew rate at VCC = 36 V
Figure 17. Output voltage (Vol) vs. supply voltage
0
32
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
-1.2
-1.4
4.0
Vicm=Vcc/2
T=125°C T=25°C T=-40°C Vload=Vcc/2
Rl=10kΩ
Cl=100pF
8.0
12.0 16.0 20.0 24.0 28.0 32.0 36.0
Supply Voltage (V)
page 13/31
TSB571, TSB572
Electrical characteristics
Figure 21. Bode diagram at VCC = 4 V
0
40
Phase
Gain
0
-40
-60
1k
10k
100k
40
-120
20
-180
Vcc=4V
Vicm=2V
Rl=10kΩ
Cl=100pF
Gain=100
-20
-60
Phase (°)
20
60
1M
0
T=-40°C
T=25°C
T=125°C
Phase
0
-180
-240
-20
-300
-40
-360
10M
-60
Vcc=36V
Vicm=18V
Rl=10kΩ
Cl=100pF
Gain=100
1k
-240
-300
10k
100k
Figure 24. Phase margin vs. output current at VCC = 36 V
100
100
90
90
80
80
70
70
60
60
50
50
40
40
30
30
20
20
10
10
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
0
-1.0
1.0
Figure 25. Phase margin vs. capacitive load
Overshoot (%)
Phase margin(°)
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
Vcc=36V
Vicm=Vcc/2
Rl=10kΩ
Vin=100mVpp
Gain=1
T=25°C
80
30
Vcc=4V
20
Vcc=36V
Vicm=Vcc/2
Rl=10kΩ
T=25°C
60
40
20
Sustained Oscillations
0
200
300
400
500
Capacitive load (pF)
DS11248 - Rev 9
-0.6
100
40
0
100
-0.8
Figure 26. Overshoot vs. capacitive load at VCC = 36 V
50
10
-360
10M
1M
Frequency (Hz)
Figure 23. Phase margin vs. output current at VCC = 4 V
-0.8
-120
Gain
Frequency (Hz)
0
-1.0
-60
Phase (°)
T=-40°C
T=25°C
T=125°C
Gain (dB)
60
Gain (dB)
Figure 22. Bode diagram at VCC = 36 V
700
1000
10
100
1000
10000
Capacitive load (pF)
page 14/31
TSB571, TSB572
Electrical characteristics
Figure 27. Small step response vs. time at VCC = 4 V
Figure 28. Output desaturation vs. time
Vcc=4V
Vicm=2V
Rl=10kΩ
Cl=100pF
Follower
Configuration
T=25°C
0.07
20
Input and Output voltages (V)
Output Voltage (V)
0.15
0.00
-0.07
Vcc=+/-18V
Vicm=0V
Gain=4.7
Rl=10kΩ
Cl=100pF
15
10
5
0
-5
-10
-15
-20
0
-0.15
0.0
2.5
5.0
Time (µs)
7.5
36.00
35.95
35.90
35.85
35.80
35.70
35.75
0.25
0.20
0.15
0.10
0.05
Vcc=36V
Follower configuration
60
40
20
0
10
100
1000
Frequency (Hz)
10000
Figure 32. THD+N vs. frequency
0.01
400
Vicm=Vcc/2
Gain=1
Rl=10kΩ
Cl=100pF
BW=80kHz
T=25°C
Vcc=36V
300 Vicm=Vcc/2
Vload=Vcc/2
200
THD + N (%)
Input voltage nosie (nV)
1000
@Vcc=36V
@Vcc=12V
@Vcc=4V
Vicm=Vcc/2
T=25°C
80
Figure 31. Noise vs. time at VCC = 36 V
100
0
-100
1E-3
-200
Vcc=4V
with Vin=3.8Vpp
Vcc=12V
with Vin=7Vpp
Vcc=36V
with Vin=7Vpp
-300
DS11248 - Rev 9
800
100
Input voltage (V)
-400
0
600
Figure 30. Noise vs. frequency at VCC = 36 V
Equivalent Input Noise Voltage (nV/√Hz)
T=-40°C
T=25°C
T=125°C
0.00
Output voltage (V)
36.00
35.95
35.90
35.85
35.80
35.75
35.70
400
Time (µs)
Figure 29. Amplifier behavior close to the rails at
VCC = 36 V
0.25
0.20
0.15
0.10
0.05
0.00
200
10.0
1
2
3
4
5
6
Time (s)
7
8
9
10
1E-4
10
100
1000
Frequency (Hz)
10000
page 15/31
TSB571, TSB572
Electrical characteristics
Figure 34. PSRR vs. frequency at VCC = 36 V
Figure 33. THD+N vs. output voltage
0.1
-20
0.01
1E-3
1E-4
0.01
Vicm=Vcc/2
Gain=1
f=1kHz
BW=22kHz
Rl=10kΩ
Cl=100pF
T=25°C
0.1
PSRR (dB)
THD + N (%)
-40
4V
PSRR +
-60
-80
12V
PSRR -100
36V
-120
1
10
Output Voltage (Vpp)
10
100
1k
10k
100k
Frequency (Hz)
Channel Separation refered to input (dB)
Figure 35. Channel separation vs. frequency at VCC= 36 V
160
Vcc=36V
Vicm=18V
Gain=11
Vin = 1Vpp
140
120
100
80
60
40
20
0
100
1k
10k
100k
1M
Frequency (Hz)
DS11248 - Rev 9
page 16/31
TSB571, TSB572
Application information
4
Application information
4.1
Operating voltages
The TSB571 and TSB572 can operate from 4 V to 36 V. The parameters are fully specified for 4 V, 12 V, and 36 V
power supplies. However, the parameters are stable in the full VCC range. Additionally, the main specifications are
guaranteed in extended temperature ranges from -40 to 125 °C.
4.2
Input pin voltage ranges
The TSB571 and TSB572 have an internal ESD diode protection on the inputs. These diodes are connected
between the inputs and each supply rail to protect the input transistors from electrical discharge.
If the input pin voltage exceeds the power supply by 0.2 V, the ESD diodes become conductive and excessive
current can flow through them. Without limitation this over current can damage the device.
In this case, it is important to limit the current to 10 mA, by adding resistance on the input pin, as shown in
Figure 37. Input current limitation.
Figure 36. Input current limitation
16 V
R
Vin
4.3
-
+
+
-
Vout
Rail-to-rail input
The TSB571 and TSB572 have rail-to-rail inputs. The input common mode range is extended from (VCC -) - 0.1 V
to (VCC+) + 0.1 V at T = 25 °C.
4.4
Input offset voltage drift over temperature
The maximum input voltage drift variation over temperature is defined as the offset variation related to the offset
value measured at 25 °C. The operational amplifier is one of the main circuits of the signal conditioning chain, and
the amplifier input offset is a major contributor to the chain accuracy. The signal chain accuracy at 25 °C can be
compensated during production at application level. The maximum input voltage drift over temperature enables
the system designer to anticipate the effect of temperature variations.
The maximum input voltage drift over temperature is computed using Equation 1.
Equation 1
∆V io
V ( T ) – V io ( 25 °C)
= ma x io
∆T
T – 25 °C
where T = -40 °C and 125 °C.
The TSB571 and TSB572 datasheet maximum value is guaranteed by measurements on a representative sample
size ensuring a Cpk (process capability index) greater than 1.3.
DS11248 - Rev 9
page 17/31
TSB571, TSB572
Long term input offset voltage drift
4.5
Long term input offset voltage drift
To evaluate product reliability, two types of stress acceleration are used:
•
•
Voltage acceleration, by changing the applied voltage
Temperature acceleration, by changing the die temperature (below the maximum junction temperature
allowed by the technology) with the ambient temperature.
The voltage acceleration has been defined based on JEDEC results, and is defined using Equation 2.
Equation 2
A FV = e
β . ( VS – VU )
Where:
AFV is the voltage acceleration factor
β is the voltage acceleration constant in 1/V, constant technology parameter (β = 1)
VS is the stress voltage used for the accelerated test
VU is the voltage used for the application
The temperature acceleration is driven by the Arrhenius model, and is defined in Equation 3.
Equation 3
A FT = e
E
1
1
-----a- .
–
k
TU TS
Where:
AFT is the temperature acceleration factor
Ea is the activation energy of the technology based on the failure rate
k is the Boltzmann constant (8.6173 x 10-5 eV.K-1)
TU is the temperature of the die when VU is used (K)
TS is the temperature of the die under temperature stress (K)
The final acceleration factor, AF, is the multiplication of the voltage acceleration factor and the temperature
acceleration factor (Equation 4).
Equation 4
A F = A FT × A FV
AF is calculated using the temperature and voltage defined in the mission profile of the product. The AF value can
then be used in Equation 5 to calculate the number of months of use equivalent to 1000 hours of reliable stress
duration.
Equation 5
Months = A F × 1000 h × 12 months / ( 24 h × 365.25 days )
To evaluate the op amp reliability, a follower stress condition is used where VCC is defined as a function of the
maximum operating voltage and the absolute maximum rating (as recommended by JEDEC rules).
The Vio drift (in µV) of the product after 1000 h of stress is tracked with parameters at different measurement
conditions (see Equation 6).
Equation 6
V CC = maxV op with V icm = V CC / 2
The long term drift parameter (ΔVio), estimating the reliability performance of the product, is obtained using the
ratio of the Vio (input offset voltage value) drift over the square root of the calculated number of months (Equation
7).
Equation 7
∆V io =
V io dr ift
( month s )
Where Vio drift is the measured drift value in the specified test conditions after 1000 h stress duration.
DS11248 - Rev 9
page 18/31
TSB571, TSB572
Capacitive load
4.6
Capacitive load
Driving large capacitive loads can cause stability problems. Increasing the load capacitance produces gain
peaking in the frequency response, with overshoot and ringing in the step response. It is usually considered that
with a gain peaking higher than 2.3 dB an op amp might become unstable.
Generally, unity gain configuration is the worst situation for stability and the ability to drive large capacitive loads.
Figure 38. Stability criteria with a serial resistor at different supply voltages shows the serial resistor that must be
added to the output, to make a system stable. Figure 39. Test configuration for Riso shows the test configuration
using an isolation resistor, Riso.
Figure 37. Stability criteria with a serial resistor at different supply voltages
Serial Riso (Ω)
100
Vcc=36V
Vicm=18V
follower
configuration
T=25°C
Stable
10
Unstable
1
@Vcc=4V
@Vcc=12V
@Vcc=36V
0.1 2
10
10 3
10 4
10 5
Capacitive load (pF)
10 6
Figure 38. Test configuration for Riso
V CC+
Riso
VIN
+
V CC-
4.7
Cload
VOUT
10 kΩ
PCB layout recommendations
Particular attention must be paid to the layout of the PCB tracks connected to the amplifier, load, and power
supply. The power and ground traces are critical as they must provide adequate energy and grounding for
all circuits. The best practice is to use short and wide PCB traces to minimize voltage drops and parasitic
inductance.
In addition, to minimizing parasitic impedance over the entire surface, a multi-via technique that connects the
bottom and top layer ground planes together in many locations is often used.
The copper traces that connect the output pins to the load and supply pins should be as wide as possible to
minimize trace resistance.
4.8
Optimized application recommendation
It is recommended to place a 22 nF capacitor as close as possible to the supply pin. A good decoupling will help
to reduce electromagnetic interference impact.
DS11248 - Rev 9
page 19/31
TSB571, TSB572
Package information
5
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages,
depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product
status are available at: www.st.com. ECOPACK is an ST trademark.
5.1
SOT23-5 package information
Figure 39. SOT23-5 package outline
Table 8. SOT23-5 package mechanical data
Dimensions
Millimeters
Ref.
A
Min.
Typ.
Max.
Min.
Typ.
Max.
0.90
1.20
1.45
0.035
0.047
0.057
A1
DS11248 - Rev 9
Inches
0.15
0.006
A2
0.90
1.05
1.30
0.035
0.041
0.051
B
0.35
0.40
0.50
0.014
0.016
0.020
C
0.09
0.15
0.20
0.004
0.006
0.020
D
2.80
2.90
3.00
0.110
0.114
0.118
D1
1.90
0.075
e
0.95
0.037
E
2.60
2.80
3.00
0.102
0.110
0.118
F
1.50
1.60
1.75
0.059
0.063
0.069
L
0.10
0.35
0.60
0.004
0.014
0.024
K
0°
10°
0°
10°
page 20/31
TSB571, TSB572
MiniSO8 package information
5.2
MiniSO8 package information
Figure 40. MiniSO8 package outline
Table 9. MiniSO8 package mechanical data
Dimensions
Millimeters
Ref.
Min.
Typ.
A
Max.
Min.
Typ.
1.1
A1
0
A2
0.75
b
Max.
0.043
0.15
0
0.95
0.030
0.22
0.40
0.009
0.016
c
0.08
0.23
0.003
0.009
D
2.80
3.00
3.20
0.11
0.118
0.126
E
4.65
4.90
5.15
0.183
0.193
0.203
E1
2.80
3.00
3.10
0.11
0.118
0.122
e
L
0.85
0.65
0.40
0.60
0.0006
0.033
0.80
0.016
0.024
0.95
0.037
L2
0.25
0.010
ccc
0°
0.037
0.026
L1
k
DS11248 - Rev 9
Inches
8°
0.10
0°
0.031
8°
0.004
page 21/31
TSB571, TSB572
DFN8 3x3 wettable flanks package information (package code: A03Y)
5.3
DFN8 3x3 wettable flanks package information (package code: A03Y)
Figure 41. DFN8 3x3 package outline and mechanical data
Table 10. DFN8 3x3 mechanical data
Symbol
mm
Min.
Typ.
Max.
A
0.70
0.75
0.80
A1
0.0
A2
0.10
A3
0.20 Ref.
b
0.25
0.30
0.35
D
2.95
3.00
3.05
D2
2.25
2.35
2.45
e
0.65 BSC
E
2.95
3.00
3.05
E2
1.45
1.55
1.65
L
0.35
0.45
0.55
K
DS11248 - Rev 9
0.05
0.275 Ref.
page 22/31
TSB571, TSB572
DFN8 3x3 wettable flanks package information (package code: A03Y)
Figure 42. DFN8 3x3 footprint data
DS11248 - Rev 9
page 23/31
TSB571, TSB572
SO8 package information
5.4
SO8 package information
Figure 43. SO8 package outline
0016023_So-807_fig2_Rev10
Table 11. SO8 mechanical data
Dim.
mm
Min.
Typ.
A
1.75
A1
0.10
A2
1.25
b
0.31
0.51
b1
0.28
0.48
0.25
c
0.10
0.25
c1
0.10
0.23
D
4.80
4.90
5.00
E
5.80
6.00
6.20
E1
3.80
3.90
4.00
e
1.27
h
0.25
0.50
L
0.40
1.27
L1
1.04
L2
0.25
k
ccc
DS11248 - Rev 9
Max.
0°
8°
0.10
page 24/31
TSB571, TSB572
SO8 package information
Figure 44. SO8 recommended footprint
DS11248 - Rev 9
page 25/31
TSB571, TSB572
Ordering information
6
Ordering information
Table 12. Order codes
Order code
TSB571ILT
TSB571IYLT (1)
Temperature range
Package
Packing
-40 °C to +125 °C
SOT23-5
Tape and reel
TSB572IQ2T
TSB572IST
-40 °C to 125 °C
TSB572IYST (1)
TSB572IDT
MiniSO8
SO8 package
K31
K32
K31
DFN8 3x3
TSB572IYQ2T (1)
Marking
K32
Tape and reel
K31
K32
TSB572I
1. Automotive qualification according to AEC-Q100.
DS11248 - Rev 9
page 26/31
TSB571, TSB572
Revision history
Table 13. Document revision history
Date
Version
Changes
12-Oct-2015
1
Initial release
17-Dec-2015
2
Section 2: "Absolute maximum ratings and operating conditions": updated ESD,
MM value. Section 6: "Ordering information": removed footnote (1) from order code
TSB572IQ2T
In Table1: "Absolute maximum ratings":
26-Jun-2017
3
- Updated Latch-up immunity Parameter Value
- updated footnote (3)
DS11248 - Rev 9
10-Nov-2017
4
Added: new SO-8 Package information and new order code TSB572IDT Section 6
Ordering information
26-Mar-2018
5
Updated: Section 5.2 DFN8 3x3 package information
22-Jul-2019
6
Added the root part number TSB571 and updated the whole document accordingly
06-May-2020
7
Updated cover page
09-Jun-2021
8
Added Vio Typ. value in Table 5, Table 6 and Table 7
24-Oct-2022
9
Updated Section 5.3 DFN8 3x3 wettable flanks package information (package
code: A03Y)
page 27/31
TSB571, TSB572
Contents
Contents
1
Package pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2
Absolute maximum ratings and operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
5
6
4.1
Operating voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2
Input pin voltage ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.3
Rail-to-rail input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.4
Input offset voltage drift over temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.5
Long term input offset voltage drift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.6
Capacitive load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.7
PCB layout recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.8
Optimized application recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
5.1
SOT23-5 package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.2
MiniSO8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.3
DFN8 3x3 wettable flanks package information (package code: A03Y). . . . . . . . . . . . . . . . . 22
5.4
SO8 package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
DS11248 - Rev 9
page 28/31
TSB571, TSB572
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Pin description (SOT23-5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin description (miniSO8/SO8/DFN8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical characteristics at Vcc = 4 V, Vicm = Vcc/2, Tamb = 25 °C, and RL connected to Vcc/2 (unless otherwise
specified) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical characteristics at Vcc = 12 V, Vicm = Vcc/2, Tamb = 25 °C, and RL connected to Vcc/2 (unless otherwise
specified) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical characteristics at Vcc = 36 V, Vicm = Vcc/2, Tamb = 25 °C, and RL connected to Vcc/2 (unless otherwise
specified) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SOT23-5 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MiniSO8 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DFN8 3x3 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SO8 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS11248 - Rev 9
.
.
.
.
2
3
4
4
. 5
. 7
. 9
20
21
22
24
26
27
page 29/31
TSB571, TSB572
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
DS11248 - Rev 9
Pin connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin connections for each package (top view) . . . . . . . . . . . . . . . .
Supply current vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . .
Input offset voltage distribution at VCC = 4 V . . . . . . . . . . . . . . . . .
Input offset voltage distribution at VCC = 12 V . . . . . . . . . . . . . . . .
Input offset voltage distribution at VCC = 36 V . . . . . . . . . . . . . . . .
Input offset voltage vs. temperature at VCC = 36 V . . . . . . . . . . . .
Input offset voltage temperature variation distribution at VCC = 36 V
Input offset voltage vs. supply voltage . . . . . . . . . . . . . . . . . . . . .
Input offset voltage vs. common-mode voltage at VCC = 4 V . . . . . .
Input offset voltage vs. common-mode voltage at VCC = 36 V . . . . .
Input bias current vs. temperature at VICM = VCC/2 . . . . . . . . . . . .
Input bias current vs. common-mode voltage at VCC = 36 V . . . . . .
Output current vs. output voltage at VCC = 4 V . . . . . . . . . . . . . . .
Output current vs. output voltage at VCC = 36 V . . . . . . . . . . . . . .
Output voltage (Voh) vs. supply voltage . . . . . . . . . . . . . . . . . . . .
Output voltage (Vol) vs. supply voltage . . . . . . . . . . . . . . . . . . . .
Negative slew rate at VCC = 36 V . . . . . . . . . . . . . . . . . . . . . . . .
Positive slew rate at VCC = 36 V . . . . . . . . . . . . . . . . . . . . . . . . .
Slew rate vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bode diagram at VCC = 4 V . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bode diagram at VCC = 36 V . . . . . . . . . . . . . . . . . . . . . . . . . . .
Phase margin vs. output current at VCC = 4 V . . . . . . . . . . . . . . . .
Phase margin vs. output current at VCC = 36 V . . . . . . . . . . . . . . .
Phase margin vs. capacitive load . . . . . . . . . . . . . . . . . . . . . . . .
Overshoot vs. capacitive load at VCC = 36 V. . . . . . . . . . . . . . . . .
Small step response vs. time at VCC = 4 V . . . . . . . . . . . . . . . . . .
Output desaturation vs. time. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Amplifier behavior close to the rails at VCC = 36 V . . . . . . . . . . . . .
Noise vs. frequency at VCC = 36 V . . . . . . . . . . . . . . . . . . . . . . .
Noise vs. time at VCC = 36 V . . . . . . . . . . . . . . . . . . . . . . . . . . .
THD+N vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
THD+N vs. output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PSRR vs. frequency at VCC = 36 V . . . . . . . . . . . . . . . . . . . . . . .
Channel separation vs. frequency at VCC= 36 V . . . . . . . . . . . . . .
Input current limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stability criteria with a serial resistor at different supply voltages . . .
Test configuration for Riso . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SOT23-5 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MiniSO8 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DFN8 3x3 package outline and mechanical data . . . . . . . . . . . . . .
DFN8 3x3 footprint data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SO8 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SO8 recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . .
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page 30/31
TSB571, TSB572
IMPORTANT NOTICE – READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST
products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST
products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgment.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of
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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2022 STMicroelectronics – All rights reserved
DS11248 - Rev 9
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