TSB7191, TSB7191A
TSB7192, TSB7192A
Datasheet
Precision rail-to-rail input / output 36 V, 22 MHz op-amps
TSB7192 and TSB7192A
MiniSO8
SO8
TSB7191 and TSB7191A
SOT23-5
Product status link
TSB7191, TSB7191A, TSB7192,
TSB7192A
Related products
TSB572
TSB712
TSB712A
Dual op-amps for the lowpower consumption version
(380 µA with 2.5 MHz GBP)
Precision rail-to-rail input /
output 36 V, 6 MHz dual opamps
Features
•
•
•
•
•
•
•
•
•
•
•
Rail-to-rail input and output
Low offset voltage: 300 µV maximum
Wide supply voltage range: 2.7 V to 36 V
Gain bandwidth product: 22 MHz
Slew rate: 12 V/µs
Low noise: 12 nV/√Hz
Stable with gain +10/-9
Integrated EMI filter
2 kV HBM ESD tolerance
Extended temperature range: -40 °C to +125 °C
Automotive-grade available
Applications
•
•
•
•
•
•
•
High-side and low-side current sensing
Hall effect sensors
Data acquisition and instrumentation
Test and measurement equipments
Motor control
Industrial process control
Strain gauge
Description
The TSB7191, TSB7191A, TSB7192 and the TSB7192A 22 MHz bandwidth amplifier
feature rail-to-rail input and output, which is guaranteed to operate from +2.7 V to
+36 V single supply as well as from ±1.35 V to ±18 V dual supplies.
These amplifiers have the advantage of offering a large span of supply voltage and
an excellent input offset voltage of 300 µV maximum at 25 °C.
The combination of wide bandwidth, slew rate, low noise, rail-to-rail capability and
precision makes the TSB7191, TSB7191A, TSB7192 and the TSB7192A useful in a
wide variety of applications such as: filters, power supply and motor control, actuator
driving, hall effect sensors and resistive transducers.
DS12641 - Rev 5 - October 2019
For further information contact your local STMicroelectronics sales office.
www.st.com
TSB7191, TSB7191A, TSB7192, TSB7192A
Pin description
1
Pin description
Figure 1. Pin connections (top view)
VCC+
OUT
VCC-
IN-
IN+
SOT23-5
Table 1. Pin description (SOT23-5)
Pin n°
Pin name
Description
1
OUT
Output channel
2
VCC-
Negative supply voltage
3
IN1+
Non-inverting input channel
4
IN-
Inverting input channel
5
VCC+
Positive supply voltage
Figure 2. Pin connections (top view)
OUT1
VCC+
IN1-
OUT2
IN1+
IN2-
VCC-
IN2+
MiniSO8/SO8
Table 2. Pin description (MiniSO8/SO8)
DS12641 - Rev 5
Pin n°
Pin name
1
OUT1
Description
Output channel 1
2
IN1-
Inverting input channel 1
3
IN1+
Non-inverting input channel 1
4
VCC-
Negative supply voltage
5
IN2+
Non-inverting input channel 2
6
IN2-
Inverting input channel 2
7
OUT2
Output channel 2
8
VCC+
Positive supply voltage
page 2/34
TSB7191, TSB7191A, TSB7192, TSB7192A
Absolute maximum ratings and operating conditions
2
Absolute maximum ratings and operating conditions
Table 3. Absolute maximum ratings
Symbol
Parameter
VCC
Supply voltage
Vid
Input voltage differential (2)
Vin
Input voltage
Iin
Input current
(1)
(3)
Storage temperature
Rth-ja
Tj
ESD
Thermal resistance junction-to-ambient
Value
Unit
+40 or ±20
V
±2
V
(VCC-) - 0.2 to (VCC+) + 0.2
V
±10
mA
-65 to +150
°C
(4) (5)
°C / W
MiniSO-8
190
Maximum junction temperature
150
°C
HBM: human body model (6)
2
kV
CDM: charged device model (7)
1
kV
100
mA
Latch-up immunity
1. All voltage values, except the differential voltage are with respect to the network ground terminal.
2. Differential voltages are the non-inverting input terminal with respect to the inverting input terminal. The maximum input
voltage differential value may be extended to the condition that the input current is limited to ±10 mA. See Input pin voltage
range.
3. Input current must be limited by a resistor in series with the inputs when the input voltage is beyond the rails (see Input pin
voltage range).
4. Short-circuits can cause excessive heating and destructive dissipation.
5. Rth are typical values.
6. Human body according to JEDEC standard JESD22-A114F.
7. According to ANSI/ESD STM5.3.1.
Table 4. Operating conditions
Symbol
DS12641 - Rev 5
Parameter
VCC
Supply voltage
Vicm
Common mode input voltage range
Toper
Operating free air temperature range
Value
2.7 V to 36 V
(VCC-) to (VCC+) + 0.1 V
-40 °C to +125 °C
page 3/34
TSB7191, TSB7191A, TSB7192, TSB7192A
Electrical characteristics
3
Electrical characteristics
Table 5. Electrical characteristics at VCC = 36 V, VICM = VOUT = VCC / 2, Tamb = 25 °C and RL connected to
VCC / 2 (unless otherwise specified)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
DC performance
TSB7191A, TSB7192A, T = 25 °C,
± 300
VCC- ≤ VICM ≤ VCC+ -1.5 V
TSB7191A, TSB7192A, T = 25 °C,
± 650
VCC- ≤ VICM ≤ VCC+
TSB7191A, TSB7192A, -40 °C < T <
125 °C,
± 580
VCC- ≤ VICM ≤ VCC+ -1.5 V
TSB7191A, TSB7192A, -40 °C < T <
125 °C,
Vio
Input offset voltage
± 930
VCC- ≤ VICM ≤ VCC+
µV
TSB7191, TSB7192, T = 25 °C,
± 800
VCC- ≤ VICM ≤ VCC+ -1.5 V
TSB7191, TSB7192, T = 25 °C,
± 1200
VCC- ≤ VICM ≤ VCC+
TSB7191, TSB7192, -40 °C < T < 125
°C,
± 1100
VCC- ≤ VICM ≤ VCC+ -1.5 V
TSB7191, TSB7192, -40 °C < T < 125
°C,
± 1400
VCC- ≤ VICM ≤ VCC+
ΔVio / ΔT
ΔVio
IIB
IIO
DS12641 - Rev 5
Input offset voltage drift -40 °C < T < 125 °C (1)
Long-term input offset
voltage drift
Input bias current (3)
Input offset current(4)
2.8
T = 25 °C (2)
0.57
µV/√mo
VICM = VCC+, T = 25 °C
0
300
VICM = VCC+, -40 °C < T < 125 °C
0
900
VICM = VCC-, T = 25 °C
-100
0
VICM = VCC-,-40 °C < T < 125 °C
-200
0
VICM = VCC+
10
VICM = VCC-
10
µV/°C
nA
page 4/34
TSB7191, TSB7191A, TSB7192, TSB7192A
Electrical characteristics
Symbol
Parameter
Conditions
Min.
Typ.
110
125
Max.
Unit
RL ≥ 10 kΩ,
(VCC-) + 0.5 V ≤ VOUT ≤ (VCC+) -0.5 V,
AVD
Open loop gain
T = 25 °C
RL ≥ 10 kΩ,
(VCC-) + 0.5 V ≤ VOUT ≤ (VCC+) -0.5 V,
-40 °C < T < 125 °C
(VCC-) ≤ VICM ≤ ( VCC+) - 1.5 V,
T = 25 °C
(VCC-) ≤ VICM ≤ (VCC+) - 1.5 V,
-40 °C < T < 125 °C
TSB7191A, TSB7192A (VCC-) ≤ VICM ≤
(VCC+),
CMR
Common-mode
rejection ratio
20 log (∆VINCM / ∆VIO)
105
115
130
110
100
120
dB
T = 25 °C
TSB7191A, TSB7192A (VCC-) ≤ VICM ≤
(VCC+),
95
-40 °C < T < 125 °C
TSB7191, TSB7192 (VCC-) ≤ VICM ≤
(VCC+),
90
120
T = 25 °C
TSB7191, TSB7192 (VCC-) ≤ VICM ≤
(VCC+),
85
-40 °C < T < 125 °C
SVR
Power supply rejection
ratio
20 log (∆VCC / ∆VIO)
VOH
VOL
High level output
voltage (drop voltage
from VCC+)
Low level output
voltage
ISINK
IOUT
ISOURCE
ICC
5 V < VCC < 36 V,
VICM = VCC/2
100
125
-40 °C < T < 125 °C
No load, -40 °C < T < 125 °C
120
ISOURCE = 2 mA, -40 °C < T < 125 °C
200
ISOURCE = 15 mA, -40 °C < T < 125 °C
1000
No load , -40 °C < T < 125 °C
120
ISINK = 2 mA, -40 °C < T < 125 °C
200
ISINK = 15 mA , -40 °C < T < 125 °C
1000
VOUT = VCC, T = 25 °C
25
VOUT = VCC, -40 °C < T < 125 °C
20
VOUT = 0 V, T = 25 °C
25
VOUT = 0 V, -40 °C < T < 125 °C
20
Supply current by
No load, T = 25 °C
op-amp
No load, -40 °C < T < 125 °C
mV
50
mA
50
1.8
3
mA
AC performance
GBP
DS12641 - Rev 5
Gain bandwidth
product
RL = 10 kΩ, CL = 100 pF
16
22
MHz
page 5/34
TSB7191, TSB7191A, TSB7192, TSB7192A
Electrical characteristics
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
No sustained oscillations.
Positive gain configuration:
10
Vcc- < Vicm < Vcc+ + 0.1 V,
Astab
Minimum gain for
stability
-40 °C < T < 125 °C
V/V
No sustained oscillations.
Negative gain configuration.
-9
Vcc- < Vicm < Vcc+ + 0.1 V ,
-40 °C < T < 125 °C
9 V step, RL = 10 kΩ,
SR
Slew rate
CL = 100 pF,
AV = 1 V/V, 10% to 90%
VIN = 0.1 Vrms , RL = 10 kΩ, AV = +1,
THD+N
Total harmonic
distorsion + noise
f = 1 kHz, BW = 22 kHz
VIN = 0.1 Vrms , RL = 1 kΩ, AV = +1,
f = 1 kHz, BW = 22 kHz
VOUT = 5 Vpp, f = 1 kHz, AV = +11,
CR
Crosstalk
RL = 10 kΩ
VOUT = 5Vpp, f = 10 kHz, AV = +11,
RL = 10 kΩ
Φm
CLOAD
en
Phase margin
At gain= +10, 25 °C, 10 kΩ, 100 pF
Capacitive load drive
Input voltage noise
density
8.5
12
V/µs
0.0022
%
0.0022
125
dB
100
68
ᵒ
100(5)
pF
f = 10 Hz
20
f = 100 Hz
13
f = 10 kHz
12
0.5
µVPP
0.15(6)
pA/√Hz
en p-p
Input noise voltage
0.1 Hz ≤ f ≤ 10 Hz
in
Input current noise
density
f = 1 kHz
nV/√Hz
1. See Input offset voltage drift over the temperature in application information.
2. Typical value is based on the VIO drift observed after 1000 h at 125 °C extrapolated to 25 °C using the Arrhenius law and
assuming an activation energy of 0.7 eV. The operational amplifier is aged in follower mode configuration. See Long term
input offset voltage drift.
3. Current is positive when it is sinked into the op-amp.
4. Iio is defined as |Iibp – Iibn|
5. For higher capacitive values see Figure 24. Phase margin vs. output current at VCC = 36 V and Figure 25. Phase margin vs.
capacitive load
6. Theoretical value of the input current noise density based on the measurement of the input transistor base current:
in = 2. q.ib
DS12641 - Rev 5
page 6/34
TSB7191, TSB7191A, TSB7192, TSB7192A
Electrical characteristics
Table 6. Electrical characteristics at VCC = 5 V, VICM = VOUT = VCC / 2, Tamb = 25 °C and RL connected to
VCC / 2 (unless otherwise specified)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
DC performance
TSB7191A, TSB7192A, T = 25 °C,
± 350
VCC- ≤ VICM ≤ VCC+ -1.5 V
TSB7191A, TSB7192A, T = 25 °C,
± 650
VCC- ≤ VICM ≤ VCC+
TSB7191A, TSB7192A, -40 °C < T <
125 °C,
± 750
VCC- ≤ VICM ≤ VCC+ -1.5 V
TSB7191A, TSB7192A, -40 °C < T <
125 °C,
Vio
Input offset voltage
± 1050
VCC- ≤ VICM ≤ VCC+
µV
TSB7191, TSB7192, T = 25 °C,
±800
VCC- ≤ VICM ≤ VCC+ -1.5 V
TSB7191, TSB7192, T = 25 °C,
±1200
VCC- ≤ VICM ≤ VCC+
TSB7191, TSB7192, -40 °C < T < 125
°C,
±1100
VCC- ≤ VICM ≤ VCC+ -1.5 V
TSB7191, TSB7192, -40 °C < T < 125
°C,
±1400
VCC- ≤ VICM ≤ VCC+
ΔVio / ΔT
IIB
IIO
DS12641 - Rev 5
Input offset voltage
drift
Input bias current (2)
Input offset current (3)
-40°C < T < 125 °C(1)
4
VICM = VCC+, T = 25 °C
0
300
VICM = VCC+, -40 °C < T < 125 °C
0
900
VICM = VCC-, T = 25 °C
-100
0
VICM = VCC-, -40 °C < T < 125 °C
-200
0
VICM = VCC+
10
VICM = VCC-
10
µV/°C
nA
page 7/34
TSB7191, TSB7191A, TSB7192, TSB7192A
Electrical characteristics
Symbol
Parameter
Conditions
Min.
Typ.
(VCC-) + 0.5 V ≤ VOUT ≤ (VCC+) -0.5 V,
T = 25 °C
105
120
Max.
Unit
RL ≥ 10 kΩ,
AVD
Open loop gain
RL ≥ 10 kΩ,
(VCC-) + 0.5 V ≤ VOUT ≤ (VCC+) -0.5 V,
-40 °C < T < 125 °C
(VCC-) ≤ VICM ≤ ( VCC+) -1.5 V,
T = 25 °C
(VCC-) ≤ VICM ≤ (VCC+) - 1.5 V,
-40 °C < T < 125 °C
TSB7191A,TSB7192A (VCC-) ≤ VICM ≤
(VCC+),
CMR
Common-mode
rejection ratio
20 log (∆VINCM/∆VIO )
100
95
125
90
dB
80
105
T = 25 °C
TSB7191A, TSB7192A (VCC-) ≤ VICM ≤
(VCC+),
75
-40 °C < T < 125 °C
TSB7191, TSB7192 (VCC-) ≤ VICM ≤
(VCC+),
75
105
T = 25 °C
TSB7191, TSB7192 (VCC-) ≤ VICM ≤
(VCC+),
70
-40 °C < T < 125 °C
High level output
voltage (drop voltage
from VCC+)
No load, -40 °C < T < 125 °C
90
VOH
ISOURCE = 2 mA, -40 °C < T < 125 °C
200
VOL
Low level output
voltage
No load, -40 °C < T < 125 °C
90
ISINK = 2 mA, -40 °C < T < 125 °C
200
ISINK
IOUT
ISOURCE
ICC
Supply current by opamp
VOUT = VCC, T = 25 °C
20
VOUT = VCC, -40 °C < T < 125 °C
15
VOUT = 0 V, T = 25 °C
20
VOUT = 0 V, -40 °C < T < 125 °C
15
No load, T = 25 °C
mV
50
mA
50
1.4
No load, -40 °C < T < 125 °C
2.3
mA
AC performance
GBP
Gain bandwidth
product
RL = 10 kΩ, CL = 100 pF
16
22
MHz
No sustained oscillations.
Positive gain configuration:
Astab
Minimum gain for
stability
10
Vcc- < Vicm < Vcc+ + 0.1 V,
-40 °C < T < 125 °C
V/V
No sustained oscillations.
Negative gain configuration.
-9
Vcc- < Vicm < Vcc+ + 0.1 V,
-40 °C < T < 125 °C
DS12641 - Rev 5
page 8/34
TSB7191, TSB7191A, TSB7192, TSB7192A
Electrical characteristics
Symbol
SR
Parameter
Slew rate
Conditions
3 V step, RL = 10 kΩ, CL = 100 pF,
AV = 1 V/V, 10% to 90%
Min.
Typ.
7.5
11
Max.
Unit
V/µs
VIN = 0.1 Vrms , RL = 10 kΩ,
THD+N
Total harmonic
distorsion + noise
AV = +1,
f = 1 kHz, BW = 22 kHz
VIN = 0.1 Vrms , RL = 1 kΩ, AV = +1,
f = 1 kHz, BW = 22 kHz
Φm
CLOAD
en
Phase margin
At gain = +10, 25 °C, 10 kΩ, 100 pF
Capacitive load drive
Input voltage noise
density
0.0022
%
0.0024
63
ᵒ
100(4)
pF
f = 10 Hz
20
f = 100 Hz
13
f = 10 kHz
12
0.8
µVPP
0.15(5)
pA/√Hz
en p-p
Input noise voltage
0.1 Hz ≤ f ≤ 10 Hz
in
Input current noise
density
f = 1 kHz
nV/√Hz
1. See Input offset voltage drift over the temperature in application information.
2. Current is positive when it is sinked into the op-amp.
3. Iio is defined as |Iibp – Iibn|.
4. For higher capacitive values see Figure 23. Phase margin vs. output current at VCC = 5 V and Figure 25. Phase margin vs.
capacitive load
5. Theoretical value of the input current noise density based on the measurement of the input transistor base current:
in = 2. q.ib
DS12641 - Rev 5
page 9/34
TSB7191, TSB7191A, TSB7192, TSB7192A
Typical performance characteristics
4
Typical performance characteristics
RL connected to VCC / 2 (unless otherwise specified).
Figure 3. Supply current vs. supply voltage
Figure 4. Input offset voltage distribution at VCC = 5 V
TSB7191A, TSB7192A
Figure 5. Input offset voltage distribution at VCC = 36 V
TSB7191A, TSB7192A
Figure 6. Input offset voltage vs. temperature at VCC = 5 V
DS12641 - Rev 5
page 10/34
TSB7191, TSB7191A, TSB7192, TSB7192A
Typical performance characteristics
Figure 7. Input offset voltage vs. temperature at
VCC = 36 V
Figure 8. Input offset voltage thermal coefficient
distribution at VCC = 5 V
Figure 9. Input offset voltage vs. supply voltage
Figure 10. Input offset voltage vs. common mode voltage
at VCC = 5 V
Figure 11. Input offset voltage vs. common mode voltage
at VCC = 36 V
Figure 12. Input bias current vs. temperature at
VICM = VCC / 2
DS12641 - Rev 5
page 11/34
TSB7191, TSB7191A, TSB7192, TSB7192A
Typical performance characteristics
Figure 13. Output current vs. output voltage at
VCC = 5 V
Figure 14. Input bias current vs. common mode voltage at
VCC = 5 V
Figure 15. Input bias current vs. common mode voltage at
Figure 16. Output current vs. output voltage at VCC = 36 V
VCC = 36 V
Figure 17. Output voltage (VOH) vs. supply voltage
DS12641 - Rev 5
Figure 18. Output voltage (VOL) vs. supply voltage
page 12/34
TSB7191, TSB7191A, TSB7192, TSB7192A
Typical performance characteristics
Figure 20. Negative slew rate at VCC = 36 V
Figure 21. Bode diagram at VCC = 5 V
Figure 22. Bode diagram at VCC = 36 V
Figure 23. Phase margin vs. output current at VCC = 5 V
Figure 24. Phase margin vs. output current at VCC = 36 V
Phase margin (°)
Phase margin (°)
Figure 19. Positive slew rate at VCC = 36 V
DC output current (mA)
DS12641 - Rev 5
DC output current (mA)
page 13/34
TSB7191, TSB7191A, TSB7192, TSB7192A
Typical performance characteristics
Figure 25. Phase margin vs. capacitive load
Figure 26. Small step response vs. time at VCC = 5 V
Figure 27. Desaturation time at low rail at VCC = 5 V
Figure 28. Desaturation time at high rail at VCC = 5 V
Figure 29. Small step response vs. time at VCC = 36 V
Figure 30. Amplifier behavior close to the low rail at
VCC = 36 V
DS12641 - Rev 5
page 14/34
TSB7191, TSB7191A, TSB7192, TSB7192A
Typical performance characteristics
Figure 31. Amplifier behavior close to the high rail at
VCC = 36 V
Figure 32. Noise vs. frequency at VCC = 5 V
Figure 33. Noise vs. frequency at VCC = 36 V
Figure 34. Noise vs. time at VCC = 36 V
Figure 35. THD+N vs. frequency
Figure 36. THD+N vs. output voltage
DS12641 - Rev 5
page 15/34
TSB7191, TSB7191A, TSB7192, TSB7192A
Typical performance characteristics
Figure 37. PSRR vs. frequency at VCC = 10 V
Figure 38. CMRR vs. frequency at VCC = 10 V
Figure 39. Channel separation vs. frequency at VCC = 36 V
DS12641 - Rev 5
page 16/34
TSB7191, TSB7191A, TSB7192, TSB7192A
Application information
5
Application information
5.1
Operating voltages
The TSB7191, TSB7191A, TSB7192 and TSB7192A devices can operate from 2.7 to 36 V. The parameters are
fully specified at 5 V and 36 V power supplies. However, the parameters are very stable over the full VCC range
and several characterization curves show the TSB7191, TSB7191A, TSB7192 and TSB7192A device
characteristics over the full operating range. Additionally, the main specifications are guaranteed in extended
temperature range from -40 to 125 °C.
5.2
Input pin voltage range
The TSB7191, TSB7191A, TSB7192 and TSB7192A devices have an internal ESD diode protection on the
inputs. These diodes are connected between the inputs and each supply rail to protect the input stage from
electrical discharge, as shown in the figure below.
Figure 40. Input current limitation
Vcc+
In-
100 Ω
D1
In+
100Ω
D2
VCC +
TSB7192
+
Out
Out
VCC -
Vcc-
When the input pin voltage exceeds the power supply, the ESD diodes become conductive and, depending on
this voltage, excessive current can flow through them. Without limitation this overcurrent can damage the device.
In this case, the current has to be limited to 10 mA by adding a resistance in series with the input pin.
Similarly, in order to avoid excessive current in the protection diodes between the positive and negative inputs,
the differential voltage should be limited to ± 2 V, or the current limited to 10 mA. Such a high differential voltage
can be reached when the output is in saturation mode, or slew rate limited. In particular, it can happen when the
device is used in comparator mode.
The TSB7191, TSB7191A, TSB7192 and TSB7192A do not show any phase reversal for any input common
mode voltage inside the absolute maximum ratings (AMR) voltage window, (VCC-) - 200 mV < VICM < (VCC+) +
200 mV.
DS12641 - Rev 5
page 17/34
TSB7191, TSB7191A, TSB7192, TSB7192A
Rail-to-rail input stage
5.3
Rail-to-rail input stage
The TSB7191, TSB7191A, TSB7192 and TSB7192A devices are built with two complementary NPN and PNP
input differential pairs, as shown in the figure below.
Figure 41. Rail-to-rail input stage
V CC
Ip
VIP
Pp
Pn
VIN
[…]
[…]
[…]
Nn
[…]
Np
In
GND
The device has rail-to-rail inputs, and the input common mode range is extended from VCC- to (VCC+) + 0.1 V.
However, the performance of these devices is optimized for the P-channel differential pair (which means from
VCC- to (VCC+) - 1.5 V). Around (VCC+) – 1 V, and with slight variations depending on the process, a transition
occurs between the P-channel and the N-channel differential pair, impacting the input offset voltage (see
Figure 10. Input offset voltage vs. common mode voltage at VCC = 5 V and Figure 11. Input offset voltage vs.
common mode voltage at VCC = 36 V). As a consequence, CMRR can be degraded around this transition region.
In order to achieve the best possible performance, this operating point should be avoided.
Please also notice that the input bias current polarity depends on the operation of NPN or PNP input stage. This
transition is visible in figures Figure 14. Input bias current vs. common mode voltage at VCC = 5 V and
Figure 15. Input bias current vs. common mode voltage at VCC = 36 V.
5.4
Input offset voltage drift over the temperature
The maximum input voltage drift variation over temperature is defined as the offset variation related to the offset
value measured at 25 °C. The operational amplifier is one of the main circuits of the signal conditioning chain, and
the amplifier input offset is a major contributor to the chain accuracy. The signal chain accuracy at 25 °C can be
compensated during the production at application level. The maximum input voltage drift overtemperature enables
the system designer to anticipate the effect of temperature variations. The maximum input voltage drift
overtemperature is computed using the following formula:
ΔVio
Vio T − Vio 25°C
= max
ΔT
T − 25°C
T = − 40 °C and T = 125 °C
(1)
The datasheet maximum value is guaranteed by a measurement on a representative sample size ensuring a Cpk
(process capability index) greater than 1.3.
DS12641 - Rev 5
page 18/34
TSB7191, TSB7191A, TSB7192, TSB7192A
Long term input offset voltage drift
5.5
Long term input offset voltage drift
To evaluate product reliability, two types of stress acceleration are used:
Voltage acceleration, by changing the applied voltage.
•
•
Temperature acceleration, by changing the die temperature (below the maximum junction temperature
allowed by the technology) with the ambient temperature.
The voltage acceleration has been defined based on JEDEC results, and is defined using:
(2)
AFV = еβ.(VS - VU)
Where:
AFV is the voltage acceleration factor
β is the voltage acceleration coefficient in 1/V, constant technology parameter (β = 1)
VS is the stress voltage used for the accelerated test
VU is the voltage used for the application
The temperature acceleration is driven by the Arrhenius model, and is defined as follows:
(3)
Ea
1
1
AFT = e k . TU − TS .
Where:
AFT is the temperature acceleration factor
Ea is the activation energy of the technology based on the failure rate
k is the Boltzmann constant (8.6173 x 10-5 eV.K-1)
TU is the temperature of the die when VU is used (K)
TS is the temperature of the die under temperature stress (K)
The final acceleration factor, AF, is the multiplication of the voltage acceleration factor and the temperature
acceleration factor.
(4)
AF = AFT . AFV
AF is calculated using the temperature and voltage defined in the mission profile of the product. The AF value can
then be used in Equation 5 to calculate the number of months of use equivalent to 1000 hours of reliable stress
duration.
(5)
Months = AF × 1000 h × 12 months / (24 h × 365.25 days)
To evaluate the op-amp reliability, a follower stress condition is used where VCC is defined as a function of the
maximum operating voltage and the absolute maximum ratings (as recommended by JEDEC rules). Vio drift (in
µV) of the product after 1000 h of stress is tracked with parameters at different measurement conditions.
(6)
VCC = max(VOP) with Vicm = VCC/2
The long term drift parameter ΔVio (in µV.month-1/2), estimating the reliability performance of the product, is
obtained using the ratio of the Vio (input offset voltage value) drift over the square root of the calculated number of
months.
(7)
Viodrift
∆ Vio =
montℎs
Where Vio drift is the measured drift value in the specified test conditions after 1000 h stress duration.
DS12641 - Rev 5
page 19/34
TSB7191, TSB7191A, TSB7192, TSB7192A
EMI rejection
The Vio final drift, in µV, to be measured on the device in real operation conditions can be computed from:
(8)
Ea
1
1
Vio final drift top, Top, VCC = ∆ Vio, 25°C . top . eβ . VCC − VCC nom . e k . 297 − Top
Where:
ΔVio is the long term drift parameter in µV.month-1/2
top is the operating time seen by the device, in months
Top is the operating temperature
VCC is the power supply during operating time
VCC nom is the nominal VCC at which the ΔVio is computed (36 V for the TSB7192A).
Ea is the activation energy of the technology (here 0.7 eV).
5.6
EMI rejection
The electromagnetic interference (EMI) rejection ratio, or EMIRR, describes the EMI immunity of operational
amplifiers. An adverse effect that is common to many op-amps is a change in the offset voltage as a result of RF
signal rectification. EMIRR is defined as follows:
EMIRR = 20.log
Vin pp
ΔVio
(9)
The TSB7191, TSB7191A, TSB7192 and TSB7192A have been specially designed to minimize susceptibility to
EMIRR and shows a low sensitivity. As visible on figure below, EMI rejection ratio has been measured on both
inputs and outputs, from 400 MHz to 2.4 GHz.
Figure 42. EMIRR on In+, In- and out pins
EMIRR performance might be improved by adding small capacitances (in the pF range) on the inputs, power
supply and output pins. These capacitances help in minimizing the impedance of these nodes at high frequencies.
5.7
Minimum gain
The TSB7191 and TSB7192 series is non-compensated op-amp, and thus it is not stable at unity gain. The
minimum gain advised for this family is +10 or -9, for a capacitive load Cload = 100 pF; that guarantees a good
stability at all biases and temperatures. For a lower gain, the TSB712 series must be preferred.
However, a TSB7191 and TSB7192 op-amp can be used in follower mode at low frequency, provided that the
circuit is externally compensated. This can be useful for the second channel, when the TSB7192 frequency or
slew rate performance is needed for the first channel. In this case, the circuit topology described in the figure
below can be used. At low frequency, the circuit behaves as a follower, but at high frequency (>1 MHz), the circuit
is stabilized by attenuating the feedback injected into the negative input.
DS12641 - Rev 5
page 20/34
TSB7191, TSB7191A, TSB7192, TSB7192A
Minimum gain
Figure 43. Proposed circuit configuration for unity gain stability
Figure 44. Small step response vs. time in follower configuration
Figure 45. Small step response vs. time in the proposed compensated circuit configuration
DS12641 - Rev 5
page 21/34
TSB7191, TSB7191A, TSB7192, TSB7192A
Unused channel
5.8
Unused channel
When one of the two channels of the TSB7192 and TSB7192A is not used, it must be properly connected in order
to avoid internal oscillations that can negatively impact the signal integrity on the other channel, as well as the
current consumption. Two different configurations can be used:
•
Gain configuration: the channel can be set in gain at which the stability is guaranteed (+10/-9 or more). The
input can be set to any voltage within the Vicm operating range.
•
5.9
Comparator configuration: the channel can be set to a comparator configuration (without negative feedback).
In this case, positive and negative inputs can be set to any value provided that these values are significantly
different (100 mV or more, to avoid oscillations between positive and negative state) and the differential
input is lower than the maximum specified in the operating range (maximum 2 V), or the input current is
limited to less than 10 mA to avoid damaging the circuit.
Maximum power dissipation
The usable output load current drive is limited by the maximum power dissipation allowed by the device package.
The absolute maximum junction temperature for the TSB7191, TSB7191A, TSB7192 and TSB7192A is 150 °C.
The junction temperature can be estimated as follows:
T J = PD × Rtℎ − ja + TA
TJ is the die junction temperature
(10)
PD is the power dissipated in the package
Rth-ja is the junction to ambient thermal resistance of the package
TA is the ambient temperature
The power dissipated in the package PD is the sum of the quiescent power dissipated and the power dissipated
by the output stage transistor. It is calculated as follows:
PD = VCC × ICC + VCC + − VOUT × ILoad
(11)
PD = VCC × ICC + VOUT − VCC− × ILoad
(12)
when the op-amp sources the current
when the op-amp is sinks the current.
Do not exceed the 150 °C maximum junction temperature for the device. Exceeding the junction temperature limit
can cause degradation in the parametric performance or even destroy the device.
5.10
PCB layout recommendations
Particular attention must be paid to the layout of the PCB tracks connected to the amplifier, load, and power
supply. The power and ground traces are critical as they must provide adequate energy and grounding for all
circuits. The best practice is to use short and wide PCB traces to minimize voltage drops and parasitic
inductance. In addition, to minimize parasitic impedance over the entire surface, a multi-via technique that
connects the bottom and top layer ground planes together in many locations is often used. The copper traces
connecting the output pins to the load and supply pins should be as wide as possible to minimize trace resistance.
5.11
Decoupling capacitor
In order to ensure op-amp full functionality, it is mandatory to place a decoupling capacitor of at least 22 nF as
close as possible to the op-amp supply pin. A good decoupling helps to reduce electromagnetic interference
impact.
DS12641 - Rev 5
page 22/34
TSB7191, TSB7191A, TSB7192, TSB7192A
Typical applications
6
Typical applications
6.1
Low-side current sensing
Power management mechanisms are found in most electronic systems. Current sensing is useful to protect
applications. The low-side current sensing method consists of placing a sense resistor between the load and the
circuit ground. The resulting voltage drop is amplified using the TSB7191 and the TSB7192 (see the following
figure).
Figure 46. Low-side current sensing schematic
C1
Rg1
I
Rf1
In
Rshunt
Rg2
Ip
5V
- +
+ -
Vout
TSB7191
TSB7192
Rf2
Vout can be expressed as follows:
Rg2
Rf1
Rg2.Rf2
Rf1
VOUT = Rsℎunt.I 1 −
. 1−
+ Ip.
− In.Rf1
. 1+
Rg2 + Rf2
Rg1
Rg2 + Rf2
Rg1
Rf1
− Vio. 1 −
Rg1
(13)
Assuming that Rf2 = Rf1 = Rf and Rg2 = Rg1 = Rg, can be simplified in the following manner:
Rf
Rf
VOUT = Rsℎunt.I .
+ Rf.Iio
− Vio. 1 +
Rg
Rg
(14)
The main advantage of using the TSB7191 and the TSB7192 for a low-side current sensing relies on its low Vio,
compared to general purpose operational amplifiers. For the same current and targeted accuracy, the shunt
resistor can be chosen with a lower value, resulting in lower power dissipation, lower drop in the ground path, and
lower cost. Particular attention must be paid to the matching and precision of Rg1, Rg2, Rf1, and Rf2, to maximize
the accuracy of the measurement.
DS12641 - Rev 5
page 23/34
TSB7191, TSB7191A, TSB7192, TSB7192A
Package information
7
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages,
depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product
status are available at: www.st.com. ECOPACK is an ST trademark.
7.1
SOT23-5 package information
Figure 47. SOT23-5 package outline
DS12641 - Rev 5
page 24/34
TSB7191, TSB7191A, TSB7192, TSB7192A
SOT23-5 package information
Table 7. SOT23-5 package mechanical data
Dimensions
Ref.
A
Millimeters
Min.
Typ.
Max.
Min.
Typ.
Max.
0.90
1.20
1.45
0.035
0.047
0.057
A1
DS12641 - Rev 5
Inches
0.15
0.006
A2
0.90
1.05
1.30
0.035
0.041
0.051
B
0.35
0.40
0.50
0.014
0.016
0.020
C
0.09
0.15
0.20
0.004
0.006
0.020
D
2.80
2.90
3.00
0.110
0.114
0.118
D1
1.90
0.075
e
0.95
0.037
E
2.60
2.80
3.00
0.102
0.110
0.118
F
1.50
1.60
1.75
0.059
0.063
0.069
L
0.10
0.35
0.60
0.004
0.014
0.024
K
0°
10°
0°
10°
page 25/34
TSB7191, TSB7191A, TSB7192, TSB7192A
MiniSO8 package information
7.2
MiniSO8 package information
Figure 48. MiniSO8 package outline
Table 8. MiniSO8 mechanical data
Dim.
Millimeters
Min.
Inches
Typ.
A
Min.
Typ.
1.1
A1
0
A2
0.75
b
Max.
0.043
0.15
0
0.95
0.03
0.22
0.4
0.009
0.016
c
0.08
0.23
0.003
0.009
D
2.8
3
3.2
0.11
0.118
0.126
E
4.65
4.9
5.15
0.183
0.193
0.203
E1
2.8
3
3.1
0.11
0.118
0.122
e
L
0.85
0.65
0.4
0.6
0.006
0.033
0.8
0.016
0.024
0.95
0.037
L2
0.25
0.01
ccc
0°
0.037
0.026
L1
k
DS12641 - Rev 5
Max.
8°
0.1
0°
0.031
8°
0.004
page 26/34
TSB7191, TSB7191A, TSB7192, TSB7192A
SO8 package information
7.3
SO8 package information
Figure 49. SO8 package outline
Table 9. SO-8 mechanical data
Dim.
mm
Min.
Inches
Typ.
A
Min.
Typ.
1.75
0.25
Max.
0.069
A1
0.1
A2
1.25
b
0.28
0.48
0.011
0.019
c
0.17
0.23
0.007
0.01
D
4.8
4.9
5
0.189
0.193
0.197
E
5.8
6
6.2
0.228
0.236
0.244
E1
3.8
3.9
4
0.15
0.154
0.157
e
0.004
0.01
0.049
1.27
0.05
h
0.25
0.5
0.01
0.02
L
0.4
1.27
0.016
0.05
L1
k
ccc
DS12641 - Rev 5
Max.
1.04
0
0.04
8°
0.1
1°
8°
0.004
page 27/34
TSB7191, TSB7191A, TSB7192, TSB7192A
Ordering information
8
Ordering information
Table 10. Order code
Order code
TSB7191AILT
TSB7191ILT
TSB7191AIYLT
TSB7191IYLT
Temperature range
-40 °C to +125 °C
-40 °C to +125 °C automotive grade
TSB7192AIST
TSB7192AIDT
TSB7192IDT
-40 °C to +125 °C
Package
Packing
Marking
SOT23-5
K224
SOT23-5
K220
SOT23-5
K226
SOT23-5
K222
MiniSO8
K21A
SO8
SO8
Tape and reel
7192AI
7192I
TSB7192IST
MiniSO8
792S
TSB7192AIYDT
SO8
7192AIY
MiniSO8
792Y
SO8
7192IY
MiniSO8
K21Y
TSB7192AIYST
TSB7192IYDT
TSB7192IYST
-40 °C to 125 °C automotive grade(1)
1. Qualified and characterized according to AEC Q100 and Q003 or equivalent, advanced screening according to AEC Q001
and Q002 or equivalent.
SO8 package for single op-amp may be available for qualification upon customer request. Please contact sales
office for such request.
DFN8 package for dual op-amp may be available for qualification under customer request. Please contact sales
office for such request.
DS12641 - Rev 5
page 28/34
TSB7191, TSB7191A, TSB7192, TSB7192A
Revision history
Table 11. Document revision history
Date
Revision
29-Jun-2018
1
Changes
Initial release.
Added the TSB7192 as root part number; cover page has been updated accordingly.
Updated Section 3 Electrical characteristics, Section 4 Typical performance
26-Sep-2018
2
characteristics, Section 5.1 Operating voltages, Section 5.2 Input pin voltage range,
Section 5.3 Rail-to-rail input stage and Section 5.6 EMI rejection, Section 8 Ordering
information.
Added Section 7.2 SO8 package information.
DS12641 - Rev 5
29-Nov-2018
3
Updated Table 5. Electrical characteristics at VCC = 36 V, VICM = VOUT = VCC / 2,
Tamb = 25 °C and RL connected to VCC / 2 (unless otherwise specified) and Table 6.
Electrical characteristics at VCC = 5 V, VICM = VOUT = VCC / 2, Tamb = 25 °C and RL
connected to VCC / 2 (unless otherwise specified).
17-Jun-2019
4
Added root part numbers TSB7191A and TSB7192A, therefore the whole document has
been updated accordingly.
15-Oct-2019
5
Updated Table 10. Order code.
page 29/34
TSB7191, TSB7191A, TSB7192, TSB7192A
Contents
Contents
1
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
2
Absolute maximum ratings and operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3
Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
4
Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
5
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
6
5.1
Operating voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.2
Input pin voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.3
Rail-to-rail input stage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.4
Input offset voltage drift over the temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.5
Long term input offset voltage drift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.6
EMI rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.7
Minimum gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.8
Unused channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.9
Maximum power dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.10
PCB layout recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.11
Decoupling capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
6.1
7
8
Low-side current sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
7.1
SOT23-5 package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.2
MiniSO8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.3
SO8 package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
DS12641 - Rev 5
page 30/34
TSB7191, TSB7191A, TSB7192, TSB7192A
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Pin description (SOT23-5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin description (MiniSO8/SO8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Electrical characteristics at VCC = 36 V, VICM = VOUT = VCC / 2, Tamb = 25 °C and RL connected to VCC / 2 (unless
otherwise specified) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Electrical characteristics at VCC = 5 V, VICM = VOUT = VCC / 2, Tamb = 25 °C and RL connected to VCC / 2 (unless
otherwise specified) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
SOT23-5 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
MiniSO8 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
SO-8 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Order code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
DS12641 - Rev 5
page 31/34
TSB7191, TSB7191A, TSB7192, TSB7192A
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
Figure 48.
DS12641 - Rev 5
Pin connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply current vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input offset voltage distribution at VCC = 5 V TSB7191A, TSB7192A . . . . . . . . .
Input offset voltage distribution at VCC = 36 V TSB7191A, TSB7192A . . . . . . . .
Input offset voltage vs. temperature at VCC = 5 V . . . . . . . . . . . . . . . . . . . . . .
Input offset voltage vs. temperature at VCC = 36 V . . . . . . . . . . . . . . . . . . . . .
Input offset voltage thermal coefficient distribution at VCC = 5 V . . . . . . . . . . . .
Input offset voltage vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input offset voltage vs. common mode voltage at VCC = 5 V . . . . . . . . . . . . . . .
Input offset voltage vs. common mode voltage at VCC = 36 V . . . . . . . . . . . . . .
Input bias current vs. temperature at VICM = VCC / 2 . . . . . . . . . . . . . . . . . . . .
Output current vs. output voltage at
VCC = 5 V . . . . . . . . . . . . . . . . . .
Input bias current vs. common mode voltage at VCC = 5 V . . . . . . . . . . . . . . . .
Input bias current vs. common mode voltage at VCC = 36 V . . . . . . . . . . . . . . .
Output current vs. output voltage at VCC = 36 V . . . . . . . . . . . . . . . . . . . . . . .
Output voltage (VOH) vs. supply voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage (VOL) vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Positive slew rate at VCC = 36 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Negative slew rate at VCC = 36 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bode diagram at VCC = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bode diagram at VCC = 36 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Phase margin vs. output current at VCC = 5 V . . . . . . . . . . . . . . . . . . . . . . . . .
Phase margin vs. output current at VCC = 36 V . . . . . . . . . . . . . . . . . . . . . . . .
Phase margin vs. capacitive load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Small step response vs. time at VCC = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . .
Desaturation time at low rail at VCC = 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Desaturation time at high rail at VCC = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . .
Small step response vs. time at VCC = 36 V . . . . . . . . . . . . . . . . . . . . . . . . . .
Amplifier behavior close to the low rail at VCC = 36 V . . . . . . . . . . . . . . . . . . . .
Amplifier behavior close to the high rail at VCC = 36 V . . . . . . . . . . . . . . . . . . .
Noise vs. frequency at VCC = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Noise vs. frequency at VCC = 36 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Noise vs. time at VCC = 36 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
THD+N vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
THD+N vs. output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PSRR vs. frequency at VCC = 10 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CMRR vs. frequency at VCC = 10 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Channel separation vs. frequency at VCC = 36 V . . . . . . . . . . . . . . . . . . . . . . .
Input current limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Rail-to-rail input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EMIRR on In+, In- and out pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Proposed circuit configuration for unity gain stability . . . . . . . . . . . . . . . . . . . .
Small step response vs. time in follower configuration . . . . . . . . . . . . . . . . . . .
Small step response vs. time in the proposed compensated circuit configuration .
Low-side current sensing schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SOT23-5 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MiniSO8 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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page 32/34
TSB7191, TSB7191A, TSB7192, TSB7192A
List of figures
Figure 49.
DS12641 - Rev 5
SO8 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
page 33/34
TSB7191, TSB7191A, TSB7192, TSB7192A
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST
products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST
products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of
Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. For additional information about ST trademarks, please refer to www.st.com/trademarks. All other product or service
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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2019 STMicroelectronics – All rights reserved
DS12641 - Rev 5
page 34/34
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