TSM103AIDT

TSM103/A DUAL OPERATIONAL AMPLIFIER AND VOLTAGE REFERENCE NOT FOR NEW DESIGN - REPLACED BY TSM103W OPERATIONAL AMPLIFIER ■ LOW INPUT OFFSET VOLTAGE : 0.5mV typ.for TSM103A ■ LOW SUPPLY CURRENT : 350µA/op. ) s t( (@ V CC = 5V) ■ MEDIUM BANDWIDTH (unity gain) : 0.9MHz ■ LARGE OUTPUT VOLTAGE SWING : 0V to c u d (VCC - 1.5V) ■ INPUT COMMON MODE VOLTAGE RANGE ±1.5 TO ±16V e t le VOLTAGE REFERENCE ■ FIXED OUTPUT VOLTAGE REFERENCE 2.5V ■ 0.4% AND 1% VOLTAGE PRECISION ■ SINK CURRENT CAPABILITY : 1 to 100mA ■ TYPICAL OUTPUT IMPEDANCE : 0.2Ω s ( t c The TSM103 is a monolithic IC that includes one independent op-amp and another op-amp for which the non inverting input is wired to a 2.5V fixed Voltage Reference. This device is offering space and cost saving in many applications like power supply management or data acquisition systems. u d o Pr Part Number O TSM103I/AI Output 1 1 OP1 OP2 Inverting Input 1 2 Non-inverting Input 1 3 V - 4 CC ORDER CODE o s b o s b PIN CONNECTIONS (top view) O ) DESCRIPTION e t e l o r P D SO8 (Plastic Micropackage) INCLUDES GROUND ■ WIDE POWER SUPPLY RANGE : 3 to 32V - + VRef 8 VCC+ 7 Output 2 6 Inverting Input 2 + - 5 Non-inverting Input 2 Package Temperature Range D -40°C, +105°C • D = Small Outline Package (SO) - also available in Tape & Reel (DT) January 2003 1/9 TSM103/A ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit VCC Supply Voltage 36 V Vid Differential Input Voltage 36 V Vi Input Voltage -03. to +36 V Operating Free-air Temperature Range Toper Tj Rthja -55 to +125 °C Maximum Junction Temperature 150 °C Thermal Resistance Junction to Ambient (SO package) 175 °C/W ELECTRICAL CHARACTERISTICS Symbol ICC Parameter Min. Total Supply Current, excluding Current in the Voltage Reference VCC+ = 5V, no load Tmin. < Tamb < Tmax. VCC+ = 30V, no load Tmin. < Tamb < Tmax u d o r P e t e l o s b O 2/9 c u d b O - ro P e et ) s t( Max. 1.2 0.7 l o s ) s ( ct Typ. 2 Unit mA TSM103/A OPERATOR 2 (independent op-amp) VCC+ = +5V, VCC = Ground, V o = 1.4V,T amb = 25°C (unless otherwise specified) Symbol Vio Parameter Min. Input Offset Voltage TSM103, Tamb = 25°C Tmin. ≤ Tamb ≤ Tmax. TSM103A, Tamb = 25°C Tmin. ≤ Tamb ≤ Tmax. Max. 1 4 5 2 3 0.5 µV/°C Input Offset Voltage Drift 7 Input Offset Current Tmin. ≤ Tamb ≤ Tmax. 2 30 50 Iib Input Bias Current Tmin. ≤ Tamb ≤ Tmax 20 150 200 Avd SVR Vicm Large Signal Voltage Gain VCC = 15V, RL = 2k, Vo = 1.4V to 11.4V Tmin. ≤ Tamb ≤ Tmax. 50 25 Supply Voltage Rejection Ratio VCC = 5V to 30V 65 Input Common Mode Voltage Range VCC = +30V - see note 1) Tmin. ≤ Tamb ≤ Tmax. CMR Common Mode Rejection Ratio Tmin. ≤ Tamb ≤ Tmax. Isource Output Current Source VCC = +15V, Vo = 2V, Vid = +1V Io Isink VOH Short Circuit to Ground VCC = +15V du High Level Output Voltage VCC+ = 30V Tamb = 25°C, RL = 10k Tmin. ≤ Tamb ≤ Tmax. e t e ol VOL )- s ( t c Output Current Sink Vid = -1V, VCC = +15V, Vo = 2V o r P so Ob GBP THD 100 ) s ( nA V/mV dB 100 70 60 85 20 40 (VCC+) -1.5 V (VCC+) -2 dB mA mA 40 60 mA 10 20 V 27 27 28 Low Level Output Voltage mV 5 Slew Rate at Unity Gain Vi = 0.5 to 3V, VCC = 15V RL = 2k, CL = 100pF, unity gain 0.2 0.4 Gain Bandwidth Product VCC = 30V,RL = 2k, CL = 100pF f = 100kHz, Vin = 10mV 0.5 0.9 Total Harmonic Distortion f = 1kHz AV = 20dB,RL = 2k, VCC = 30V CL = 100pF, Vo = 2Vpp nA ct u d o r P e let 0 0 RL = 10k Tmin. ≤ Tamb ≤ Tmax. SR Unit mV Iio DVio s b O Typ. 20 20 V/µs MHz % 0.02 1. The input common-mode voltage of either input signal voltage should not be allowed to go negative by more than 0.3V. The upper end of the common-mode voltage range is VCC+ - 1.5V. But either of both inputs can go to +36V without damage. 3/9 TSM103/A OPERATOR 1 (op-amp with non-inverting input connected to the internal Vref) VCC+ = +5V, VCC- = Ground, Tamb = 25°C (unless otherwise specified) Symbol Vio Parameter Input Offset Voltage Vicm = 0V TSM103, Tamb = 25°C Tmin. ≤ Tamb ≤ Tmax. TSM103A, Tamb = 25°C Tmin. ≤ Tamb ≤ Tmax. DVio Iib Avd SVR Isource o s b GBP THD e t e )- t(s s b O 20 o r P P e V/mV dB mA 40 mA 40 60 mA 10 20 V 27 27 28 mV 5 RL = 10k Tmin. ≤ Tamb ≤ Tmax. Slew Rate at Unity Gain Vi = 0.5 to 2V, VCC = 15V RL = 2k, CL = 100pF, unity gain 0.2 0.4 Gain Bandwidth Product VCC = 30V,RL = 2k, CL = 100pF f = 100kHz, Vin = 10mV 0.5 0.9 Total Harmonic Distortion f = 1kHz AV = 20dB,RL = 2k, VCC = 30V CL = 100pF, Vo = 2Vpp nA 100 Low Level Output Voltage let 4/9 65 ol uc c u d 100 Output Current Source Vo = 2V VCC = +15V, Vid = +1V High Level Output Voltage VCC+ = 30V Tamb = 25°C, RL = 10k Tmin. ≤ Tamb ≤ Tmax. ) s t( 20 Supply Voltage Rejection Ratio Vicm = 0V VCC+ = 5V to 30V VOH SR µV/°C 7 Output Current Sink Vid = -1V, VCC = +15V, Vo = 2V Unit 4 5 2 3 0.5 Input Bias Current negative input Large Signal Voltage Gain Vicm = 0V VCC = 15V, RL = 2k d o r Max. 1 Input Offset Voltage Drift Isink VOL Typ. mV Short Circuit to Ground VCC = +15V Io O Min. 20 20 V/µs MHz % 0.02 TSM103/A VOLTAGE REFERENCE Symbol Ik Parameter Cathode Current Symbol Vref ∆Vref Imin |ZKA| Parameter Reference Input Voltage TSM103, Tamb = 25°C Tmin. ≤ Tamb ≤ Tmax. TSM103A, Tamb = 25°C Tmin. ≤ Tamb ≤ Tmax. Value Unit 1 to 100 mA Min. Typ. Max. 2.475 2.45 2.49 2.48 2.5 2.525 2.55 2.51 2.52 Unit V 2.5 mV Reference Input Voltage Deviation Over Temperature Range VKA = Vref; Ik = 10mA Tmin. ≤ Tamb ≤ Tmax. Minimum Cathode Current for Regulation VKA = Vref 7 0.5 uc od 0.2 Dynamic Impedance - note 1) VKA = Vref, ∆IK = 1 to 100mA, f < 1kHz r P e 1. The dynamic impedance is defined as [Z KA| = ∆VKA/∆IK ) s t( 30 1 0.5 mA Ω t e l o ) (s s b O t c u d o r P e t e l o s b O 5/9 TSM103/A OPERATIONAL AMPLIFIERS Unit Frequency = F(I) Vcc=+/-15V, RL=2k, CL=100pF 1000 Unit Freq Thousands 800 600 400 ) s t( 200 c u d 0 -0.01 -0.005 0 source sink e t le GBP = F(I) 0.01 0.015 o r P Vcc=+/-15V, RL=2k, CL=100pF o s b 800 O ) Thousands GBP 700 600 500 400 s ( t c 300 200 u d o 100 0 bs Phase Margin (deg) O -0.01 -0.005 0 source sink 0.01 -14 0.015 Gain Margin (dB) e t e ol Pr TSM103/A Total Harmonic Distorsion THD = F(freq) 0.014 0.013 0.012 THD(%) 0.011 0.01 0.009 0.008 0.007 ) s t( 0.006 0.005 10 100 1000 10000 c u d Frequency (Hz) Noise = F(frequency) e t le 70 o s b Noise(nV/SQR(Hz)) 60 50 O ) 40 30 s ( t c 20 10 0 0.01 u d o 0.1 r P e 1 10 100 Frequency (Hz) Vio Distribution - Operator 1 Vcc+=5V, Vcc-=0V 70 60 Distribution (%) s b O t e l o o r P 50 40 30 20 10 0 -3 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 2.5 3 Vio (mV) 7/9 TSM103/A Vio Distribution - Operator 2 Vcc+=5V, Vcc-=0V 70 Distribution (%) 60 50 40 30 20 ) s t( 10 0 -3 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 e t le 3 Vref (V) O ) 2 1.5 s ( t c 1 u d o 0.5 0.0002 r P e 0.002 0.02 0.2 Cathode Current Ik (Amps) Vref Stability = f(I,C) 0.06 0.05 Current (Amps) s b O o r P o s b 2.5 t e l o 3 c u d Vio (mV) Vref = F(Ik) 2.5 Stable 0.04 0.03 Unstable 0.02 0.01 0 1E-10 1E-9 1E-8 1E-7 Capacitor(F) 8/9 1E-6 1E-5 TSM103/A PACKAGE MECHANICAL DATA 8 PINS - PLASTIC MICROPACKAGE (SO) ) s t( c u d e t le Millimeters Dim. Min. A a1 a2 a3 b b1 C c1 D E e e3 F L M S Max. 0.1 0.65 0.35 0.19 0.25 s ( t c u d o 3.8 0.4 o s b 1.75 0.25 1.65 0.85 0.48 0.25 0.5 O ) 4.8 5.8 r P e t e l o s b O Typ. Min. o r P Inches Typ. Max. 0.026 0.014 0.007 0.010 0.069 0.010 0.065 0.033 0.019 0.010 0.020 0.189 0.228 0.197 0.244 0.004 45° (typ.) 5.0 6.2 1.27 3.81 0.050 0.150 4.0 1.27 0.6 0.150 0.016 0.157 0.050 0.024 8° (max.) Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics © 2003 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom http://www.st.com 9/9