UPSD3254A-40

µPSD325X Flash Programmable System Devices with 8032 Microcontroller Core and 256Kbit SRAM FEATURES SUMMARY s The µPSD325X devices combine a Flash PSD architecture with an 8032 microcontroller core. The µPSD325X devices of Flash PSDs feature dual banks of Flash memory, SRAM, general purpose I/O and programmable logic, supervisory functions and access via USB, I2C, ADC, DDC and PWM channels, and an on-board 8032 microcontroller core, with two UARTs, three 16-bit Timer/Counters and two External Interrupts. As with other Flash PSD families, the µPSD325X devices are also in-system programmable (ISP) via a JTAG ISP interface. s Large 32KByte SRAM with battery back-up option s Figure 1. 52-lead, Thin, Quad, Flat Package TQFP52 (T) Dual bank Flash memories – 128KByte or 256KByte main Flash memory – 32KByte secondary Flash memory s Content Security – Block access to Flash memory Programmable Decode PLD for flexible address mapping of all memories within 8032 space. High-speed clock standard 8032 core (12-cycle) USB Interface (some devices only) I2C interface for peripheral connections 5 Pulse Width Modulator (PWM) channels Analog-to-Digital Converter (ADC) Standalone Display Data Channel (DDC) Six I/O ports with up to 50 I/O pins 3000 gate PLD with 16 macrocells Supervisor functions with Watchdog Timer In-System Programming (ISP) via JTAG Zero-Power Technology Single Supply Voltage – 4.5 to 5.5V – 3.0 to 3.6V Figure 2. 80-lead, Thin, Quad, Flat Package s s s s s s s s s s s s s TQFP80 (U) November 2002 1/176 µPSD325X DEVICES TABLE OF CONTENTS SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 µPSD325X Devices Product Matrix (Table 1.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 TQFP52 Connections (Figure 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 TQFP80 Connections (Figure 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 80-Pin Package Pin Description (Table 2.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 52 PIN PACKAGE I/O PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 ARCHITECTURE OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Memory Map and Address Space (Figure 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8032 MCU Registers (Figure 6.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Configuration of BA 16-bit Registers (Figure 7.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Stack Pointer (Figure 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 PSW (Program Status Word) Register (Figure 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Interrupt Location of Program Memory (Figure 10.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 XRAM-DDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 XRAM-PSD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 SFR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 RAM Address (Table 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Addressing Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Direct Addressing (Figure 11.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Indirect Addressing (Figure 12.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Indexed Addressing (Figure 13.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Arithmetic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Arithmetic Instructions (Table 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Logical Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Logical Instructions (Table 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Data Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Data Transfer Instructions that Access Internal Data Memory Space (Table 6.) . . . . . . . . . . . . . . 24 Shifting a BCD Number Two Digits to the Right (using direct MOVs: 14 bytes) (Table 7.) . . . . . . . 25 Shifting a BCD Number Two Digits to the Right (using direct XCHs: 9 bytes) (Table 8.) . . . . . . . . 25 Shifting a BCD Number One Digit to the Right (Table 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Data Transfer Instruction that Access External Data Memory Space (Table 10.) . . . . . . . . . . . . . . 26 Lookup Table READ Instruction (Table 11.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Boolean Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Boolean Instructions (Table 12.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Relative Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2/176 µPSD325X DEVICES Jump Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Unconditional Jump Instructions (Table 13.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Machine Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Conditional Jump Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 State Sequence in µPSD325X Devices (Figure 14.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 µPSD325X HARDWARE DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 µPSD325X devices Functional Modules (Figure 15.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 MCU MODULE DISCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Special Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 SFR Memory Map (Table 15.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 List of all SFR (Table 16.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 PSD Module Register Address Offset (Table 17.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 INTERRUPT SYSTEM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 External Int0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Timer 0 and 1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Timer 2 Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 I2C Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 External Int1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 DDC Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 USB Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 USART Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Interrupt System (Figure 16.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 SFR Register (Table 18.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Interrupt Priority Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Interrupts Enable Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Priority Levels (Table 19.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Description of the IE Bits (Table 20.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Description of the IEA Bits (Table 21.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Description of the IP Bits (Table 22.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Description of the IPA Bits (Table 23.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 How Interrupts are Handled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Vector Addresses (Table 24.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 POWER-SAVING MODE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Power-Saving Mode Power Consumption (Table 25.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Power Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Pin Status During Idle and Power-down Mode (Table 26.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Description of the PCON Bits (Table 27.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3/176 µPSD325X DEVICES I/O PORTS (MCU Module) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 I/O Port Functions (Table 28.) . . . . . . . . . . . . . . . . . P1SFS (91H) (Table 29.) . . . . . . . . . . . . . . . . . . . . . P3SFS (93H) (Table 30.) . . . . . . . . . . . . . . . . . . . . . P4SFS (94H) (Table 31.) . . . . . . . . . . . . . . . . . . . . . PORT Type and Description . . . . . . . . . . . . . . . . . . PORT Type and Description (Part 1) (Figure 17.) . . PORT Type and Description (Part 2) (Figure 18.) . . ....... ....... ....... ....... ....... ....... ....... ...... ...... ...... ...... ...... ...... ...... ....... ....... ....... ....... ....... ....... ....... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... . . . . 46 . . . . 46 . . . . 46 . . . . 46 . . . . 47 . . . . 47 . . . . 48 OSCILLATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Oscillator (Figure 19.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 SUPERVISORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 RESET Configuration (Figure 20.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Low VDD Voltage Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Watchdog Timer Overflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 USB Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 WATCHDOG TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Watchdog Timer Key Register (WDKEY: 0AEH) (Table 32.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Description of the WDKEY Bits (Table 33.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 RESET Pulse Width (Figure 21.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Watchdog Timer Clear Register (WDRST: 0A6H) (Table 34.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Description of the WDRST Bits (Table 35.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 TIMER/COUNTERS (TIMER0, TIMER1 AND TIMER2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Timer0 and Timer1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Control Register (TCON) (Table 36.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Description of the TCON Bits (Table 37.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 TMOD Register (TMOD) (Table 38.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Description of the TMOD Bits (Table 39.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Timer/Counter Mode 0: 13-bit Counter (Figure 22.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Timer/Counter Mode 2: 8-bit Auto-reload (Figure 23.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Timer/Counter Mode 3: Two 8-bit Counters (Figure 24.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Timer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Timer/Counter 2 Control Register (T2CON) (Table 40.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Description of the T2CON Bits (Table 41.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Timer/Counter2 Operating Modes (Table 42.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Timer 2 in Capture Mode (Figure 25.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Timer 2 in Auto-Reload Mode (Figure 26.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4/176 µPSD325X DEVICES STANDARD SERIAL INTERFACE (UART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Multiprocessor Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Serial Port Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Serial Port Control Register (SCON) (Table 43.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Description of the SCON Bits (Table 44.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Timer 1-Generated Commonly Used Baud Rates (Table 45.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Serial Port Mode 0, Block Diagram (Figure 27.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Serial Port Mode 0, Waveforms (Figure 28.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Serial Port Mode 1, Block Diagram (Figure 29.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Serial Port Mode 1, Waveforms (Figure 30.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Serial Port Mode 2, Block Diagram (Figure 31.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Serial Port Mode 2, Waveforms (Figure 32.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Serial Port Mode 3, Block Diagram (Figure 33.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Serial Port Mode 3, Waveforms (Figure 34.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 ANALOG-TO-DIGITAL CONVERTOR (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 ADC Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 A/D Block Diagram (Figure 35.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 ADC SFR Memory Map (Table 46.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Description of the ACON Bits (Table 47.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 ADC Clock Input (Table 48.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 PULSE WIDTH MODULATION (PWM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 4-channel PWM unit (PWM 0-3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Four-Channel 8-bit PWM Block Diagram (Figure 36.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 PWM SFR Memory Map (Table 49.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Programmable Period 8-bit PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Programmable PWM 4 Channel Block Diagram (Figure 37.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 PWM 4 Channel Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 PWM 4 With Programmable Pulse Width and Frequency (Figure 38.) . . . . . . . . . . . . . . . . . . . . . . 76 I2C INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Block Diagram of the I2C Bus Serial I/O (Figure 39.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Serial Control Register (SxCON: S1CON, S2CON) (Table 50.) . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Description of the SxCON Bits (Table 51.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Selection of the Serial Clock Frequency SCL in Master Mode (Table 52.) . . . . . . . . . . . . . . . . . . . 78 Serial Status Register (SxSTA: S1STA, S2STA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Data Shift Register (SxDAT: S1DAT, S2DAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Serial Status Register (SxSTA) (Table 53.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Description of the SxSTA Bits (Table 54.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Data Shift Register (SxDAT: S1DAT, S2DAT) (Table 55.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Address Register (SxADR: S1ADR, S2ADR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Address Register (SxADR) (Table 56.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Start /Stop Hold Time Detection Register (S1SETUP, S2SETUP) (Table 57.) . . . . . . . . . . . . . . . . 80 System Cock of 40MHz (Table 58.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 System Clock Setup Examples (Table 59.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Programmer’s Guide for I2C and DDC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 5/176 µPSD325X DEVICES DDC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 DDC Interface Block Diagram (Figure 40.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Special Function Register for the DDC Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 DDC SFR Memory Map (Table 60.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Description of the DDCON Register Bits (Table 61.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 SWNEB Bit Function (Table 62.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Host Type Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Host Type Detection (Figure 41.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 DDC1 Protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Transmission Protocol in the DDC1 Interface (Figure 42.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 DDC2B Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Conceptual Structure of the DDC Interface (Figure 43.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 USB HARDWARE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 USB related registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 USB Address Register (UADR: 0EEh) (Table 63.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Description of the UADR Bits (Table 64.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 USB Interrupt Enable Register (UIEN: 0E9h) (Table 65.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Description of the UIEN Bits (Table 66.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 USB Interrupt Status Register (UISTA: 0E8h) (Table 67.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Description of the UISTA Bits (Table 68.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 USB Endpoint0 Transmit Control Register (UCON0: 0EAh) (Table 69.) . . . . . . . . . . . . . . . . . . . . . 93 Description of the UCON0 Bits (Table 70.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 USB Endpoint1 (and 2) Transmit Control Register (UCON1: 0EBh) (Table 71.). . . . . . . . . . . . . . . 94 Description of the UCON1 Bits (Table 72.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 USB Control Register (UCON2: 0ECh) (Table 73.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Description of the UCON2 Bits (Table 74.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 USB Endpoint0 Status Register (USTA: 0EDh) (Table 75.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Description of the USTA Bits (Table 76.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 USB Endpoint0 Data Receive Register (UDR0: 0EFh) (Table 77.) . . . . . . . . . . . . . . . . . . . . . . . . . 95 USB Endpoint0 Data Transmit Register (UDT0: 0E7h) (Table 78.) . . . . . . . . . . . . . . . . . . . . . . . . 95 USB Endpoint1 Data Transmit Register (UDT1: 0E6h) (Table 79.) . . . . . . . . . . . . . . . . . . . . . . . . 95 USB SFR Memory Map (Table 80.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Low Speed Driver Signal Waveforms (Figure 44.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Receiver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Differential Input Sensitivity Over Entire Common Mode Range (Figure 45.) . . . . . . . . . . . . . . . . . 98 External USB Pull-Up Resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 USB Data Signal Timing and Voltage Levels (Figure 46.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Receiver Jitter Tolerance (Figure 47.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Differential to EOP Transition Skew and EOP Width (Figure 48.) . . . . . . . . . . . . . . . . . . . . . . . . . 100 Differential Data Jitter (Figure 49.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Transceiver DC Characteristics (Table 81.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Transceiver AC Characteristics (Table 82.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1 6/176 µPSD325X DEVICES PSD MODULE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 PSD MODULE Block Diagram (Figure 50.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 In-System Programming (ISP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Methods of Programming Different Functional Blocks of the PSD MODULE (Table 83.) . . . . . . . 104 DEVELOPMENT SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 PSDsoft Express Development Tool (Figure 51.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 PSD MODULE REGISTER DESCRIPTION AND ADDRESS OFFSET . . . . . . . . . . . . . . . . . . . . . . . 106 Register Address Offset (Table 84.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 PSD MODULE DETAILED OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 MEMORY BLOCKS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Primary Flash Memory and Secondary Flash memory Description. . . . . . . . . . . . . . . . . . . . . . . . 107 Memory Block Select Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Instructions (Table 85.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Power-down Instruction and Power-up Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 READ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Status Bit (Table 86.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Programming Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Data Polling Flowchart (Figure 52.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Data Toggle Flowchart (Figure 53.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Erasing Flash Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Specific Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Sector Protection/Security Bit Definition – Flash Protection Register (Table 87.) . . . . . . . . . . . . . 115 Sector Protection/Security Bit Definition – Secondary Flash Protection Register (Table 88.) . . . . 115 SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Sector Select and SRAM Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Priority Level of Memory and I/O Components in the PSD MODULE (Figure 54.) . . . . . . . . . . . . 117 VM Register (Table 89.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Separate Space Mode (Figure 55.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Combined Space Mode (Figure 56.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Page Register (Figure 57.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 DPLD and CPLD Inputs (Table 90.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 The Turbo Bit in PSD MODULE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 PLD Diagram (Figure 58.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Decode PLD (DPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 DPLD Logic Array (Figure 59.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Complex PLD (CPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Macrocell and I/O Port (Figure 60.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Output Macrocell Port and Data Bit Assignments (Table 91.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 7/176 µPSD325X DEVICES Product Term Allocator . . . . . . . . . . . . . . . . CPLD Output Macrocell (Figure 61.) . . . . . . Input Macrocells (IMC) . . . . . . . . . . . . . . . . Input Macrocell (Figure 62.). . . . . . . . . . . . . ...... ...... ...... ...... ....... ....... ....... ....... ...... ...... ...... ...... ....... ....... ....... ....... ...... ...... ...... ...... ...... ...... ...... ...... . . . 125 . . . 125 . . . 126 . . . 126 I/O PORTS (PSD MODULE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 General Port Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 General I/O Port Architecture (Figure 63.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Port Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 MCU I/O Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 PLD I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Address Out Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Peripheral I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 JTAG In-System Programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Peripheral I/O Mode (Figure 64.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Port Operating Modes (Table 92.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Port Operating Mode Settings (Table 93.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 I/O Port Latched Address Output Assignments (Table 94.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Port Configuration Registers (PCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Port Configuration Registers (PCR) (Table 95.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Port Pin Direction Control, Output Enable P.T. Not Defined (Table 96.) . . . . . . . . . . . . . . . . . . . . 130 Port Pin Direction Control, Output Enable P.T. Defined (Table 97.) . . . . . . . . . . . . . . . . . . . . . . . 130 Port Direction Assignment Example (Table 98.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Port Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Drive Register Pin Assignment (Table 99.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Ports A and B – Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Port A and Port B Structure (Figure 65.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Port C – Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Port C Structure (Figure 66.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Port D – Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Port D Structure (Figure 67.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 External Chip Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Port D External Chip Select Signals (Figure 68.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 POWER MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 APD Unit (Figure 69.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Enable Power-down Flow Chart (Figure 70.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Power-down Mode’s Effect on Ports (Table 101.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 PLD Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 PSD Chip Select Input (CSI, PD2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Input Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Input Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Power Management Mode Registers PMMR01 (Table 102.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Power Management Mode Registers PMMR21 (Table 103.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 APD Counter Operation (Table 104.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 8/176 µPSD325X DEVICES RESET TIMING AND DEVICE STATUS AT RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Warm RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 I/O Pin, Register and PLD Status at RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Reset of Flash Memory Erase and Program Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Reset (RESET) Timing (Figure 71.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Status During Power-on RESET, Warm RESET and Power-down Mode (Table 105.). . . . . . . . . 141 PROGRAMMING IN-CIRCUIT USING THE JTAG SERIAL INTERFACE . . . . . . . . . . . . . . . . . . . . . 142 Standard JTAG Signals . . . . . . . . . . . . . . . . JTAG Port Signals (Table 106.). . . . . . . . . . JTAG Extensions . . . . . . . . . . . . . . . . . . . . . Security and Flash memory Protection . . . . ...... ...... ...... ...... ....... ....... ....... ....... ...... ...... ...... ...... ....... ....... ....... ....... ...... ...... ...... ...... . . . . . . . . . 142 . . . . . . . . . 142 . . . . . . . . . 142 . . . . . . . . . 142 INITIAL DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 AC/DC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 PLD ICC /Frequency Consumption (5V range) (Figure 72.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 PLD ICC /Frequency Consumption (3V range) (Figure 73.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 PSD MODULE Example, Typ. Power Calculation at VCC = 5.0V (Turbo Mode Off) (Table 107.) . 144 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Absolute Maximum Ratings (Table 108.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Operating Conditions (5V Devices) (Table 109.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Operating Conditions (3V Devices) (Table 110.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 AC Symbols for Timing (Table 111.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Switching Waveforms – Key (Figure 74.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 DC Characteristics (5V Devices) (Table 112.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 DC Characteristics (3V Devices) (Table 113.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 External Program Memory READ Cycle (Figure 75.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 External Program Memory AC Characteristics (with the 5V MCU Module) (Table 114.) . . . . . . . 152 External Program Memory AC Characteristics (with the 3V MCU Module) (Table 115.) . . . . . . . 153 External Clock Drive (with the 5V MCU Module) (Table 116.) . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 External Clock Drive (with the 3V MCU Module) (Table 117.) . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 External Data Memory READ Cycle (Figure 76.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 External Data Memory WRITE Cycle (Figure 77.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 External Data Memory AC Characteristics (with the 5V MCU Module) (Table 118.). . . . . . . . . . . 155 External Data Memory AC Characteristics (with the 3V MCU Module) (Table 119.). . . . . . . . . . . 156 A/D Analog Specification (Table 120.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Input to Output Disable / Enable (Figure 78.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 CPLD Combinatorial Timing (5V Devices) (Table 121.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 CPLD Combinatorial Timing (3V Devices) (Table 122.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Synchronous Clock Mode Timing – PLD (Figure 79.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 CPLD Macrocell Synchronous Clock Mode Timing (5V Devices) (Table 123.) . . . . . . . . . . . . . . . 158 CPLD Macrocell Synchronous Clock Mode Timing (3V Devices) (Table 124.) . . . . . . . . . . . . . . . 159 Asynchronous RESET / Preset (Figure 80.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 9/176 µPSD325X DEVICES Asynchronous Clock Mode Timing (product term clock) (Figure 81.) . . . . . . . . . . . . . . . . . . . . . . 160 CPLD Macrocell Asynchronous Clock Mode Timing (5V Devices) (Table 125.) . . . . . . . . . . . . . . 160 CPLD Macrocell Asynchronous Clock Mode Timing (3V Devices) (Table 126.) . . . . . . . . . . . . . . 161 Input Macrocell Timing (product term clock) (Figure 82.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Input Macrocell Timing (5V Devices) (Table 127.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Input Macrocell Timing (3V Devices) (Table 128.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Program, WRITE and Erase Times (5V Devices) (Table 129.) . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Program, WRITE and Erase Times (3V Devices) (Table 130.) . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Peripheral I/O READ Timing (Figure 83.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Port A Peripheral Data Mode READ Timing (5V Devices) (Table 131.) . . . . . . . . . . . . . . . . . . . . 164 Port A Peripheral Data Mode READ Timing (3V Devices) (Table 132.) . . . . . . . . . . . . . . . . . . . . 164 Peripheral I/O WRITE Timing (Figure 84.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Port A Peripheral Data Mode WRITE Timing (5V Devices) (Table 133.) . . . . . . . . . . . . . . . . . . . 165 Port A Peripheral Data Mode WRITE Timing (3V Devices) (Table 134.) . . . . . . . . . . . . . . . . . . . 165 Reset (RESET) Timing (Figure 85.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 Reset (RESET) Timing (5V Devices) (Table 135.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 Reset (RESET) Timing (3V Devices) (Table 136.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 VSTBYON Definitions Timing (5V Devices) (Table 137.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 VSTBYON Timing (3V Devices) (Table 138.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 ISC Timing (Figure 86.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 ISC Timing (5V Devices) (Table 139.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 ISC Timing (3V Devices) (Table 140.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 MCU Module AC Measurement I/O Waveform (Figure 87.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 PSD MODULE AC Float I/O Waveform (Figure 88.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 External Clock Cycle (Figure 89.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Recommended Oscillator Circuits (Figure 90.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 PSD MODULE AC Measurement I/O Waveform (Figure 91.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 PSD MODULE AC Measurement Load Circuit (Figure 92.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Capacitance (Table 141.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 10/176 µPSD325X DEVICES SUMMARY DESCRIPTION s Dual bank Flash memories – Concurrent operation, read from memory while erasing and writing the other. In-Application Programming (IAP) for remote updates – Large 128KByte or 256KByte main Flash memory for application code, operating systems, or bit maps for graphic user interfaces – Large 32KByte secondary Flash memory divided in small sectors. Eliminate external EEPROM with software EEPROM emulation – Secondary Flash memory is large enough for sophisticated communication protocol (USB) during IAP while continuing critical system tasks s s 4-channel, 8-bit Analog-to-Digital Converter (ADC) with analog supply voltage (VREF) Standalone Display Data Channel (DDC) – For use in monitor, projector, and TV applications – Compliant with VESA standards DDC1 and DDC2B – Eliminate external DDC PROM s s Six I/O ports with up to 50 I/O pins – Multifunction I/O: GPIO, DDC, I2C, PWM, PLD I/O, supervisor, and JTAG – Eliminates need for external latches and logic s 3000 gate PLD with 16 macrocells – Create glue logic, state machines, delays, etc. – Eliminate external PALs, PLDs, and 74HCxx – Simple PSDsoft Express software ...Free Large SRAM with battery back-up option – 32KByte SRAM for RTOS, high-level languages, communication buffers, and stacks s Programmable Decode PLD for flexible address mapping of all memories – Place individual Flash and SRAM sectors on any address boundary – Built-in page register breaks restrictive 8032 limit of 64KByte address space – Special register swaps Flash memory segments between 8032 “program” space and “data” space for efficient In-Application Programming s Supervisor functions – Generates reset upon low voltage or watchdog time-out. Eliminate external supervisor device – RESET Input pin; Reset output via PLD s In-System Programming (ISP) via JTAG – Program entire chip in 10 - 25 seconds with no involvement of 8032 – Allows efficient manufacturing, easy product testing, and Just-In-Time inventory – Eliminate sockets and pre-programmed parts – Program with FlashLINKTM cable and any PC s High-speed clock standard 8032 core (12-cycle) – 40MHz operation at 5V, 24MHz at 3.3V – 2 UARTs with independent baud rate, three 16-bit Timer/Counters and two External Interrupts s Content Security – Programmable Security Bit blocks access of device programmers and readers s USB Interface (some devices only) – Supports USB 1.1 Slow Mode (1.5Mbit/s) – Control endpoint 0 and interrupt endpoints 1 and 2 s Zero-Power Technology – Memories and PLD automatically reach standby current between input changes s I2C interface for peripheral connections – Capable of master or slave operation 5 Pulse Width Modulator (PWM) channels – Four 8-bit PWM units – One 8-bit PWM unit with programmable period s Packages – 52-pin TQFP – 80-pin TQFP: allows access to 8032 address/ data/control signals for connecting to external peripherals s 11/176 µPSD325X DEVICES Table 1. µPSD325X Devices Product Matrix Part No. uPSD 3254 A-40 uPSD 3254 BV-24 uPSD 3253 B-40 uPSD 3253 BV-24 Main Sec. ADC SRAM Macro I/O PWM Timer UART 2 Flash Flash I C Ch. (bit) -Cells Pins Ch. / Ctr Ch. (bit) (bit) 2M 256K 256K 16 41 or 50 5 3 2 1 4 DDC USB VCC MHz Pins yes yes 5V 40 52 or 80 2M 256K 256K 16 50 5 3 2 1 4 yes 3V 24 80 1M 256K 256K 16 41 5 3 2 1 4 yes 5V 40 52 1M 256K 256K 16 41 5 3 2 1 4 yes 3V 24 52 Figure 3. TQFP52 Connections 44 RESET 41 ADC3 40 ADC2 46 VREF 45 GND 52 PB0 51 PB1 50 PB2 49 PB3 48 PB4 47 PB5 43 PB6 42 PB7 PD1 1 PC7 2 PC6 3 PC5 4 USB– 5(1) PC4 6 USB+ 7 VCC 8 GND 9 PC3 10 PC2 11 PC1 12 PC0 13 39 P1.5 / ADC1 38 P1.4 / ADC0 37 P1.3 / TXD1 36 P1.2 / RXD1 35 P1.1 / T2X 34 P1.0 / T2 33 VCC 32 XTAL2 31 XTAL1 30 P3.7 / SCL1 29 P3.6 / SDA1 28 P3.5 / T1 27 P3.4 / T0 P4.7 / PWM4 14 P4.6 / PWM3 15 P4.5 / PWM2 16 P4.4 / PWM1 17 P4.3 / PWM0 18 GND 19 P4.2 / DDC VSYNC 20 P4.1 / DDC SCL 21 P4.0 / DDC SDA 22 P3.0 / RXD 23 P3.1 / TXD 24 P3.2 / EXINT0 25 P3.3 / EXINT1 26 AI05790C Note: 1. Pull-up resistor required on pin 5 (2k Ω for 3V devices, 7.5kΩ for 5V devices) for all 52-pin devices, with or without USB function. 12/176 µPSD325X DEVICES Figure 4. TQFP80 Connections 63 PSEN, CNTL2 79 P3.2 / EXINT0 64 P1.7 / ADC3 61 P1.6 / ADC2 62 WR, CNTL0 65 RD, CNTL1 75 P3.0 / RXD 77 P3.1 / TXD 68 RESET 70 VREF 69 GND 80 PB0 78 PB1 76 PB2 74 PB3 73 PB4 72 PB5 67 PB6 PD2 1 P3.3 /EXINT1 2 PD1 3 PD0, ALE 4 PC7 5 PC6 6 PC5 7 USB- 8(1) PC4 9 USB+ 10 NC 11 VCC 12 GND 13 PC3 14 PC2 15 PC1 16 NC 17 P4.7 / PWM4 18 P4.6 / PWM3 19 PC0 20 66 PB7 71 NC 60 P1.5 / ADC1 59 P1.4 / ADC0 58 P1.3 / TXD1 57 P2.3, A11 56 P1.2 / RXD1 55 P2.2, A10 54 P1.1 / T2X 53 P2.1, A9 52 P1.0 / T2 51 P2.0, A8 50 VCC 49 XTAL2 48 XTAL1 47 P0.7, AD7 46 P3.7 / SCL1 45 P0.6, AD6 44 P3.6 / SDA1 43 P0.5, AD5 42 P3.5 / T1 41 P0.4, AD4 PA7 21 PA6 22 P4.5 / PWM2 23 PA5 24 P4.4 / PWM1 25 PA4 26 P4.3 / PWM0 27 PA3 28 GND 29 P4.2 / DCC VSYNC 30 P4.1 / DDC SCL 31 PA2 32 P4.0 / DDC SDA 33 PA1 34 PA0 35 AD0, P0.0 36 AD1, P0.1 37 AD2, P0.2 38 AD3, P0.3 39 P3.4 / T0 40 AI05791B Note: NC = Not Connected 1. Pull-up resistor required on pin 8 (2k Ω for 3V devices, 7.5kΩ for 5V devices) for all 82-pin devices, with or without USB function. 13/176 µPSD325X DEVICES Table 2. 80-Pin Package Pin Description Port Pin Signal Name AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 T2 T2EX RxD2 TxD2 ADC0 ADC1 ADC2 ADC3 A8 A9 A10 A11 RxD1 TxD1 INTO INT1 T0 T1 SDA1 SCL1 SDA2 SCL2 VSYNC Function Pin No. In/Out Basic 36 37 38 39 41 43 45 47 52 54 56 58 59 60 61 64 51 53 55 57 75 77 79 2 40 42 44 46 33 31 30 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O External Bus Multiplexed Address/Data bus A1/D1 Multiplexed Address/Data bus A0/D0 Multiplexed Address/Data bus A2/D2 Multiplexed Address/Data bus A3/D3 Multiplexed Address/Data bus A4/D4 Multiplexed Address/Data bus A5/D5 Multiplexed Address/Data bus A6/D6 Multiplexed Address/Data bus A7/D7 General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin External Bus, Address A8 External Bus, Address A9 External Bus, Address A10 External Bus, Address A11 General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin UART Receive UART Transmit Interrupt 0 input / timer0 gate control Interrupt 1 input / timer1 gate control Counter 0 input Counter 1 input I2C Bus serial data I/O I2C Bus clock I/O I2C serial data I/O for DDC interface I2C clock I/O for DDC interface VSYNC input for DDC interface Timer 2 Count input Timer 2 Trigger input 2nd UART Receive 2nd UART Transmit ADC Channel 0 input ADC Channel 1 input ADC Channel 2 input ADC Channel 3 input Alternate P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 P2.2 P2.3 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 P4.0 P4.1 P4.2 14/176 µPSD325X DEVICES Signal Name PWM0 PWM1 PWM2 PWM3 PWM4 Function Pin No. In/Out Basic 27 25 23 19 18 I/O I/O I/O I/O I/O General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin USB Pin Pull-up resistor required (2kΩ for 3V devices, 7.5kΩ for 5V devices) for all devices, with or without USB function. USB Pin Reference Voltage input for ADC READ signal, external bus WRITE signal, external bus PSEN signal, external bus Address Latch signal, external bus Active low RESET input Oscillator input pin for system clock Oscillator output pin for system clock General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin 1. 2. 3. 4. PLD Macro-cell outputs PLD inputs Latched Address Out (A0-A7) Peripheral I/O Mode Alternate 8-bit Pulse Width Modulation output 0 8-bit Pulse Width Modulation output 1 8-bit Pulse Width Modulation output 2 8-bit Pulse Width Modulation output 3 Programmable 8-bit Pulse Width modulation output 4 Port Pin P4.3 P4.4 P4.5 P4.6 P4.7 USB- 8 I/O USB+ AVREF RD_ WR_ PSEN_ ALE RESET_ XTAL1 XTAL2 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 10 70 65 62 63 4 68 48 49 35 34 32 28 26 24 22 21 I/O O O O O O I I O I/O I/O I/O I/O I/O I/O I/O I/O 15/176 µPSD325X DEVICES Signal Name Function Pin No. 80 78 76 74 73 72 67 66 TMS TCK VSTBY TSTAT TERR TDI TDO 20 16 15 14 9 7 6 5 CLKIN CSI 3 1 12 50 13 29 69 11 17 71 In/Out Basic I/O I/O I/O I/O I/O I/O I/O I/O I I I/O I/O I/O I O I/O I/O I/O General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin General I/O port pin JTAG pin JTAG pin General I/O port pin General I/O port pin General I/O port pin JTAG pin JTAG pin General I/O port pin General I/O port pin General I/O port pin 1. PLD I/O 2. Clock input to PLD and APD 1. PLD I/O 2. Chip select to PSD Module 1. PLD Macro-cell outputs 2. PLD inputs 3. SRAM stand by voltage input (VSTBY) 4. SRAM battery-on indicator (PC4) 5. JTAG pins are dedicated pins 1. PLD Macro-cell outputs 2. PLD inputs 3. Latched Address Out (A0-A7) Alternate Port Pin PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PD1 PD2 Vcc Vcc GND GND GND NC NC NC 52 PIN PACKAGE I/O PORT The 52-pin package members of the µPSD325X devices have the same port pins as those of the 80-pin package except: s Port 0 (P0.0-P0.7, external address/data bus AD0-AD7) s s s s Port A (PA0-PA7) Port D (PD2) Bus control signal (RD,WR,PSEN,ALE) Pin 5 requires a pull-up resistor (2kΩ for 3V devices, 7.5kΩ for 5V devices) for all devices, with or without USB function. Port 2 (P2.0-P2.3, external address bus A8A11) 16/176 µPSD325X DEVICES ARCHITECTURE OVERVIEW Memory Organization The µPSD325X devices’ standard 8032 Core has separate 64KB address spaces for Program memory and Data Memory. Program memory is where the 8032 executes instructions from. Data memory is used to hold data variables. Flash memory can be mapped in either program or data space. The Flash memory consists of two flash memory blocks: the main Flash (1 or 2Mbit) and the Secondary Flash (256Kbit). Except during flash memory programming or update, Flash memory can only be read, not written to. A Page Register is used to access memory beyond the 64K bytes address space. Refer to the PSD Module for details on mapping of the Flash memory. Figure 5. Memory Map and Address Space MAIN FLASH EXT. RAM The 8032 core has two types of data memory (internal and external) that can be read and written. The internal SRAM consists of 256 bytes, and includes the stack area. The SFR (Special Function Registers) occupies the upper 128 bytes of the internal SRAM, the registers can be accessed by Direct addressing only. There are two separate blocks of external SRAM inside the µPSD325X devices: one 256 bytes block is assigned for DDC data storage. Another 32K bytes resides in the PSD Module that can be mapped to any address space defined by the user. INT. RAM FF SECONDARY FLASH 128KB OR 7F 32KB 256KB Indirect or Direct Addressing Indirect Addressing SFR FFFF Direct Addressing EXT. RAM (DDC) 256B 32KB 0 FF00 Flash Memory Space Internal RAM Space (256 Bytes) External RAM Space (MOVX) AI07422 Registers The 8032 has several registers; these are the Program Counter (PC), Accumulator (A), B Register (B), the Stack Pointer (SP), the Program Status Word (PSW), General purpose registers (R0 to R7), and DPTR (Data Pointer register). Figure 6. 8032 MCU Registers A B SP PCH PCL PSW R0-R7 DPTR(DPH) DPTR(DPL) Accumulator B Register Stack Pointer Program Counter Program Status Word General Purpose Register (Bank0-3) Data Pointer Register AI06636 17/176 µPSD325X DEVICES Accumulator. The Accumulator is the 8-bit general purpose register, used for data operation such as transfer, temporary saving, and conditional tests. The Accumulator can be used as a 16-bit register with B Register as shown below. Figure 7. Configuration of BA 16-bit Registers B B A Two 8-bit Registers can be used as a "BA" 16-bit Registers AI06637 A B Register. The B Register is the 8-bit general purpose register, used for an arithmetic operation such as multiply, division with Accumulator Stack Pointer. The Stack Pointer Register is 8 bits wide. It is incremented before data is stored during PUSH and CALL executions. While the stack may reside anywhere in on-chip RAM, the Stack Pointer is initialized to 07h after reset. This causes the stack to begin at location 08h. Figure 8. Stack Pointer Stack Area (30h-FFh) Bit 15 00h Hardware Fixed Bit 8 Bit 7 SP 00h-FFh Bit 0 SP (Stack Pointer) could be in 00h-FFh AI06638 Program Counter. The Program Counter is a 16bit wide which consists of two 8-bit registers, PCH and PCL. This counter indicates the address of the next instruction to be executed. In RESET state, the program counter has reset routine address (PCH:00h, PCL:00h). Program Status Word. The Program Status Word (PSW) contains several bits that reflect the current state of the CPU and select Internal RAM (00h to 1Fh: Bank0 to Bank3). The PSW is described in Figure 9, page 19. It contains the Carry flag, the Auxiliary carry flag, the Half Carry (for BCD operation), the general purpose flag, the Register bank select flags, the Overflow flag, and Parity flag. [Carry Flag, CY]. This flag stores any carry or not borrow from the ALU of CPU after an arithmetic operation and is also changed by the Shift Instruction or Rotate Instruction. [Auxiliary Carry Flag, AC]. After operation, this is set when there is a carry from Bit 3 of ALU or there is no borrow from Bit 4 of ALU. [Register Bank Select Flags, RS0, RS1]. This flags select one of four bank(00~07H:bank0, 08~0Fh:bank1, 10~17h:bank2, 17~1Fh:bank3) in Internal RAM. [Overflow Flag, OV]. This flag is set to ’1’ when an overflow occurs as the result of an arithmetic operation involving signs. An overflow occurs when the result of an addition or subtraction exceeds +127 (7Fh) or -128 (80h). The CLRV instruction clears the overflow flag. There is no set instruction. When the BIT instruction is executed, Bit 6 of memory is copied to this flag. [Parity Flag, P]. This flag reflect on number of Accumulator’s 1. If number of Accumulator’s 1 is odd, P=0. otherwise P=1. Sum of adding Accumulator’s 1 to P is always even. R0~R7. General purpose 8-bit registers that are locked in the lower portion of internal data area. Data Pointer Register. Data Pointer Register is 16-bit wide which consists of two-8bit registers, DPH and DPL. This register is used as a data pointer for the data transmission with external data memory in the PSD Module. 18/176 µPSD325X DEVICES Figure 9. PSW (Program Status Word) Register MSB PSW Carry Flag Auxillary Carry Flag General Purpose Flag Register Bank Select Flags (to select Bank0-3) CY AC FO RS1 RS0 OV LSB P Reset Value 00h Parity Flag Bit not assigned Overflow Flag AI06639 Program Memory The program memory consists of two Flash memory: 128 KByte (or 256 KByte) Main Flash and 32 KByte of Secondary Flash. The Flash memory can be mapped to any address space as defined by the user in the PSDsoft Tool. It can also be mapped to Data memory space during Flash memory update or programming. After reset, the CPU begins execution from location 0000h. As shown in Figure 10, each interrupt is assigned a fixed location in Program Memory. The interrupt causes the CPU to jump to that location, where it commences execution of the service routine. External Interrupt 0, for example, is assigned to location 0003h. If External Interrupt 0 is going to be used, its service routine must begin at location 0003h. If the interrupt is not going to be used, its service location is available as general purpose Program Memory. The interrupt service locations are spaced at 8byte intervals: 0003h for External Interrupt 0, 000Bh for Timer 0, 0013h for External Interrupt 1, 001Bh for Timer 1 and so forth. If an interrupt service routine is short enough (as is often the case in control applications), it can reside entirely within that 8-byte interval. Longer service routines can use a jump instruction to skip over subsequent interrupt locations, if other interrupts are in use. Data memory The internal data memory is divided into four physically separated blocks: 256 bytes of internal RAM, 128 bytes of Special Function Registers (SFRs) areas, 256 bytes of external RAM (XRAM-DDC) and 32K bytes (XRAM-PSD) in the PSD Module. RAM Four register banks, each 8 registers wide, occupy locations 0 through 31 in the lower RAM area. Only one of these banks may be enabled at a time. The next 16 bytes, locations 32 through 47, contain 128 directly addressable bit locations. The stack depth is only limited by the available internal RAM space of 256 bytes. Figure 10. Interrupt Location of Program Memory Interrupt Location • • • • • 008Bh • • • • 0013h 8 Bytes 000Bh 0003h Reset 0000h AI06640 XRAM-DDC The 256 bytes of XRAM-DDC used to support DDC interface is also available for system usage by indirect addressing through the address pointer DDCADR and data I/O buffer RAMBUF. The address pointer (DDCADR) is equipped with the post increment capability to facilitate the transfer of data in bulk (for details refer to DDC Interface part). However, it is also possible to address the RAM through MOVX command as normally used in the internal RAM extension of 80C51 derivatives. XRAM-DDC FF00 to FFFF is directly addressable as external data memory locations FF00 to FFFF via MOVX-DPTR instruction or via MOVX-Ri instruction. When XRAM-DDC is disabled, the address space FF00 to FFFF can be assigned to other resources. XRAM-PSD The 32K bytes of XRAM-PSD resides in the PSD Module and can be mapped to any address space through the DPLD (Decoding PLD) as defined by the user in PSDsoft Development tool. The XRAMPSD has a battery backup feature that allow the data to be retained in the event of a power lost. The battery is connected to the Port C PC2 pin. This pin must be configured in PSDSoft to be battery back-up. 19/176 µPSD325X DEVICES SFR The SFRs can only be addressed directly in the address range from 80h to FFh. Table 15, page 32 gives an overview of the Special Function Registers. Sixteen address in the SFRs space are bothbyte and bit-addressable. The bit-addressable SFRs are those whose address ends in 0h and 8h. The bit addresses in this area are 80h to FFh. Table 3. RAM Address Byte Address (in Hexadecimal) ↓ FFh 30h msb 2Fh 2Eh 2Dh 2Ch 2Bh 2Ah 29h 28h 27h 26h 25h 24h 23h 22h 21h 20h 1Fh Register Bank 3 18h 17h Register Bank 2 10h 0Fh Register Bank 1 08h 07h Register Bank 0 00h 0 AI06642 Addressing Modes The addressing modes in µPSD325X devices instruction set are as follows s Direct addressing s s s s Indirect addressing Register addressing Register-specific addressing Immediate constants addressing Indexed addressing Byte Address (in Decimal) ↓ 255 48 Bit Address (Hex) lsb 79 71 69 61 59 51 49 41 39 31 29 21 19 11 09 01 78 70 68 60 58 50 48 40 38 30 28 20 18 10 08 00 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 24 23 16 15 8 7 s (1) Direct addressing. In a direct addressing the operand is specified by an 8-bit address field in the instruction. Only internal Data RAM and SFRs (80~FFH RAM) can be directly addressed. Example: mov A, 3EH ; A 50ns) 1EA 1EA 2EA 3EA ... 12EA ... 128EA Required Start/ Stop Hold Time 50ns 50ns 100ns 150ns ... 600ns ... 6000ns Fast Mode I²C Start/Stop hold time specification Note When Bit 7 (enable bit) = 0, the number of sample clock is 1EA (ignore Bit 6 to Bit 0) Table 59. System Clock Setup Examples System Clock 40MHz (fOSC/2 -> 50ns) 30MHz (fOSC/2 -> 66.6ns) 20MHz (fOSC/2 -> 100ns) 8MHz (fOSC/2 -> 250ns) S1SETUP, S2SETUP Register Value 8Bh 89h 86h 83h Number of Sample Clock 12 EA 9 EA 6 EA 3 EA Required Start/Stop Hold Time 600ns 600ns 600ns 750ns 80/176 µPSD325X DEVICES Programmer’s Guide for I 2C and DDC2 The I2C serial I/O and DDC Interface operates in four modes. s Master transmitter s s s Else then write next data to SxDAT**. Go to step3. 6. Wait for interrupt. Write dummy data to SxDAT**. Note: 1. (*) If the master don’t receive the acknowledge from the slave, it generates the STOP condition and returns to the IDLE state. 2. (**) This action should be the last in service routine. Master receiver Slave transmitter Slave receiver Master transmitter mode flow. 1. Read SxSTA. 2. If BBUSY == 1 then go to step1. Else then write slave address to SxDAT and set both ENI and STA, reset AA in SxCON. 3. Wait for interrupt. 4. Read SxSTA. If BLOST == 1 or /ACK_REP == 1* then write dummy data to SxDAT. Go to step1. Else then clear STA. 5. Perform required service routines. If this datum == LAST then set STO in SxCON and write last data to SxDAT**. Go to step 6. Slave transmitter mode flow. 1. Write slave address to SxADR, set AA and ENI in SxCON. 2. Wait for interrupt. 3. Read SxSTA and write the first data to SxDAT*. Reset AA in SxCON. 4. Wait for interrupt. 5. Read SxSTA. If /ACK_REP == 1** then Go to step7. Else then write the next SxDAT*. Go to step5. 6. Write dummy data to SxDAT*. Note: 1. (*) These actions should be the last. 2. (**) If the master want to stop the current data requests, it don’t have to acknowledge to the slave transmitter. 3. If the slave does not receive the acknowledge from the master, it releases the SDA and enters the IDLE state, so if the master is to resume the data requests, it must regenerate the START condition. 81/176 µPSD325X DEVICES Master receiver mode flow. 1. Read SxSTA. 2. If BBUSY == 1 then go to step1. Else then write slave address to SxDAT and set both ENI1 and STA, reset AA in SxCON. 3. Wait for interrupt. 4. Read SxSTA. If BLOST == 1 or /ACK_REP == 1 then write dummy data to SxDAT Go to step1. Else then clear STA and write FFH to SxDAT. Set AA in SxCON. 5. Wait for interrupt. 6. Read SxSTA. If this datum == LAST then reset AA* and read SxDAT**. Go to step7. Else then read SxDAT**. Go to step5. 7. Wait for interrupt. Read SxSTA. Read SxDAT**. Note: 1. (*) If the master want to terminate the current data requests, it don’t have to acknowledge to the slave. 2. (**) This action should be the last. Slave transmitter mode. 1. Write slave address to SxADR, set AA and ENI in SxCON. 2. Wait for interrupt. 3. Read SxSTA and write FFH to SxDAT*. 4. 5. Wait for interrupt. 6. Read SxSTA. If STOP == 1 then Go to step7. Else then read data from SxDAT*. Go to step5. 7. Read dummy data from SxDAT*. Note: 1. (*) This action should be the last. 82/176 µPSD325X DEVICES DDC INTERFACE The basic DDC unit consists of an I2C interface and 256 bytes of SRAM for DDC data storage. The 8032 core is responsible of loading the contents of the SRAM with the DDC data. The DDC unit has the following features: s Supports both DDC1 and DDC2b Modes. s s Supports fully automatic operation of DDC1 and DDC2b Modes DDC operates in Slave Mode only. SW Interrupt Mode available (existing design) s s Features 256 bytes of DDC data - initialized by the 8032 The interface signals for the DDC can be mapped to pins in Port 4. The interface consists of the standard VSYNC (P4.2), SDA (P4.0) and SCL (P4.1) DDC signals. The conceptual block diagram is illustrated in Figure 43. Figure 40. DDC Interface Block Diagram DDC2B/DDC2AB DDC2B+Interface 7 Monitor Address S1ADR0 Monitor Address S1ADR1 1 0 SDA1 S1DAT Arbitration Logic SCL1 Shift Register Bus Clock Generator Internal Bus SICON RAMBUF SISTA DDC1/DDC2 Detection DDC1 Hold Register DDCDAT DDC1 Transmitter RAM Buffer VSYNCEN Address Pointer Initialization Synchronization DDCADR X EX_ SW DAT ENB X DDC1 DDC1 SWH INT EN INT M0 INTR (from SISTA) DDCCON INT AI06628 83/176 µPSD325X DEVICES Special Function Register for the DDC Interface There are eight SFR in the DDC interface: RAMBUF, DDCCON, DDCADR, DDCDAT are DDC registers. S1CON, S1STA, S1DAT, S1ADR are I2C Interface registers, same as the ones described in the standalone I2C bus. DDCDAT Register. DDC1 DATA register for transmission (DDCDAT: 0D5H) s 8-bit READ and WRITE register. s DDCADR Register. Address pointer for DDC interface (DDCADR: 0D6H) s 8-bit READ and WRITE register. s Indicates DATA BYTE to be transmitted in DDC1 protocol. Address pointer with the capability of the post increment. After each access to RAMBUF register (either by software or by hardware DDC1 interface), the content of this register will be increased by one. It’s available both in DDC1, DDC2 (DDC2B, DDC2B+, and DDC2AB) and system operation. Table 60. DDC SFR Memory Map SFR Addr Reg Name Bit Register Name 7 6 5 4 3 2 1 0 Reset Comments Value XX 00 00 — EX_DAT SWENB DDC_AX DDCINT DDC1EN SWHINT M0 00 DDC Ram Buffer DDC Data xmit register Addr pointer register DDC Control Register D4 RAMBUF D5 DDCDAT D6 DDCADR D7 DDCCON 84/176 µPSD325X DEVICES Table 61. Description of the DDCON Register Bits Bit 7 6 Symbol — EX_DAT Reserved 0 = The SRAM has 128 bytes (Default) 1 = The SRAM has 256 bytes Note: This bit is valid for DDC1 & DDC2b Modes 0 = Data is automatically read from SRAM at the current location of DDCADR and sent out via current DDC protocol. (Default) 1 = MCU is interrupted during the current data byte transmission period to load the next byte of data to send out. Note: This bit is valid for DDC1 & DDC2b Modes 0 = Data is automatically read from SRAM at the current location of DDCADR and sent out via current DDC protocol. (Default) 1 = MCU is interrupted during the current data byte transmission period to load the next byte of data to send out. This bit only affects DDC2b Mode Operation: 0 = DDC2b I2C Address is A0/A1 (default) 1 = DDC2b I2C Address is AX. Least 3 significant address bits are ignored. For DDC1 Mode Operation Only: 0 = No DDC1 interrupt 1 = DDC1 Interrupt request. Set by HW and should be cleared by SW interrupt service routine. Note1: This bit is set in the 9th VCLK at DDC1 Enable Mode. (SWENB=1) 0 = DDC1 Mode is disabled – VSYNC is ignored. The DDC unit will still respond to DDC2b requests. –provided I2C enabled.(Default) 1 = DDC1 Mode is enabled. Set by hardware when the DDC unit switches from DDC1 to DDC2b Modes. 0 = No interrupt request. 1 = Switch to DDC2b Mode (Interrupt pending) Set by HW and should be cleared by SW interrupt service routine. Note1: This bit has no connection with SWENB. Current Mode Indication Bit: 0 = Unit is in DDC1 Mode 1 = Unit is in DDC2b Mode Note: When the DDC unit transitions to DDC2b Mode, the DDC unit will stay in DDC2b Mode until the DDC unit is disabled, or the system is reset. Function 5 SWENB 4 DDC_AX 3 DDC1_Int 2 DDC1EN 1 SWHINT 0 Mode 85/176 µPSD325X DEVICES Table 62. SWNEB Bit Function DDC1 or DDC2b Mode Disabled SWENB DDCCON.bit2 = 0 (DDC1 Mode Disable) or S1CON.bit6 = 0 (I2C Mode Disable) In this state, the DDC unit is disabled. The DDC SRAM cannot be accessed by the MCU. No MCU interrupt and no DDC activity will occur. MCU cannot access internal DDC SRAM: DDC SRAM address space is re-assigned to external data space. In this state, the DDC unit is disabled, BUT with SWENB=1, the MCU can access the SRAM. This state is used to load the DDC SRAM with the correct data for automatic modes. No MCU interrupt and no DDC activity will occur. MCU can access DDC SRAM: data space FF00hFFFFh is dedicated to DDC SRAM. DDC1 or DDC2b Mode Enabled DDCCON.bit2 = 1 (DDC1 Mode Enable) or S1CON.bit6 = 1 (I2C Mode Enable) In this state, the DDC is enabled and the unit is in automatic mode. The DDC SRAM cannot be accessed by the MCU – only the DDC unit has access. MCU cannot access internal DDC SRAM: data space FF00h-FFFFh is dedicated to DDC SRAM. In this state, the DDC SRAM can be accessed by the MCU. The DDC unit does not use the DDC SRAM when SWENB=1. Since the DDC unit is in manual mode, the DDC unit generates an MCU interrupt for each byte transferred. The byte transferred is held in the I2C S1DAT SFR register. MCU can access DDC SRAM. 0 1 86/176 µPSD325X DEVICES Host Type Detection The detection procedure conforms to the sequences proposed by VESA Monitor Display Data Channel (DDC) specification. The monitor needs to determine the type of host system: s s DDC1 or OLD type host. DDC2B host (Host is master, monitor is always slave) DDC2B+/DDC2AB(ACCESS.bus) host. s Figure 41. Host Type Detection Power on Communication isidle Is VSYNC present? EDID sent continously using VSYNC as clock Is DDC2 clock present? Stop sending of EDID switch to DDC2 communication mode DDC2 communication is idle. Has a command been received? Is 2B+/A.B command detected? Is it DDC2B command? Is DDC2B+/DDC2AB? Respond to DDC2B command Respond to DDC2B+/ DDC2AB command AI06644 87/176 µPSD325X DEVICES DDC1 Protocol DDC1 is primitive and a point to point interface. The monitor is always put at “Transmit only” mode. In the initialization phase, 9 clock cycles on VCLK pin will be given for the internal synchronization. During this period, the SDA pin will be kept at high impedance state. If DDC1 hardware mode is used, the following procedure is recommended to proceed DDC1 operation. 1. Reset DDC1 enable (by default, DDC1 enable is cleared as LOW after Power-on Reset). 2. Set SWENB as high (the default value is zero.) 3. Depending on the data size of EDID data, set EX_DAT as LOW (128 bytes) or HIGH (256 bytes). 4. By using bulky moving commands (DDCADR, RAMBUF involved) to move the entire EDID data to RAM buffer. 5. Reset SWENB to LOW. 6. Reset DDCADR to 00h. 7. Set DDC1 enable as HIGH. In case SWENB is set as high, interrupt service routine is finished within 133 machine cycle in 40MHz System clock. The maximum V SYNC (VCLK) frequency is 25Khz (40µs). And the 9th clock of VSYNC (VCLK) is interrupt period. So the machine cycle be needed is calculated as below. For example, When 40MHz system clock, 40µs = 133 x (25ns x 12); 133 machine cycle. 12MHz system clock, 40µs = 40 x (83.3ns x 12); 40 machine cycle. 8MHz system clock, 40µs = 26 x (125ns x 12); 26 machine cycle. Note: If EX_DAT equals to LOW, it is meant the lower part is occupied by DDC1 operation and the upper part is still free to the system. Nevertheless, the effect of the post increment just applies to the part related to DDC1 operation. In other words, the system program is still able to address the locations from 128 to 255 in the RAM buffer through MOVX command but without the facility of the post increment. For example, the case of accessing 200 of the RAM Buffer: MOV R0, #200, and MOVX A, @R0 Figure 42. Transmission Protocol in the DDC1 Interface Max=40us SC VCLK DDC1INT DDC1EN SD Hi-Z B B B B B B B B HiZ B 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 tSU(DDC1) t H(VCLK) t L(VCLK) t DOV AI06652 88/176 µPSD325X DEVICES DDC2B Protocol DDC2B is constructed based on the Philips I2C interface. However, in the level of DDC2B, PC host is fixed as the master and the monitor is always regarded as the slave. Both master and slave can be operated as a transmitter or receiver, but the master device determines which mode is activated. In this protocol, address pointer is also used. According to DDC2B specification, A0 (for WRITE Mode) and A1 (for READ Mode) are assigned as the default address of monitors. The reception of the incoming data in WRITE Mode or the updating of the outgoing data in READ Mode should be finished within the specified time limit. If software in the slave’s side cannot react to the master in time, based on I2C protocol, SCL pin can be stretched low to inhibit the further action from the master. The transaction can be proceeded in either byte or burst format. Figure 43. Conceptual Structure of the DDC Interface DDC Interrupt vector address ( 0023H ) Check Mode flag in DDCCON Mode = 1 Mode = 1 Mode = 0 DDC2B/DDC2AB command received SWENB =1 DDC2B/DDC2AB Utilities DDC2B SWENB =1 DDC2B Utilities SWENB =0 DDC1.DDC2B Utilities I2C ServiceRoutines DDC Transmitter (H/W) I2C interface (H/W) AI06645 89/176 µPSD325X DEVICES USB HARDWARE The characteristics of USB hardware are as follows: s Complies with the Universal Serial Bus specification Rev. 1.1 s Integrated SIE (Serial Interface Engine), FIFO memory and transceiver Low speed (1.5Mbit/s) device capability Supports control endpoint0 and interrupt endpoint1 and 2 USB clock input must be 6MHz (requires MCU clock frequency to be 12, 24, or 36MHz). s s s The analog front-end is an on-chip generic USB transceiver. It is designed to allow voltage levels equal to V DD from the standard logic to interface with the physical layer of the Universal Serial Bus. It is capable of receiving and transmitting serial data at low speed (1.5Mb/s). The SIE is the digital-front-end of the USB block. This module recovers the 1.5MHz clock, detects the USB sync word and handles all low-level USB protocols and error checking. The bit-clock recovTable 63. USB Address Register (UADR: 0EEh) 7 USBEN 6 UADD6 5 UADD5 4 UADD4 ery circuit recovers the clock from the incoming USB data stream and is able to track jitter and frequency drift according to the USB specification. The SIE also translates the electrical USB signals into bytes or signals. Depending upon the device USB address and the USB endpoint. Address, the USB data is directed to the correct endpoint on SIE interface. The data transfer of this H/W could be of type control or interrupt. The device’s USB address and the enabling of the endpoints are programmable in the SIE configuration header. USB related registers The USB block is controlled via seven registers in the memory: (UADR, UCON0, UCON1, UCON2, UISTA, UIEN, and USTA). Three memory locations on chip which communicate the USB block are: s USB endpoint0 data transmit register (UDT0) s s USB endpoint0 data receive register (UDR0) USB endpoint1 data transmit register (UDT1) 3 UADD3 2 UADD2 1 UADD1 0 UADD0 Table 64. Description of the UADR Bits Bit Symbol R/W Function USB Function Enable Bit. When USBEN is clear, the USB module will not respond to any tokens from host. RESET clears this bit. Specify the USB address of the device. RESET clears these bits. 7 USBEN R/W 6 to 0 UADD6 to UADD0 R/W 90/176 µPSD325X DEVICES Table 65. USB Interrupt Enable Register (UIEN: 0E9h) 7 SUSPNDI 6 RSTE 5 RSTFIE 4 TXD0IE 3 RXD0IE 2 TXD1IE 1 EOPIE 0 RESUMI Table 66. Description of the UIEN Bits Bit 7 6 5 4 3 2 1 0 Symbol SUSPNDI RSTE RSTFIE TXD0IE RXD0IE TXD1IE EOPIE RESUMI R/W R/W R/W R/W R/W R/W R/W R/W R/W Enable SUSPND interrupt Enable USB Reset; also resets the CPU and PSD Modules when bit is set to ’1.’ Enable RSTF (USB Bus Reset Flag) Interrupt Enable TXD0 interrupt Enable RXD0 interrupt Enable TXD1 interrupt Enable EOP interrupt Enable USB resume interrupt when it is the Suspend Mode Function Table 67. USB Interrupt Status Register (UISTA: 0E8h) 7 SUSPND 6 — 5 RSTF 4 TXD0F 3 RXD0F 2 TXD1F 1 EOPF 0 RESUMF 91/176 µPSD325X DEVICES Table 68. Description of the UISTA Bits Bit Symbol R/W Function USB Suspend Mode Flag. To save power, this bit should be set if a 3ms constant idle state is detected on USB bus. Setting this bit stops the clock to the USB and causes the USB module to enter Suspend Mode. Software must clear this bit after the Resume flag (RESUMF) is set while this Resume interrupt flag is serviced Reserved USB Reset Flag. This bit is set when a valid RESET signal state is detected on the D+ and D- lines. When the RSTE bit in the UIEN Register is set, this reset detection will also generate an internal reset signal to reset the CPU and other peripherals including the USB module. Endpoint0 Data Transmit Flag. This bit is set after the data stored in Endpoint 0 transmit buffers has been sent and an ACK handshake packet from the host is received. Once the next set of data is ready in the transmit buffers, software must clear this flag. To enable the next data packet transmission, TX0E must also be set. If TXD0F Bit is not cleared, a NAK handshake will be returned in the next IN transactions. RESET clears this bit. Endpoint0 Data Receive Flag. This bit is set after the USB module has received a data packet and responded with ACK handshake packet. Software must clear this flag after all of the received data has been read. Software must also set RX0E Bit to one to enable the next data packet reception. If RXD0F Bit is not cleared, a NAK handshake will be returned in the next OUT transaction. RESET clears this bit. Endpoint1 / Endpoint2 Data Transmit Flag. This bit is shared by Endpoints 1 and Endpoints 2. It is set after the data stored in the shared Endpoint 1/ Endpoint 2 transmit buffer has been sent and an ACK handshake packet from the host is received. Once the next set of data is ready in the transmit buffers, software must clear this flag. To enable the next data packet transmission, TX1E must also be set. If TXD1F Bit is not cleared, a NAK handshake will be returned in the next IN transaction. RESET clears this bit. End of Packet Flag. This bit is set when a valid End of Packet sequence is detected on the D+ and D-line. Software must clear this flag. RESET clears this bit. Resume Flag. This bit is set when USB bus activity is detected while the SUSPND Bit is set. Software must clear this flag. RESET clears this bit. 7 SUSPND R/W 6 — — 5 RSTF R 4 TXD0F R/W 3 RXD0F R/W 2 TXD1F R/W 1 EOPF R/W 0 RESUMF R/W 92/176 µPSD325X DEVICES Table 69. USB Endpoint0 Transmit Control Register (UCON0: 0EAh) 7 TSEQ0 6 STALL0 5 TX0E 4 RX0E 3 TP0SIZ3 2 TP0SIZ2 1 TP0SIZ1 0 TP0SIZ0 Table 70. Description of the UCON0 Bits Bit Symbol R/W Function Endpoint0 Data Sequence Bit. (0=DATA0, 1=DATA1) This bit determines which type of data packet (DATA0 or DATA1) will be sent during the next IN transaction. Toggling of this bit must be controlled by software. RESET clears this bit Endpoint0 Force Stall Bit. This bit causes Endpoint 0 to return a STALL handshake when polled by either an IN or OUT token by the USB Host Controller. The USB hardware clears this bit when a SETUP token is received. RESET clears this bit. Endpoint0 Transmit Enable. This bit enables a transmit to occur when the USB Host Controller sends an IN token to Endpoint 0. Software should set this bit when data is ready to be transmitted. It must be cleared by software when no more Endpoint 0 data needs to be transmitted. If this bit is ’0’ or the TXD0F is set, the USB will respond with a NAK handshake to any Endpoint 0 IN tokens. RESET clears this bit. Endpoint0 receive enable. This bit enables a receive to occur when the USB Host Controller sends an OUT token to Endpoint 0. Software should set this bit when data is ready to be received. It must be cleared by software when data cannot be received. If this bit is ’0’ or the RXD0F is set, the USB will respond with a NAK handshake to any Endpoint 0 OUT tokens. RESET clears this bit. The number of transmit data bytes. These bits are cleared by RESET. 7 TSEQ0 R/W 6 STALL0 R/W 5 TX0E R/W 4 RX0E R/W 3 to 0 TP0SIZ3 to TP0SIZ0 R/W 93/176 µPSD325X DEVICES Table 71. USB Endpoint1 (and 2) Transmit Control Register (UCON1: 0EBh) 7 TSEQ1 6 EP12SEL 5 TX1E 4 FRESUM 3 TP1SIZ3 2 TP1SIZ2 1 TP1SIZ1 0 TP1SIZ0 Table 72. Description of the UCON1 Bits Bit Symbol R/W Function Endpoint 1/ Endpoint 2 Transmit Data Packet PID. (0=DATA0, 1=DATA1) This bit determines which type of data packet (DATA0 or DATA1) will be sent during the next IN transaction directed to Endpoint 1 or Endpoint 2. Toggling of this bit must be controlled by software. RESET clears this bit. Endpoint 1/ Endpoint 2 Transmit Selection. (0=Endpoint 1, 1=Endpoint 2) This bit specifies whether the data inside the registers UDT1 are used for Endpoint 1 or Endpoint 2. If all the conditions for a successful Endpoint 2 USB response to a hosts IN token are satisfied (TXD1F=0, TX1E=1, STALL2=0, and EP2E=1) except that the EP12SEL Bit is configured for Endpoint 1, the USB responds with a NAK handshake packet. RESET clears this bit. Endpoint1 / Endpoint2 Transmit Enable. This bit enables a transmit to occur when the USB Host Controller send an IN token to Endpoint 1 or Endpoint 2. The appropriate endpoint enable bit, EP1E or EP2E Bit in the UCON2 register, should also be set. Software should set the TX1E Bit when data is ready to be transmitted. It must be cleared by software when no more data needs to be transmitted. If this bit is ’0’ or TXD1F is set, the USB will respond with a NAK handshake to any Endpoint 1 or Endpoint 2 directed IN token. RESET clears this bit. Force Resume. This bit forces a resume state (“K” on non-idle state) on the USB data lines to initiate a remote wake-up. Software should control the timing of the forced resume to be between 10ms and 15ms. Setting this bit will not cause the RESUMF Bit to set. The number of transmit data bytes. These bits are cleared by RESET. 7 TSEQ1 R/W 6 EP12SEL R/W 5 TX1E R/W 4 FRESUM R/W 3 to 0 TP1SIZ3 to TP1SIZ0 R/W 94/176 µPSD325X DEVICES Table 73. USB Control Register (UCON2: 0ECh) 7 — 6 — 5 — 4 SOUT 3 EP2E 2 EP1E 1 STALL2 0 STALL1 Table 74. Description of the UCON2 Bits Bit 7 to 5 4 3 2 1 0 Symbol — SOUT EP2E EP1E STALL2 STALL1 R/W — R/W R/W R/W R/W R/W Reserved Status out is used to automatically respond to the OUT of a control READ transfer Endpoint2 enable. RESET clears this bit Endpoint1 enable. RESET clears this bit Endpoint2 Force Stall Bit. RESET clears this bit Endpoint1 Force Stall Bit. RESET clears this bit Function Table 75. USB Endpoint0 Status Register (USTA: 0EDh) 7 RSEQ 6 SETUP 5 IN 4 OUT 3 RP0SIZ3 2 RP0SIZ2 1 RP0SIZ1 0 RP0SIZ0 Table 76. Description of the USTA Bits Bit 7 Symbol RSEQ R/W R/W Function Endpoint0 receive data packet PID. (0=DATA0, 1=DATA1) This bit will be compared with the type of data packet last received for Endpoint0 SETUP Token Detect Bit. This bit is set when the received token packet is a SEPUP token, PID = b1101. IN Token Detect Bit. This bit is set when the received token packet is an IN token. OUT Token Detect Bit. This bit is set when the received token packet is an OUT token. The number of data bytes received in a DATA packet 6 5 4 3 to 0 SETUP IN OUT RP0SIZ3 to RP0SIZ0 R R R R Table 77. USB Endpoint0 Data Receive Register (UDR0: 0EFh) 7 UDR0.7 6 UDR0.6 5 UDR0.5 4 UDR0.4 3 UDR0.3 2 UDR0.2 1 UDR0.1 0 UDR0.0 Table 78. USB Endpoint0 Data Transmit Register (UDT0: 0E7h) 7 UDT0.7 6 UDT0.6 5 UDT0.5 4 UDT0.4 3 UDT0.3 2 UDT0.2 1 UDT0.1 0 UDT0.0 Table 79. USB Endpoint1 Data Transmit Register (UDT1: 0E6h) 7 UDT1.7 6 UDT1.6 5 UDT1.5 4 UDT1.4 3 UDT1.3 2 UDT1.2 1 UDT1.1 0 UDT1.0 95/176 µPSD325X DEVICES The USCL 8-bit Prescaler Register for USB is at E1h. The USCL should be loaded with a value that results in a clock rate of 6MHz for the USB using the following formula: USB clock input = (FOSC / 2) / (Prescaler register value +1) Where Fosc is the MCU clock input frequency. Table 80. USB SFR Memory Map SFR Reg Addr Name Bit Register Name 7 6 5 4 3 2 1 0 Reset Comments Value 8-bit Prescaler for USB logic USB Endpt1 Data Xmit USB Endpt0 Data Xmit USB Interrupt Status USB Interrupt Enable USB Endpt0 Xmit Control USB Endpt1 Xmit Control USB Control Register USB Endpt0 Status USB Address Register USB Endpt0 Data Recv Note: USB works ONLY with the MCU Clock frequencies of 12, 24, or 36MHz. The Prescaler values for these frequencies are 0, 1, and 2. E1 USCL 00 E6 E7 UDT1 UDT0 UDT1.7 UDT0.7 UDT1.6 UDT0.6 UDT1.5 UDT0.5 UDT1.4 UDT0.4 UDT1.3 UDT0.3 UDT1.2 UDT0.2 UDT1.1 UDT0.1 UDT1.0 UDT0.0 00 00 E8 UISTA SUSPND — RSTF TXD0F RXD0F RXD1F EOPF RESUMF 00 E9 UIEN SUSPNDIE RSTE RSTFIE TXD0IE RXD0IE TXD1IE EOPIE RESUMIE 00 EA UCON0 EB UCON1 EC UCON2 ED USTA TSEQ0 TSEQ1 — RSEQ STALL0 EP12SEL — SETUP TX0E — — IN RX0E TP0SIZ3 TP0SIZ2 TP0SIZ1 TP0SIZ0 00 00 00 00 FRESUM TP1SIZ3 TP1SIZ2 TP1SIZ1 TP1SIZ0 SOUT OUT EP2E EP1E STALL2 STALL1 RP0SIZ3 RP0SIZ2 RP0SIZ1 RP0SIZ0 EE UADR USBEN UADD6 UADD5 UADD4 UADD3 UADD2 UADD1 UADD0 00 EF UDR0 UDR0.7 UDR0.6 UDR0.5 UDR0.4 UDR0.3 UDR0.2 UDR0.1 UDR0.0 00 96/176 µPSD325X DEVICES Transceiver USB Physical Layer Characteristics. The following section describes the µPSD325X devices compliance to the Chapter 7 Electrical section of the USB Specification, Revision 1.1. The section contains all signaling, and physical layer specifications necessary to describe a low speed USB function. Low Speed Driver Characteristics. The µPSD325X devices use a differential output driver to drive the Low Speed USB data signal onto the USB cable. The output swings between the differential high and low state are well balanced to minimize signal skew. The slew rate control on the driver minimizes the radiated noise and cross talk on the USB cable. The driver’s outputs support three-state operation to achieve bi-directional half duplex operation. The µPSD325X devices driver Figure 44. Low Speed Driver Signal Waveforms One Bit Time 1.5 Mb/s tolerates a voltage on the signal pins of -0.5V to 3.6V with respect to local ground reference without damage. The driver tolerates this voltage for 10.0µs while the driver is active and driving, and tolerates this condition indefinitely when the driver is in its high impedance state. A low speed USB connection is made through an unshielded, untwisted wire cable a maximum of 3 meters in length. The rise and fall time of the signals on this cable are well controlled to reduce RFI emissions while limiting delays, signaling skews and distortions. The µPSD325X devices driver reaches the specified static signal levels with smooth rise and fall times, resulting in segments between low speed devices and the ports to which they are connected. VSE(max) Driver Signal Pins Signal pins pass output spec levels with minimal reflections and ringing VSE(min) VSS AI06629 97/176 µPSD325X DEVICES Receiver Characteristics The µPSD325X devices has a differential input receiver which is able to accept the USB data signal. The receiver features an input sensitivity of at least 200mV when both differential data inputs are in the range of at least 0.8V to 2.5V with respect to its local ground reference. This is the common mode range, as shown in Figure 45. The receiver tolerates static input voltages between -0.5V to 3.8V with respect to its local ground reference without damage. In addition to the differential receiver, there is a single-ended receiver for each of the two data lines. The single-ended receivers have a switching threshold between 0.8V and 2.0V (TTL inputs). Figure 45. Differential Input Sensitivity Over Entire Common Mode Range 1.0 Minimum Differential Sensitivity (volts) 0.8 0.6 0.4 0.2 0.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 Common Mode Input Voltage (volts) 2.6 2.8 3.0 3.2 AI06630 98/176 µPSD325X DEVICES External USB Pull-Up Resistor The USB system specifies a pull-up resistor on the D- pin for low-speed peripherals. The USB Spec 1.1 describes a 1.5kΩ pull-up resistor to a 3.3V supply. An approved alternative method is a 7.5kΩ pull-up to the USB VCC supply. This alterna- tive is defined for low-speed devices with an integrated cable. The chip is specified for the 7.5k Ω pull-up. This eliminates the need for an external 3.3V regulator, or for a pin dedicated to providing a 3.3V output from the chip. Figure 46. USB Data Signal Timing and Voltage Levels tR VOH VCR VOL 10% DD+ 90% 90% tF 10% AI06631 Figure 47. Receiver Jitter Tolerance TPERIOD Differential Data Lines TJR TJR1 TJR2 Consecutive Transitions N*TPERIOD+TJR1 Paired Transitions N*TPERIOD+TJR2 AI06632 99/176 µPSD325X DEVICES Figure 48. Differential to EOP Transition Skew and EOP Width TPERIOD Crossover Point Differential Data Lines Crossover Point Extended Diff. Data to SE0 Skew N*TPERIOD+TDEOP Source EOP Width: TEOPT Receiver EOP Width TEOPR1, TEOPR2 AI06633 Figure 49. Differential Data Jitter TPERIOD Crossover Points Differential Data Lines Consecutive Transitions N*TPERIOD+TxJR1 Paired Transitions N*TPERIOD+TxJR2 AI06634 100/176 µPSD325X DEVICES Table 81. Transceiver DC Characteristics Symb VOH VOL VDI VCM VSE CIN IIO RPU RPD Note: 1. 2. 3. 4. 5. 6. Parameter Static Output High Static Output Low Differential Input Sensitivity Differential Input Common Mode Single Ended Receiver Threshold Transceiver Capacitance Data Line (D+, D-) Leakage External Bus Pull-up Resistance, DExternal Bus Pull-down Resistance Test Conditions 15kΩ±5% Notes 2,3 |(D+) - (D-)|, Fig 6.9 Fig 6.9 — — 0V VSTBY VIN = VSS XTAL1 = VCC XTAL2 = VSS VSS < VIN < VCC 0.45 < VOUT < VCC VCC = 5.5V LVD logic disabled LVD logic enabled Active (12MHz) Idle (12MHz) ICC_CPU 2,3,6 Active (24MHz) Idle (24MHz) Active (40MHz) Idle (40MHz) VCC = 5V PLD_TURBO = Off, f = 0MHz 7 PLD_TURBO = On, f = 0MHz Flash memory SRAM PLD AC Base ICC_PSD (AC)6 Flash memory AC Adder SRAM AC Adder During Flash memory WRITE/Erase Only Read-only, f = 0MHz f = 0MHz VCC = 5V VCC = 5V 20 8 30 15 40 20 0 400 15 0 0 note 5 2.5 1.5 3.5 3.0 mA/ MHz mA/ MHz 700 30 0 0 –0.1 –10 –20 –1 –10 Symbol Parameter SRAM (PSD) Stand-by Current (VSTBY input) SRAM (PSD) Idle Current (VSTBY input) Reset Pin Pull-up Current (RESET) XTAL Feedback Resistor Current (XTAL1) Input Leakage Current Output Leakage Current Min. Typ. Max. Unit ISTBY IIDLE IRST IFR ILI ILO 1 0.5 1 0.1 –55 –50 1 10 250 380 30 10 38 20 62 30 µA µA µA µA µA µA µA µA mA mA mA mA mA mA µA/PT5 µA/PT mA mA mA IPD Power-down Mode PLD Only ICC_PSD (DC)6 Operating Supply Current Note: 1. IPD (Power-down Mode) is measured with: XTAL1=V SS; XTAL2=not connected; RESET=VCC; Port 0 =VCC; all other pins are disconnected. PLD not in Turbo Mode. 2. ICC_CPU (active mode) is measured with: XTAL1 driven with tCLCH, tCHCL = 5ns, VIL = VSS +0.5V, VIH = Vcc – 0.5V, XTAL2 = not connected; RESET=VSS; Port 0=VCC; all other pins are disconnected. ICC would be slightly higher if a crystal oscillator is used (approximately 1mA). 3. ICC_CPU (Idle Mode) is measured with: XTAL1 driven with tCLCH, tCHCL = 5ns, VIL = VSS+0.5V, VIH = V CC– 0.5V, XTAL2 = not connected; Port 0 = VCC; RESET=VCC; all other pins are disconnected. 4. PLD is in non-Turbo Mode and none of the inputs are switching. 5. See Figure 72 for the PLD current calculation. 6. I/O current = 0 mA, all I/O pins are disconnected. 149/176 µPSD325X DEVICES Table 113. DC Characteristics (3V Devices) Symbol Parameter Input High Voltage (Ports 1, 2, 3, 4[Bits 7,6,5,4,3,1,0], A, B, C, D, XTAL1, RESET) Input High Voltage (Port 4[Bit 2]) Input High Voltage (Ports 1, 2, 3, 4[Bits 7,6,5,4,3,1,0], XTAL1, RESET) Input Low Voltage (Ports A, B, C, D) VIL1 Input Low Voltage (Port 4[Bit 2]) Test Condition (in addition to those in Table 110, page 146) 3.0V < VCC < 3.6V 3.0V < VCC < 3.6V 3.0V < VCC < 3.6V Min. Typ. Max. Unit VIH VIH1 VIL 0.7VCC 2.0 VSS– 0.5 VCC + 0.5 VCC + 0.5 0.3VCC V V V 3.0V < VCC < 3.6V 3.0V < VCC < 3.6V IOL = 20µA VCC = 3.0V IOL = 4mA VCC = 3.0V IOL = 1.6mA IOL = 100µA IOL = 3.2mA IOL = 200µA IOH = –20µA VCC = 3.0V IOH = –1mA VCC = 3.0V IOH = –20µA IOH = –10µA IOH = –800µA IOH = –80µA IOH = –1µA 0.1V hysteresis IOL = 3.2mA –0.5 VSS– 0.5 0.01 0.15 0.8 0.8 0.1 0.45 0.45 0.3 0.45 0.3 V V V V V V V V V V V V V V V VOL Output Low Voltage (Ports A,B,C,D) VOL1 Output Low Voltage (Ports 1,2,3,4, WR, RD) Output Low Voltage (Port 0, ALE, PSEN) VOL2 2.9 2.4 2.0 2.7 2.0 2.7 VSTBY – 0.8 2.3 1.0 1.5 2.0 2.99 2.6 VOH Output High Voltage (Ports A,B,C,D) VOH1 Output High Voltage (Ports 1,2,3,4, WR, RD) Output High Voltage (Port 0 in ext. Bus Mode, ALE, PSEN))4 Output High Voltage VSTBYON Low Voltage Reset XTAL Open Bias Voltage (XTAL1, XTAL2) VCC(min) for Flash Erase and Program SRAM (PSD) Stand-by Voltage SRAM (PSD) Data Retention Voltage Logic '0' Input Current (Ports 1,2,3,4) VOH2 VOH3 VLVR VOP VLKO VSTBY VDF IIL 2.5 2.7 2.0 2.2 VCC–0.2 V V V V V Only on VSTBY VIN = 0.45V (0V for Port 4[pin 2]) 2 –1 –50 µA 150/176 µPSD325X DEVICES Test Condition (in addition to those in Table 110, page 146) VIN = 3.5V (2.5V for Port 4[pin 2]) VCC = 0V VCC > VSTBY VIN = VSS XTAL1 = VCC XTAL2 = VSS VSS < VIN < VCC 0.45 < VOUT < VCC VCC = 3.6V LVD logic disabled LVD logic enabled Active (12MHz) ICC_CPU 2,3,6 Idle (12MHz) Active (24MHz) Idle (24MHz) VCC = 3.6V 8 4 15 8 0 200 10 0 0 note 5 1.5 0.8 2.0 1.5 mA/ MHz mA/ MHz 400 25 0 0 –0.1 –10 –20 –1 –10 Symbol Parameter Logic 1-to-0 Transition Current (Ports 1,2,3,4) SRAM (PSD) Stand-by Current (VSTBY input) SRAM (PSD) Idle Current (VSTBY input) Reset Pin Pull-up Current (RESET) XTAL Feedback Resistor Current (XTAL1) Input Leakage Current Output Leakage Current Min. Typ. Max. Unit ITL ISTBY IIDLE IRST IFR ILI ILO 1 –25 0.5 –250 1 0.1 –55 –50 1 10 110 180 10 5 20 10 µA µA µA µA µA µA µA µA µA mA mA mA mA µA/ PT5 µA/ PT mA mA mA IPD Power-down Mode VCC = 3.6V PLD_TURBO = Off, f = 0MHz 7 PLD_TURBO = On, f = 0MHz Flash memory SRAM During Flash memory WRITE/Erase Only Read-only, f = 0MHz f = 0MHz PLD Only ICC_PSD (DC)6 Operating Supply Current PLD AC Base ICC_PSD (AC) 6 Flash memory AC Adder SRAM AC Adder Note: 1. IPD (Power-down Mode) is measured with: XTAL1=V SS; XTAL2=not connected; RESET=VCC; Port 0 =VCC; all other pins are disconnected. PLD not in Turbo mode. 2. ICC_CPU (active mode) is measured with: XTAL1 driven with tCLCH, tCHCL = 5ns, VIL = VSS +0.5V, VIH = Vcc – 0.5V, XTAL2 = not connected; RESET=VSS; Port 0=VCC; all other pins are disconnected. ICC would be slightly higher if a crystal oscillator is used (approximately 1mA). 3. ICC_CPU (Idle Mode) is measured with: XTAL1 driven with tCLCH, tCHCL = 5ns, VIL = VSS+0.5V, VIH = V CC– 0.5V, XTAL2 = not connected; Port 0 = VCC; RESET=VCC; all other pins are disconnected. 4. PLD is in non-Turbo Mode and none of the inputs are switching. 5. See Figure 72 for the PLD current calculation. 6. I/O current = 0 mA, all I/O pins are disconnected. 151/176 µPSD325X DEVICES Figure 75. External Program Memory READ Cycle tLHLL ALE tAVLL tPLPH tLLIV tPLIV PSEN tLLAX tAZPL PORT 0 A0-A7 tAVIV PORT 2 A8-A11 INSTR IN tPXIX A8-A11 AI06848 tLLPL tPXAV tPXIZ A0-A7 Table 114. External Program Memory AC Characteristics (with the 5V MCU Module) Symbol Parameter 1 40MHz Oscillator Min Max Variable Oscillator 1/tCLCL = 24 to 40MHz Min 2tCLCL – 15 tCLCL – 15 tCLCL – 15 Max Unit tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ2 tPXAV2 tAVIV tAZPL ALE pulse width Address set-up to ALE Address hold after ALE ALE Low to valid instruction in ALE to PSEN PSEN pulse width PSEN to valid instruction in Input instruction hold after PSEN Input instruction float after PSEN Address valid after PSEN Address to valid instruction in Address float to PSEN 35 10 10 55 10 60 30 0 15 20 70 –5 ns ns ns 4tCLCL – 45 ns ns ns 3tCLCL – 45 ns ns tCLCL – 10 ns ns 5tCLCL – 55 ns ns tCLCL – 15 3tCLCL – 15 0 tCLCL – 5 –5 Note: 1. Conditions (in addition to those in Table 109, VCC = 4.5 to 5.5V): V SS = 0V; CL for Port 0, ALE and PSEN output is 100pF; CL for other outputs is 80pF 2. Interfacing the µPSD325X devices to devices with float times up to 20ns is permissible. This limited bus contention does not cause any damage to Port 0 drivers. 152/176 µPSD325X DEVICES Table 115. External Program Memory AC Characteristics (with the 3V MCU Module) Symbol tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ 2 Parameter1 ALE pulse width Address set-up to ALE Address hold after ALE ALE Low to valid instruction in ALE to PSEN PSEN pulse width PSEN to valid instruction in Input instruction hold after PSEN Input instruction float after PSEN Address valid after PSEN Address to valid instruction in Address float to PSEN 24MHz Oscillator Min 43 17 17 80 22 95 60 0 32 37 148 –10 Max Variable Oscillator 1/tCLCL = 8 to 24MHz Min 2tCLCL – 40 tCLCL – 25 tCLCL – 25 4tCLCL – 87 tCLCL – 20 3tCLCL – 30 3tCLCL – 65 0 tCLCL – 10 tCLCL – 5 5tCLCL – 60 –10 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns tPXAV2 tAVIV tAZPL Note: 1. Conditions (in addition to those in Table 110, V CC = 3.0 to 3.6V): VSS = 0V; CL for Port 0, ALE and PSEN output is 100pF, for 5V devices, and 50pF for 3V devices; CL for other outputs is 80pF, for 5V devices, and 50pF for 3V devices) 2. Interfacing the µPSD325X devices to devices with float times up to 35ns is permissible. This limited bus contention does not cause any damage to Port 0 drivers. Table 116. External Clock Drive (with the 5V MCU Module) Symbol tRLRH tWLWH tLLAX2 tRHDX tRHDX Parameter1 Oscillator period High time Low time Rise time Fall time 40MHz Oscillator Min Max Variable Oscillator 1/tCLCL = 24 to 40MHz Min 25 10 10 Max 41.7 tCLCL – tCLCX tCLCL – tCLCX 10 10 ns ns ns ns ns Unit Note: 1. Conditions (in addition to those in Table 109, VCC = 4.5 to 5.5V): V SS = 0V; CL for Port 0, ALE and PSEN output is 100pF; CL for other outputs is 80pF Table 117. External Clock Drive (with the 3V MCU Module) Symbol tRLRH tWLWH tLLAX2 tRHDX tRHDX Parameter Oscillator period High time Low time Rise time Fall time 1 24MHz Oscillator Min Max Variable Oscillator 1/tCLCL = 8 to 24MHz Min 41.7 12 12 Max 125 tCLCL – tCLCX tCLCL – tCLCX 12 12 Unit ns ns ns ns ns Note: 1. Conditions (in addition to those in Table 110, V CC = 3.0 to 3.6V): VSS = 0V; CL for Port 0, ALE and PSEN output is 100pF, for 5V devices, and 50pF for 3V devices; CL for other outputs is 80pF, for 5V devices, and 50pF for 3V devices) 153/176 µPSD325X DEVICES Figure 76. External Data Memory READ Cycle ALE tLHLL PSEN tLLDV tLLWL RD tAVLL tLLAX2 PORT 0 A0-A7 from RI or DPL tWHLH tRLRH tRLDV tRLAZ tRHDZ tRHDX DATA IN A0-A7 from PCL INSTR IN tAVWL tAVDV PORT 2 P2.0 to P2.3 or A8-A11 from DPH A8-A11 from PCH AI07088 Figure 77. External Data Memory WRITE Cycle ALE tLHLL PSEN tLLWL WR tAVLL tLLAX PORT 0 A0-A7 from RI or DPL tWHLH tWLWH tQVWX tQVWH DATA OUT tWHQX A0-A7 from PCL INSTR IN tAVWL PORT 2 P2.0 to P2.3 or A8-A11 from DPH A8-A11 from PCH AI07089 154/176 µPSD325X DEVICES Table 118. External Data Memory AC Characteristics (with the 5V MCU Module) Symbol Parameter1 40MHz Oscillator Min tRLRH tWLWH tLLAX2 tRHDX tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tWHLH tQVWX tQVWH tWHQX tRLAZ RD pulse width WR pulse width Address hold after ALE RD to valid data in Data hold after RD Data float after RD ALE to valid data in Address to valid data in ALE to WR or RD Address valid to WR or RD WR or RD High to ALE High Data valid to WR transition Data set-up before WR Data hold after WR Address float after RD 60 70 10 5 125 5 0 40 0 38 150 150 90 3tCLCL – 15 4tCLCL – 30 tCLCL – 15 tCLCL – 20 7tCLCL – 50 tCLCL – 20 0 tCLCL + 15 120 120 10 75 0 2tCLCL – 12 8tCLCL – 50 9tCLCL – 75 tCLCL + 15 Max Variable Oscillator 1/tCLCL = 24 to 40MHz Min 6tCLCL – 30 6tCLCL – 30 tCLCL – 15 5tCLCL – 50 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit Note: 1. Conditions (in addition to those in Table 109, VCC = 4.5 to 5.5V): V SS = 0V; CL for Port 0, ALE and PSEN output is 100pF; CL for other outputs is 80pF 155/176 µPSD325X DEVICES Table 119. External Data Memory AC Characteristics (with the 3V MCU Module) Symbol Parameter1 24MHz Oscillator Min tRLRH tWLWH tLLAX2 tRHDX tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tWHLH tQVWX tQVWH tWHQX tRLAZ RD pulse width WR pulse width Address hold after ALE RD to valid data in Data hold after RD Data float after RD ALE to valid data in Address to valid data in ALE to WR or RD Address valid to WR or RD WR or RD High to ALE High Data valid to WR transition Data set-up before WR Data hold after WR Address float after RD 75 67 17 5 170 15 0 67 0 63 200 220 175 3tCLCL – 50 4tCLCL – 97 tCLCL – 25 tCLCL – 37 7tCLCL – 122 tCLCL – 27 0 tCLCL + 25 180 180 56 118 0 2tCLCL – 20 8tCLCL – 133 9tCLCL – 155 tCLCL + 50 Max Variable Oscillator 1/tCLCL = 8 to 24MHz Min 6tCLCL – 70 6tCLCL – 70 2tCLCL – 27 5tCLCL – 90 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit Note: 1. Conditions (in addition to those in Table 110, V CC = 3.0 to 3.6V): VSS = 0V; CL for Port 0, ALE and PSEN output is 100pF, for 5V devices, and 50pF for 3V devices; CL for other outputs is 80pF, for 5V devices, and 50pF for 3V devices) Table 120. A/D Analog Specification Symbol AVREF VAN IAVDD CAIN NNLE NDNLE NZOE NFSE NGE TCONV Parameter Analog Power Supply Input Voltage Range Analog Input Voltage Range Current Following between VCC and VSS Overall Accuracy Non-Linearity Error Differential Non-Linearity Error Zero-Offset Error Full Scale Error Gain Error Conversion Time at 8MHz clock Test Condition Min. VSS VSS – 0.3 Typ. Max. VCC AVREF + 0.3 200 ±2 ±2 ±2 ±2 ±2 ±2 20 Unit V V µA l.s.b. l.s.b. l.s.b. l.s.b. l.s.b. l.s.b. µs 156/176 µPSD325X DEVICES Figure 78. Input to Output Disable / Enable INPUT tER INPUT TO OUTPUT ENABLE/DISABLE tEA AI02863 Table 121. CPLD Combinatorial Timing (5V Devices) Symbol tPD2 tEA tER tARP tARPW tARD Parameter CPLD Input Pin/Feedback to CPLD Combinatorial Output CPLD Input to CPLD Output Enable CPLD Input to CPLD Output Disable CPLD Register Clear or Preset Delay CPLD Register Clear or Preset Pulse Width CPLD Array Delay Any macrocell 10 11 +2 Conditions Min Max 20 21 21 21 PT Turbo Slew Aloc Off rate1 +2 + 10 + 10 + 10 + 10 + 10 –2 –2 –2 –2 Unit ns ns ns ns ns ns Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount 2. tPD for MCU address and control signals refers to delay from pins on Port 0, Port 2, RD WR, PSEN and ALE to CPLD combinatorial output (80-pin package only) Table 122. CPLD Combinatorial Timing (3V Devices) Symbol tPD2 tEA tER tARP tARPW tARD Parameter CPLD Input Pin/Feedback to CPLD Combinatorial Output CPLD Input to CPLD Output Enable CPLD Input to CPLD Output Disable CPLD Register Clear or Preset Delay CPLD Register Clear or Preset Pulse Width CPLD Array Delay Any macrocell 25 25 +4 Conditions Min Max 40 43 43 40 PT Aloc +4 Turbo Slew Off rate1 + 20 + 20 + 20 + 20 + 20 –6 –6 –6 –6 Unit ns ns ns ns ns ns Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount 2. tPD for MCU address and control signals refers to delay from pins on Port 0, Port 2, RD WR, PSEN and ALE to CPLD combinatorial output (80-pin package only) 157/176 µPSD325X DEVICES Figure 79. Synchronous Clock Mode Timing – PLD tCH tCL CLKIN tS INPUT tH tCO REGISTERED OUTPUT AI02860 Table 123. CPLD Macrocell Synchronous Clock Mode Timing (5V Devices) Symbol Parameter Maximum Frequency External Feedback fMAX Maximum Frequency Internal Feedback (fCNT) Maximum Frequency Pipelined Data tS tH tCH tCL tCO tARD tMIN Input Setup Time Input Hold Time Clock High Time Clock Low Time Clock to Output Delay CPLD Array Delay Minimum Clock Period 2 Clock Input Clock Input Clock Input Any macrocell tCH+tCL 12 Conditions 1/(tS+tCO) 1/(tS+tCO–10) 1/(tCH+tCL) 12 0 6 6 13 11 +2 –2 Min Max 40.0 66.6 83.3 +2 + 10 PT Turbo Slew Aloc Off rate1 Unit MHz MHz MHz ns ns ns ns ns ns ns Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount. 2. CLKIN (PD1) t CLCL = tCH + tCL. 158/176 µPSD325X DEVICES Table 124. CPLD Macrocell Synchronous Clock Mode Timing (3V Devices) Symbol Parameter Maximum Frequency External Feedback fMAX Maximum Frequency Internal Feedback (fCNT) Maximum Frequency Pipelined Data tS tH tCH tCL tCO tARD tMIN Input Setup Time Input Hold Time Clock High Time Clock Low Time Clock to Output Delay CPLD Array Delay Minimum Clock Period2 Clock Input Clock Input Clock Input Any macrocell tCH+tCL 25 Conditions 1/(tS+tCO) 1/(tS+tCO–10) 1/(tCH+tCL) 20 0 15 10 25 25 +4 –6 Min Max 22.2 28.5 40.0 +4 + 20 PT Aloc Turbo Slew Off rate1 Unit MHz MHz MHz ns ns ns ns ns ns ns Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount. 2. CLKIN (PD1) t CLCL = tCH + tCL. 159/176 µPSD325X DEVICES Figure 80. Asynchronous RESET / Preset tARPW RESET/PRESET INPUT tARP REGISTER OUTPUT AI02864 Figure 81. Asynchronous Clock Mode Timing (product term clock) tCHA tCLA CLOCK tSA tHA INPUT tCOA REGISTERED OUTPUT AI02859 Table 125. CPLD Macrocell Asynchronous Clock Mode Timing (5V Devices) Symbol Parameter Maximum Frequency External Feedback fMAXA Maximum Frequency Internal Feedback (fCNTA) Maximum Frequency Pipelined Data tSA tHA tCHA tCLA tCOA tARDA tMINA Input Setup Time Input Hold Time Clock Input High Time Clock Input Low Time Clock to Output Delay CPLD Array Delay Minimum Clock Period Any macrocell 1/fCNTA 16 Conditions 1/(tSA+tCOA) 1/(tSA+tCOA–10) 1/(tCHA+tCLA) 7 8 9 9 21 11 +2 + 10 + 10 + 10 –2 Min Max 38.4 62.5 71.4 +2 + 10 PT Turbo Slew Aloc Off Rate Unit MHz MHz MHz ns ns ns ns ns ns ns 160/176 µPSD325X DEVICES Table 126. CPLD Macrocell Asynchronous Clock Mode Timing (3V Devices) Symbol Parameter Maximum Frequency External Feedback fMAXA Maximum Frequency Internal Feedback (fCNTA) Maximum Frequency Pipelined Data tSA tHA tCHA tCLA tCOA tARD tMINA Input Setup Time Input Hold Time Clock High Time Clock Low Time Clock to Output Delay CPLD Array Delay Minimum Clock Period Any macrocell 1/fCNTA 36 Conditions 1/(tSA+tCOA) 1/(tSA+tCOA–10) 1/(tCHA+tCLA) 10 12 17 13 36 25 +4 + 20 + 20 + 20 –6 Min Max 21.7 27.8 33.3 +4 + 20 PT Turbo Slew Aloc Off Rate Unit MHz MHz MHz ns ns ns ns ns ns ns 161/176 µPSD325X DEVICES Figure 82. Input Macrocell Timing (product term clock) t INH PT CLOCK t INL t IS INPUT t IH OUTPUT t INO AI03101 Table 127. Input Macrocell Timing (5V Devices) Symbol tIS tIH tINH tINL tINO Parameter Input Setup Time Input Hold Time NIB Input High Time NIB Input Low Time NIB Input to Combinatorial Delay Conditions (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) Min 0 15 9 9 34 +2 + 10 + 10 Max PT Aloc Turbo Off Unit ns ns ns ns ns Note: 1. Inputs from Port A, B, and C relative to register/ latch clock from the PLD. ALE/AS latch timings refer to t AVLX and t LXAX. Table 128. Input Macrocell Timing (3V Devices) Symbol tIS tIH tINH tINL tINO Parameter Input Setup Time Input Hold Time NIB Input High Time NIB Input Low Time NIB Input to Combinatorial Delay Conditions (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) Min 0 25 12 12 46 +4 + 20 + 20 Max PT Aloc Turbo Off Unit ns ns ns ns ns Note: 1. Inputs from Port A, B, and C relative to register/latch clock from the PLD. ALE latch timings refer to t AVLX and tLXAX. 162/176 µPSD325X DEVICES Table 129. Program, WRITE and Erase Times (5V Devices) Symbol Flash Program Flash Bulk Erase1 (pre-programmed) Flash Bulk Erase (not pre-programmed) tWHQV3 tWHQV2 tWHQV1 Sector Erase (pre-programmed) Sector Erase (not pre-programmed) Byte Program Program / Erase Cycles (per Sector) tWHWLO tQ7VQV Sector Erase Time-Out DQ7 Valid to Output (DQ7-DQ0) Valid (Data Polling)2 100,000 100 30 Parameter Min. Typ. 8.5 3 5 1 2.2 14 1200 30 30 Max. Unit s s s s s µs cycles µs ns Note: 1. Programmed to all zero before erase. 2. The polling status, DQ7, is valid t Q7VQV time units before the data byte, DQ0-DQ7, is valid for reading. Table 130. Program, WRITE and Erase Times (3V Devices) Symbol Flash Program Flash Bulk Erase1 (pre-programmed) Flash Bulk Erase (not pre-programmed) tWHQV3 tWHQV2 tWHQV1 Sector Erase (pre-programmed) Sector Erase (not pre-programmed) Byte Program Program / Erase Cycles (per Sector) tWHWLO tQ7VQV Sector Erase Time-Out DQ7 Valid to Output (DQ7-DQ0) Valid (Data Polling)2 100,000 100 30 Parameter Min. Typ. 8.5 3 5 1 2.2 14 1200 30 30 Max. Unit s s s s s µs cycles µs ns Note: 1. Programmed to all zero before erase. 2. The polling status, DQ7, is valid t Q7VQV time units before the data byte, DQ0-DQ7, is valid for reading. 163/176 µPSD325X DEVICES Figure 83. Peripheral I/O READ Timing ALE A/D BUS ADDRESS DATA VALID tAVQV (PA) tSLQV (PA) CSI tRLQV (PA) RD tRHQZ (PA) tDVQV (PA) DATA ON PORT A AI06610 Table 131. Port A Peripheral Data Mode READ Timing (5V Devices) Symbol tAVQV–PA tSLQV–PA tRLQV–PA tDVQV–PA tRHQZ–PA Parameter Address Valid to Data Valid CSI Valid to Data Valid RD to Data Valid Data In to Data Out Valid RD to Data High-Z (Note 2) Conditions (Note 1) Min Max 37 27 32 22 23 Turbo Off + 10 + 10 Unit ns ns ns ns ns Note: 1. Any input used to select Port A Data Peripheral Mode. 2. Data is already stable on Port A. Table 132. Port A Peripheral Data Mode READ Timing (3V Devices) Symbol tAVQV–PA tSLQV–PA tRLQV–PA tDVQV–PA tRHQZ–PA Parameter Address Valid to Data Valid CSI Valid to Data Valid RD to Data Valid Data In to Data Out Valid RD to Data High-Z (Note 2) Conditions (Note 1) Min Max 50 37 45 38 36 Turbo Off + 20 + 20 Unit ns ns ns ns ns Note: 1. Any input used to select Port A Data Peripheral Mode. 2. Data is already stable on Port A. 164/176 µPSD325X DEVICES Figure 84. Peripheral I/O WRITE Timing ALE A / D BUS ADDRESS DATA OUT tWLQV WR (PA) tWHQZ (PA) tDVQV (PA) PORT A DATA OUT AI06611 Table 133. Port A Peripheral Data Mode WRITE Timing (5V Devices) Symbol tWLQV–PA tDVQV–PA tWHQZ–PA Parameter WR to Data Propagation Delay Data to Port A Data Propagation Delay WR Invalid to Port A Tri-state (Note 1) Conditions Min Max 25 22 20 Unit ns ns ns Note: 1. Data stable on Port 0 pins to data on Port A. Table 134. Port A Peripheral Data Mode WRITE Timing (3V Devices) Symbol tWLQV–PA tDVQV–PA tWHQZ–PA Parameter WR to Data Propagation Delay Data to Port A Data Propagation Delay WR Invalid to Port A Tri-state (Note 1) Conditions Min Max 42 38 33 Unit ns ns ns Note: 1. Data stable on Port 0 pins to data on Port A. 165/176 µPSD325X DEVICES Figure 85. Reset (RESET) Timing VCC VCC(min) tNLNH tNLNH-A Warm Reset tNLNH-PO Power-On Reset tOPR tOPR RESET AI02866b Table 135. Reset (RESET) Timing (5V Devices) Symbol tNLNH tNLNH–PO tNLNH–A tOPR Parameter RESET Active Low Time 1 Power-on Reset Active Low Time Warm RESET 2 RESET High to Operational Device Conditions Min 150 1 25 120 Max Unit ns ms µs ns Note: 1. Reset (RESET) does not reset Flash memory Program or Erase cycles. 2. Warm RESET aborts Flash memory Program or Erase cycles, and puts the device in READ Mode. Table 136. Reset (RESET) Timing (3V Devices) Symbol tNLNH tNLNH–PO tNLNH–A tOPR Parameter RESET Active Low Time 1 Power-on Reset Active Low Time Warm RESET 2 RESET High to Operational Device Conditions Min 300 1 25 300 Max Unit ns ms µs ns Note: 1. Reset (RESET) does not reset Flash memory Program or Erase cycles. 2. Warm RESET aborts Flash memory Program or Erase cycles, and puts the device in READ Mode. Table 137. VSTBYON Definitions Timing (5V Devices) Symbol tBVBH tBXBL Parameter VSTBY Detection to VSTBYON Output High VSTBY Off Detection to VSTBYON Output Low Conditions (Note 1) (Note 1) Min Typ 20 20 Max Unit µs µs Note: 1. VSTBYON timing is measured at VCC ramp rate of 2ms. Table 138. VSTBYON Timing (3V Devices) Symbol tBVBH tBXBL Parameter VSTBY Detection to VSTBYON Output High VSTBY Off Detection to VSTBYON Output Low Conditions (Note 1) (Note 1) Min Typ 20 20 Max Unit µs µs Note: 1. VSTBYON timing is measured at VCC ramp rate of 2ms. 166/176 µPSD325X DEVICES Figure 86. ISC Timing t ISCCH TCK t ISCCL t ISCPSU t ISCPH TDI/TMS t ISCPZV t ISCPCO ISC OUTPUTS/TDO t ISCPVZ ISC OUTPUTS/TDO AI02865 Table 139. ISC Timing (5V Devices) Symbol tISCCF tISCCH tISCCL tISCCFP tISCCHP tISCCLP tISCPSU tISCPH tISCPCO tISCPZV tISCPVZ Parameter Clock (TCK, PC1) Frequency (except for PLD) Clock (TCK, PC1) High Time (except for PLD) Clock (TCK, PC1) Low Time (except for PLD) Clock (TCK, PC1) Frequency (PLD only) Clock (TCK, PC1) High Time (PLD only) Clock (TCK, PC1) Low Time (PLD only) ISC Port Set Up Time ISC Port Hold Up Time ISC Port Clock to Output ISC Port High-Impedance to Valid Output ISC Port Valid Output to High-Impedance Conditions (Note 1) (Note 1) (Note 1) (Note 2) (Note 2) (Note 2) 240 240 7 5 21 21 21 23 23 2 Min Max 20 Unit MHz ns ns MHz ns ns ns ns ns ns ns Note: 1. For non-PLD Programming, Erase or in ISC By-pass Mode. 2. For Program or Erase PLD only. 167/176 µPSD325X DEVICES Table 140. ISC Timing (3V Devices) Symbol tISCCF tISCCH tISCCL tISCCFP tISCCHP tISCCLP tISCPSU tISCPH tISCPCO tISCPZV tISCPVZ Parameter Clock (TCK, PC1) Frequency (except for PLD) Clock (TCK, PC1) High Time (except for PLD) Clock (TCK, PC1) Low Time (except for PLD) Clock (TCK, PC1) Frequency (PLD only) Clock (TCK, PC1) High Time (PLD only) Clock (TCK, PC1) Low Time (PLD only) ISC Port Set Up Time ISC Port Hold Up Time ISC Port Clock to Output ISC Port High-Impedance to Valid Output ISC Port Valid Output to High-Impedance Conditions (Note 1) (Note 1) (Note 1) (Note 2) (Note 2) (Note 2) 240 240 12 5 30 30 30 40 40 2 Min Max 12 Unit MHz ns ns MHz ns ns ns ns ns ns ns Note: 1. For non-PLD Programming, Erase or in ISC By-pass Mode. 2. For Program or Erase PLD only. Figure 87. MCU Module AC Measurement I/O Waveform VCC – 0.5V 0.2 VCC + 0.9V Test Points 0.2 VCC – 0.1V AI06650 0.45V Note: AC inputs during testing are driven at VCC–0.5V for a logic '1,' and 0.45V for a logic '0.' Timing measurements are made at VIH(min) for a logic '1,' and VIL(max) for a logic '0' Figure 88. PSD MODULE AC Float I/O Waveform VOH – 0.1V Test Reference Points VLOAD – 0.1V 0.2 VCC – 0.1V VOL + 0.1V AI06651 VLOAD + 0.1V Note: For timing purposes, a Port pin is considered to be no longer floating when a 100mV change from load voltage occurs, and begins to float when a 100mV change from the loaded VOH or VOL level occurs IOL and IOH ≥ 20mA 168/176 µPSD325X DEVICES Figure 89. External Clock Cycle Figure 90. Recommended Oscillator Circuits Note: C1, C2 = 30pF ± 10pF for crystals For ceramic resonators, contact resonator manufacturer Oscillation circuit is designed to be used either with a ceramic resonator or crystal oscillator. Since each crystal and ceramic resonator have their own characteristics, the user should consult the crystal manufacturer for appropriate values of external components. Figure 91. PSD MODULE AC Measurement I/O Waveform Figure 92. PSD MODULE AC Measurement Load Circuit 2.01 V 3.0V Test Point 0V AI03103b 195 Ω 1.5V Device Under Test CL = 30 pF (Including Scope and Jig Capacitance) AI03104b Table 141. Capacitance Symbol CIN COUT Parameter Input Capacitance (for input pins) Output Capacitance (for input/ output pins) Test Condition VIN = 0V VOUT = 0V Typ.2 4 8 Max. 6 12 Unit pF pF Note: 1. Sampled only, not 100% tested. 2. Typical values are for T A = 25°C and nominal supply voltages. 169/176 µPSD325X DEVICES PACKAGE MECHANICAL INFORMATION Figure 93. TQFP52 – 52-lead Plastic Quad Flatpack Package Outline D D1 D2 A2 e Ne E2 E1 E b N 1 Nd L1 A CP c QFP-A Note: Drawing is not to scale. A1 α L 170/176 µPSD325X DEVICES Table 142. TQFP52 – 52-lead Plastic Quad Flatpack Package Mechanical Data mm Symb Typ A A1 A2 b c D D1 D2 E E1 E2 e L L1 α n Nd Ne CP – 0.65 – 1.00 – – 0.45 – 0° 52 13 13 – 0.10 – – 0.75 – 7° 0.026 – 0.039 – – 0.018 – 0° 52 13 13 – 0.004 – 0.030 – 7° 12.00 10.00 – – – – 0.473 0.394 – – – – – – – – – 12.00 10.00 Min – 0.05 1.25 0.02 0.07 – – Max 1.75 0.020 1.55 0.04 0.23 – – Typ – – – – – 0.473 0.394 Min – 0.002 0.049 0.007 0.002 – – Max 0.069 0.008 0.061 0.016 0.009 – – inches 171/176 µPSD325X DEVICES Figure 94. TQFP80 – 80-lead Plastic Quad Flatpack Package Outline D D1 D2 A2 e Ne E2 E1 E b N 1 Nd L1 A CP c QFP-A Note: Drawing is not to scale. A1 α L 172/176 µPSD325X DEVICES Table 143. TQFP80 – 80-lead Plastic Quad Flatpack Package Mechanical Data mm Symb Typ A A1 A2 b c D D1 D2 E E1 E2 e L L1 α n Nd Ne CP – – – 1.40 0.22 – 14.00 12.00 9.50 14.00 12.00 9.50 0.50 0.60 1.00 3.5 Min – 0.05 1.35 0.17 0.09 – – – – – – – 0.45 – 0° 80 20 20 – 0.08 – Max 1.60 0.15 1.45 0.27 0.20 – – – – – – – 0.75 – 7° Typ – – 0.055 0.009 – 0.551 0.472 0.374 0.473 0.394 0.374 0.020 0.024 0.039 3.5 Min – 0.002 0.053 0.007 0.004 – – – – – – – 0.018 – 0° 80 20 20 – 0.003 Max 0.063 0.006 0.057 0.011 0.008 – – – – – – – 0.030 – 7° inches 173/176 µPSD325X DEVICES PART NUMBERING Table 144. Ordering Information Scheme Example: Device Type µPSD = Microcontroller PSD Family 3 = 8032 core PLD Size 2 = 16 Macrocells SRAM Size 5 = 256Kbit Main Flash Memory Size 3 = 1Mbit 4 = 2Mbit IP Mix A = USB, I2C, PWM, DDC, ADC, (2) UARTs Supervisor (Reset Out, Reset In, LVD, WD) B = I2C, PWM, DDC, ADC, (2) UARTs Supervisor (Reset Out, Reset In, LVD, WD) Operating Voltage blank = VCC = 4.5 to 5.5V V = VCC = 3.0 to 3.6V Speed –24 = 24MHz –40 = 40MHz Package T = 52-pin TQFP U = 80-pin TQFP Temperature Range 1 = 0 to 70°C 6 = –40 to 85°C Shipping Option T = Tape and Reel Packing µPSD 3 2 5 4 B V – 24 U 6 T For a list of available options (e.g., Speed, Package) or for further information on any aspect of this device, please contact your nearest ST Sales Office. 174/176 µPSD325X DEVICES REVISION HISTORY Table 145. Document Revision History Date 26-Nov-2002 Rev. # 1.0 First Issue Revision Details 175/176 µPSD325X DEVICES Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners © 2002 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. www.st.com 176/176