UPSD3434EV-40T6

uPSD34xx Turbo Plus Series Fast Turbo 8032 MCU with USB and Programmable Logic DATA BRIEFING FEATURES SUMMARY ■ ■ ■ ■ ■ FAST 8-BIT TURBO 8032 MCU, 40MHz – Advanced core, 4-clocks per instruction – 10 MIPs peak performance at 40MHz (5V) – JTAG Debug and In-System Programming – 16-bit internal instruction path fetches double-byte instruction in a single memory cycle – Branch Cache & 4 instruction Prefetch Queue – Dual XDATA pointers with automatic increment and decrement – Compatible with 3rd party 8051 tools DUAL FLASH MEMORIES WITH MEMORY MANAGEMENT – Place either memory into 8032 program address space or data address space – READ-while-WRITE operation for InApplication Programming and EEPROM emulation – Single voltage program and erase – 100K guaranteed erase cycles, 15-year retention CLOCK, RESET, AND POWER SUPPLY MANAGEMENT – SRAM is Battery Backup capable – Flexible 8-level CPU clock divider register – Normal, Idle, and Power Down Modes – Power-on and Low Voltage reset supervisor – Programmable Watchdog Timer PROGRAMMABLE LOGIC, GENERAL PURPOSE – 16 macrocells for logic applications (e.g., shifters, state machines, chip-selects, glue-logic to keypads, and LCDs) A/D CONVERTER – Eight Channels, 10-bit resolution, 6µs Figure 1. Packages TQFP52 (T), 52-lead, Thin, Quad, Flat TQFP80 (U), 80-lead, Thin, Quad, Flat ■ ■ ■ COMMUNICATION INTERFACES – USB v2.0 Full Speed (12Mbps) 10 endpoint pairs (In/Out), each endpoint with 64-byte FIFO (supports Control, Intr, and Bulk transfer types) – I2C Master/Slave controller, 833kHz – SPI Master controller, 1MHz – Two UARTs with independent baud rate – IrDA Potocol: up to 115 kbaud – Up to 46 I/O, 5V tolerant uPSD34xxV TIMERS AND INTERRUPTS – Three 8032 standard 16-bit timers – Programmable Counter Array (PCA), six 16-bit modules for PWM, CAPCOM, and timers – 8/10/16-bit PWM operation – 12 Interrupt sources with two external interrupt pins OPERATING VOLTAGE SOURCE (±10%) – 5V Devices: 5.0V and 3.3V sources – 3.3V Devices: 3.3V source February 2005 For further information contact your local ST sales office. 1/9 uPSD34xx Table 1. Device Summary Part Number uPSD3422E-40T6 uPSD3422EV-40T6 uPSD3422E-40U6 uPSD3422EV-40U6 uPSD3433E-40T6 uPSD3433EV-40T6 uPSD3433E-40U6 uPSD3433EV-40U6 uPSD3434E-40T6 uPSD3434EV-40T6 uPSD3434E-40U6 uPSD3434EV-40U6 Max MHz 40 40 40 40 40 40 40 40 40 40 40 40 1st Flash (bytes) 64K 64K 64K 64K 128K 128K 128K 128K 256K 256K 256K 256K 2nd Flash 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K SRAM 4K 4K 4K 4K 8K 8K 8K 8K 8K 8K 8K 8K GPIO 35 35 46 46 35 35 46 46 35 35 46 46 8032 Bus No No Yes Yes No No Yes Yes No No Yes Yes VCC 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V VDD 5.0V 3.3V 5.0V 3.3V 5.0V 3.3V 5.0V 3.3V 5.0V 3.3V 5.0V 3.3V Pkg. TQFP52 TQFP52 TQFP80 TQFP80 TQFP52 TQFP52 TQFP80 TQFP80 TQFP52 TQFP52 TQFP80 TQFP80 Note: Operating temperature is in the Industrial range (–40°C to 85°C). SUMMARY DESCRIPTION The Turbo Plus uPSD34xx Series combines a powerful 8051-based microcontroller with a flexible memory structure, programmable logic, and a rich peripheral mix to form an ideal embedded controller. At its core is a fast 4-cycle 8032 MCU with a 4-byte instruction prefetch queue (PFQ) and a 4-entry fully associative branching cache (BC). The MCU is connected to a 16-bit internal instruction path to maximize performance, enabling loops of code in smaller localities to execute extremely fast. The 16-bit wide instruction path in the Turbo Plus Series allows double-byte instructions to be fetched from memory in a single memory cycle. This keeps the average performance near its peak performance (peak performance for 5V, 40MHz Turbo Plus uPSD34xx is 10 MIPS for single-byte instructions, and average performance will be approximately 9 MIPS for mix of single- and multibyte instructions). USB 2.0 (full speed, 12Mbps) is included, providing 10 endpoints, each with its own 64-byte FIFO to maintain high data throughput. Endpoint 0 (Control Endpoint) uses two of the 10 endpoints for In and Out directions, the remaining eight endpoints may be allocated in any mix to either type of transfers: Bulk or Interrupt. Code development is easily managed without a hardware In-Circuit Emulator by using the serial JTAG debug interface. JTAG is also used for InSystem Programming (ISP) in as little as 10 seconds, perfect for manufacturing and lab development. The 8032 core is coupled to Programmable System Device (PSD) architecture to optimize the 8032 memory structure, offering two independent banks of Flash memory that can be placed at virtually any address within 8032 program or data address space, and easily paged beyond 64K bytes using on-chip programmable decode logic. Dual Flash memory banks provide a robust solution for remote product updates in the field through In-Application Programming (IAP). Dual Flash banks also support EEPROM emulation, eliminating the need for external EEPROM chips. General purpose programmable logic (PLD) is included to build an endless variety of glue-logic, saving external logic devices. The PLD is configured using the software development tool, PSDsoft Express, available from the web at www.st.com/psm, at no charge. The uPSD34xx also includes supervisor functions such as a programmable watchdog timer and lowvoltage reset. 2/9 uPSD34xx Figure 2. Block Diagram uPSD34xx (3) 16-bit Timer/ Counters (2) External Interrupts Turbo 8032 Core PFQ & BC Programmable Decode and Page Logic 1st Flash Memory: 64K, 128K, or 256K Bytes 2nd Flash Memory: 32K Bytes SRAM: 4K or 8K Bytes P3.0:7 I2C UART0 (8) GPIO, Port A (80-pin only) (8) GPIO, Port 3 General Purpose Programmable Logic, 16 Macrocells (8) GPIO, Port B (2) GPIO, Port D (4) GPIO, Port C PA0:7 PB0:7 PD1:2 (8) 10-bit ADC Optional IrDA Encoder/Decoder SYSTEM BUS P1.0:7 (8) GPIO, Port 1 PC0:7 JTAG ICE and ISP 8032 Address/Data/Control Bus (80-pin device only) Supervisor: Watchdog and Low-Voltage Reset VCC, VDD, GND, Reset, Crystal In UART1 SPI 16-bit PCA (6) PWM, CAPCOM, TIMER MCU Bus P4.0:7 USB+, USB– (8) GPIO, Port 4 Dedicated Pins USB v2.0, Full Speed 10 FIFOs AI09695 3/9 uPSD34xx PIN DESCRIPTIONS Figure 3. TQFP52 Connections 40 P1.6/SPITXD(2)/ADC6 41 P1.7/SPISEL(2)/ADC7 47 AVCC/VREF(3) 44 RESET_IN 45 GND 46 PB5 43 PB6 42 PB7 52 PB0 51 PB1 50 PB2 49 PB3 48 PB4 PD1/CLKIN 1 PC7 2 JTAG TDO 3 JTAG TDI 4 DEBUG 5 3.3V VCC 6 USB+ 7 VDD(1) 8 GND 9 USB– 10 PC2/VSTBY 11 JTAG TCK 12 JTAG TMS 13 39 P1.5/SPIRXD(2)/ADC5 38 P1.4/SPICLK(2)/ADC4 37 P1.3/TXD1(IrDA)(2)/ADC3 36 P1.2/RXD1(IrDA)(2)/ADC2 35 P1.1/T2X(2)/ADC1 34 P1.0/T2(2)/ADC0 33 VDD(1) 32 XTAL2 31 XTAL1 30 P3.7/SCL 29 P3.6/SDA 28 P3.5/C1 27 P3.4/C0 SPISEL(2)/PCACLK1/P4.7 14 SPITXD(2)/TCM5/P4.6 15 SPIRXD(2)/TCM4/P4.5 16 SPICLK(2)/TCM3/P4.4 17 TXD1(IrDA)(2)/PCACLK0/P4.3 18 GND 19 20 T2X(2)/TCM1/P4.1 21 T2(2)/TCM0/P4.0 22 RXD0/P3.0 23 TXD0/P3.1 24 EXTINT0/TG0/P3.2 25 RXD1(IrDA)(2)/TCM2/P4.2 EXTINT1/TG1/P3.3 26 AI09696 Note: 1. For 5V applications, VDD must be connected to a 5.0V source. For 3.3V applications, VDD must be connected to a 3.3V source. 2. These signals can be used on one of two different ports (Port 1 or Port 4) for flexibility. Default is Port1. 3. AVREF and 3.3V AVCC are shared in the 52-pin package only. ADC channels must use 3.3V as AVREF for the 52-pin package. 4/9 uPSD34xx Figure 4. TQFP80 Connections 61 P1.6/SPITXD(3)/ADC6 64 P1.7/SPISEL(3)/ADC7 79 P3.2/EXINT0/TG0 75 P3.0/RXD0 77 P3.1/TXD0 68 RESET_IN 63 PSEN 72 AVCC 70 VREF 69 GND 80 PB0 78 PB1 76 PB2 74 PB3 73 PB4 71 PB5 67 PB6 66 PB7 62 WR 65 RD PD2/CSI 1 P3.3/TG1/EXINT1 2 PD1/CLKIN 3 ALE 4 PC7 5 JTAG TDO 6 JTAG TDI 7 DEBUG 8 PC4/TERR 9 3.3V VCC 10 USB+(1) 11 VDD(2) 12 GND 13 USB– 14 PC3/TSTAT 15 PC2/VSTBY 16 JTAG TCK 17 SPISEL(2)/PCACLK1/P4.7 18 SPITXD(2)/TCM5/P4.6 19 JTAG TMS 20 60 P1.5/SPIRXD(3)/ADC5 59 P1.4/SPICLK(3)/ADC4 58 P1.3/TXD1(IrDA)(3)/ADC3 57 NC 56 P1.2/RXD1(IrDA)(3)/ADC2 55 NC 54 P1.1/T2X(3)/ADC1 53 NC 52 P1.0/T2(3)/ADC0 51 NC 50 VDD(1) 49 XTAL2 48 XTAL1 47 MCU AD7 46 P3.7/SCL 45 MCU AD6 44 P3.6/SDA 43 MCU AD5 42 P3.5/C1 41 MCU AD4 PA7 21 PA6 22 SPIRXD(2)/TCM4/P4.5 23 PA5 24 SPICLK(2)/TCM3/P4.4 25 PA4 26 TXD1(IrDA)(2)/PCACLK0/P4.3 27 PA3 28 GND 29 RXD1(IrDA)(2)/TCM2/P4.2 30 T2X(2)/TCM1/P4.1 31 PA2 32 T2(2)/TCM0/P4.0 33 PA1 34 PA0 35 MCU AD0 36 MCU AD1 37 MCU AD2 38 MCU AD3 39 P3.4/C0 40 AI09697 Note: NC = Not Connected Note: 1. The USB+ pin needs a 1.5kΩ pull-up resistor. 2. For 5V applications, VDD must be connected to a 5.0V source. For 3.3V applications, VDD must be connected to a 3.3V source. 3. These signals can be used on one of two different ports (Port 1 or Port 4) for flexibility. Default is Port1. 5/9 uPSD34xx Table 2. Major Parameters Parameter Operating Voltage Operating Temperature MCU Frequency Operating Current, Typical(1) (20% of PLD used; 25°C operation. Bus control signals are blocked from the PLD in NonTurbo mode.) Idle Current, Typical (20% of PLD used; 25°C operation) Standby Current, Typical SRAM Backup Current, Typical I/O Sink/Source Current, Ports A, B, C, and D I/O Sink/Source Current, Port 4 PLD Macrocells PLD Inputs PLD Outputs PLD Propagation Delay, Typical, Turbo Mode Test Conditions/Comments – – 8MHz (min) for I2C 40MHz Crystal, Turbo 40MHz Crystal, Non-Turbo 8MHz Crystal, Turbo 8MHz Crystal, Non-Turbo 40MHz Crystal divided by 2048 internally. All interfaces are disabled. Power-down Mode needs reset to exit. If external battery is attached. VOL = 0.45V (max); VOH = 2.4V (min) VOL = 0.6V (max); VOH = 2.4V (min) For registered or combinatorial logic Inputs from pins, feedback, or MCU addresses Output to pins or internal feedback PLD input to output 5.0V Value 4.5 to 5.5 (PSD); 3.0 to 3.6 (MCU) –40 to 85 3 Min, 40 Max 79 71 32 17.7 19 3.3V Value 3.0 to 3.6 (PSD and MCU) –40 to 85 3 Min, 40 Max 63 58 24 14 18 Unit V °C MHz mA mA mA mA mA 140 0.5 IOL = 8 (max); IOH = –2 (min) IOL = 10 (max); IOH = –10 (min) 16 69 18 15 120 0.5 IOL = 4 (max); IOH = –1 (min) IOL = 10 (max); IOH = –10 (min) 16 69 18 22 µA µA mA mA – – – ns Note: 1. Operating current is measured while the uPSD34xx is executing a typical program at 40MHz. 6/9 uPSD34xx PART NUMBERING Table 3. Ordering Information Scheme Example: Device Type uPSD = Microcontroller PSD Family 34 = Turbo Plus core SRAM Size 2 = 4Kbyte 3 = 8Kbyte Main Flash Memory Size 2 = 64Kbyte 3 = 128Kbyte 4 = 256Kbyte IP Mix E = IP Mix: USB, I2C, SPI, UART (2), IrDA, ADC, Supervisor, PCA Operating Voltage blank = VCC = 4.5 to 5.5V V = VCC = 3.0 to 3.6V Speed –40 = 40MHz Package T = 52-pin TQFP U = 80-pin TQFP Temperature Range 6 = –40 to 85°C Shipping Option Tape & Reel Packing = T UPSD 34 3 4 E V – 40 U 6 T For other options, or for more information on any aspect of this device, please contact the ST Sales Office nearest you. 7/9 uPSD34xx REVISION HISTORY Table 4. Document Revision History Date 08-Nov-2004 07-Feb-2005 Version 1.0 2.0 First Edition Updated from v1.0 full datasheet Revision Details 8/9 uPSD34xx Information furnished is believed to be accurate and reliable. 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