VND7N04TR-E

VND7N04, VND7N04-1 VNK7N04FM "OMNIFET": Fully autoprotected power MOSFET Features Type Vclamp RDS(on) Ilim VND7N04 VND7N04-1 VNK7N04FM 42 V 42 V 42 V 0.14 Ω 0.14 Ω 0.14 Ω 7A 7A 7A ■ Linear current limitation ■ Thermal shut down ■ Short circuit protection ■ Integrated clamp ■ Low current drawn from input pin ■ Diagnostic feedback through input pin ■ ESD protection ■ Direct access to the gate of the power MOSFET (analog driving) ■ Compatible with standard power MOSFET Description The VND7N04, VND7N04-1 and VNK7N04FM are monolithic devices made using STMicroeletronics VIPower M0 Technology, intended for replacement of standard power MOSFETS in DC to 50 KHz applications. Built-in thermal shut-down, linear current limitation and overvoltage clamp protect the chip in harsh enviroments. Fault feedback can be detected by monitoring the voltage at the input pin. Table 1. Device summary Part number September 2013 Rev 2 Order code VND7N04 VND7N04, VND7N04-1-E, VND7N04-E, VND7N0413TR, VND7N04TR-E VND7N04-1 VND7N04-1 VNK7N04FM VNK7N04FM 1/17 www.st.com 17 Contents VND7N04, VND7N04-1, VNK7N04FM Contents 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Protection features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2/17 VND7N04, VND7N04-1, VNK7N04FM 1 Block diagram Block diagram Figure 1. Block diagram 3/17 Electrical specification VND7N04, VND7N04-1, VNK7N04FM 2 Electrical specification 2.1 Absolute maximum rating Table 2. Absolute maximum rating Value Symbol Parameter Unit DPAK SOT-82FM IPAK VDS Drain-source voltage (Vin = 0) Internally clamped V Vin Input voltage 18 V ID Drain current Internally limited A IR Reverse DC output current -7 A 2000 V Vesd Electrostatic discharge (C = 100 pF, R=1.5 KΩ) Ptot Total dissipation at Tc = 25 °C 9 W Tj Operating junction temperature Internally limited °C Tc Case operating temperature Internally limited °C -55 to 150 °C Tstg 2.2 60 Storage temperature Thermal data Table 3. Thermal data DPAK/IPAK SOT82-FM Rthj-case Thermal resistance junction-case max 3.75 14 °C/W Rthj-amb Thermal resistance junction-ambient max 100 100 °C/W 2.3 Electrical characteristics Table 4. Electrical characteristics: off (-40 < Tj < 125 °C unless otherwise specified) Symbol VCLAMP Parameter Test conditions Min. Typ. Max. Unit 42 52 V Drain-source clamp voltage ID = 200 mA Vin = 0 32 VCLTH Drain-source clamp threshold voltage ID = 2 mA Vin = 0 31 VINCL Input-source reverse clamp voltage Iin = -1 mA -1.1 IDSS Zero input voltage drain current (Vin = 0) VDS = 13 V Vin = 0 VDS = 25 V Vin = 0 IISS Supply current from input pin VDS = 0 V Vin = 10 V 4/17 V 250 -0.25 V 75 200 µA µA 550 µA VND7N04, VND7N04-1, VNK7N04FM Table 5. Symbol Electrical specification Electrical characteristics: on Parameter Test conditions VIN(th) Input threshold voltage RDS(on) Vin = 10 V ID = 3.5 A Vin = 5 V ID = 3.5 A -40 < Tj < 25 °C Static drain-source on resistance Vin = 10 V ID = 3.5 A Vin = 5 V ID = 3.5 A Tj = 125 °C Table 6. Symbol Min. VDS = Vin ID + Iin = 1 mA Typ. Max. Unit 3 V 0.14 0.28 Ω Ω 0.28 0.56 Ω Ω 0.8 Electrical characteristics: dynamic Parameter Test conditions gfs (1) Forward transconductance VDS = 13 V ID = 3.5 A Coss Output capacitance VDS = 13 V f = 1 MHz Vin = 0 Min. Typ. 2 5 Max. Unit S 250 500 pF Typ. Max. Unit 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 % Table 7. Symbol Electrical characteristics: switching Parameter Test conditions Min. td(on) tr td(off) tf Turn-on delay time Rise time Turn-off delay time Fall time VDD = 15 V Id = 3.5 A Vgen = 10 V Rgen = 10 Ω (see Figure 26) 50 60 130 50 150 180 300 200 ns ns ns ns td(on) tr td(off) tf Turn-on delay time Rise time Turn-off delay time Fall time VDD = 15 V Id = 3.5 A Vgen = 10 V Rgen = 1000 Ω (see Figure 26) 140 0.4 2.5 1 500 1.1 7 4 ns µs µs µs (di/dt)on Qi Table 8. Turn-on current slope VDD = 15 V ID = 3.5 A Vin = 10 V Rgen = 10 Ω 50 A/µs Total input charge VDD = 12 V ID = 3.5 A Vin = 10 V 18 nC Electrical characteristics: source drain diode Symbol Parameter VSD (1) Forward on voltage ISD = 3.5 A Vin = 0 Reverse recovery time Reverse recovery charge Reverse recovery current ISD = 3.5 A di/dt = 100 A/µs VDD = 30 V Tj = 25 °C (see test circuit, Figure 28) (2) trr Qrr (2) IRRM (2) Test conditions Min. Typ. 40 0.2 3.6 Max. Unit 1.7 V ns µC A 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 % 2. Parameters guaranteed by design/characterization 5/17 Electrical specification Table 9. Symbol VND7N04, VND7N04-1, VNK7N04FM Electrical characteristics: protection Parameter Test conditions Min. Typ. Max. Unit 4 4 7 7 11 11 A A 13 15 20 25 µs µs Drain current limit Vin = 10 V VDS = 13 V Vin = 5 V VDS = 13 V tdlim (1) Step response Current limit Vin = 10 V Vin = 5 V Tjsh (1) Overtemperature shutdown 150 °C Tjrs (1) Overtemperature reset 135 °C Igf (1) Fault sink current Vin = 10 V VDS = 13 V Vin = 5 V VDS = 13 V Single pulse avalanche energy starting Tj = 25°C V DD = 20 V Vin = 10 V Rgen = 1 KΩ L = 30 mH Ilim Eas (1) 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 % 6/17 50 20 0.4 mA mA J VND7N04, VND7N04-1, VNK7N04FM 3 Protection features Protection features During normal operation, the Input pin is electrically connected to the gate of the internal power MOSFET. The device then behaves like a standard power MOSFET and can be used as a switch from DC to 50 KHz. The only difference from the user’s standpoint is that a small DC current (Iiss) flows into the Input pin in order to supply the internal circuitry. The device integrates: ● Overvoltage clamp protection: internally set at 42 V, along with the rugged avalanche characteristics of the Power MOSFET stage give this device unrivalled ruggedness and energy handling capability. This feature is mainly important when driving inductive loads. ● Linear current limiter circuit: limits the drain current Id to Ilim whatever the Input pin voltage. When the current limiter is active, the device operates in the linear region, so power dissipation may exceed the capability of the heatsink. Both case and junction temperatures increase, and if this phase lasts long enough, junction temperature may reach the overtemperature threshold Tjsh. ● Overtemperature and short circuit protection: these are based on sensing the chip temperature and are not dependent on the input voltage. The location of the sensing element on the chip in the power stage area ensures fast, accurate detection of the junction temperature. Overtemperature cutout occurs at minimum 150 °C. The device is automatically restarted when the chip temperature falls below 135 °C. ● Status feedback: in the case of an overtemperature fault condition, a Status Feedback is provided through the Input pin. The internal protection circuit disconnects the input from the gate and connects it instead to ground via an equivalent resistance of 100 Ω. The failure can be detected by monitoring the voltage at the Input pin, which will be close to ground potential. Additional features of this device are ESD protection according to the Human Body model and the ability to be driven from a TTL Logic circuit (with a small increase in RDS(on)). 7/17 Protection features VND7N04, VND7N04-1, VNK7N04FM Figure 2. Thermal impedance for DPAK / IPAK Figure 3. Derating curve Figure 4. Output characteristics Figure 5. Transconductance Figure 6. Static drain-source on resistance vs input voltage Figure 7. Static drain-source on resistance (part 1/2) 8/17 VND7N04, VND7N04-1, VNK7N04FM Figure 8. Static drain-source on resistance (part 2/2) Protection features Figure 9. Input charge vs input voltage Figure 10. Capacitance variations Figure 11. Normalized input threshold voltage vs temperature Figure 12. Normalized on resistance vs temperature (part 1/2) Figure 13. Normalized on resistance vs temperature (part 2/2) 9/17 Protection features Figure 14. Turn-on current slope(part 1/2) VND7N04, VND7N04-1, VNK7N04FM Figure 15. Turn-on current slope(part 2/2) Figure 16. Turn-off drain-source voltage slope Figure 17. Turn-off drain-source voltage slope (part 1/2) (part 2/2) Figure 18. Switching time resistive load (part 1/3) 10/17 Figure 19. Switching time resistive load (part 2/3) VND7N04, VND7N04-1, VNK7N04FM Protection features Figure 20. Switching time resistive load (part 3/3) Figure 21. Current limit vs junction temperature Figure 22. Step response current limit Figure 23. Source drain diode forward characteristics 11/17 Protection features VND7N04, VND7N04-1, VNK7N04FM Figure 24. Unclamped inductive load test circuits Figure 25. Unclamped inductive waveforms Figure 26. Switching times test circuits for resistive load Figure 27. Input charge test circuit Figure 29. Waveforms Figure 28. Test circuit for inductive load switching and diode recovery times 12/17 VND7N04, VND7N04-1, VNK7N04FM 4 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 30. TO-252 (DPAK) mechanical data 13/17 Package information Figure 31. TO-251 (IPAK) mechanical data 14/17 VND7N04, VND7N04-1, VNK7N04FM VND7N04, VND7N04-1, VNK7N04FM Package information Figure 32. SOT-82FM mechanical data 15/17 Revision history 5 VND7N04, VND7N04-1, VNK7N04FM Revision history Table 10. 16/17 Document revision history Date Revision 21-Jun-2004 0.1 18-Mar-2009 1 Changes Initial release. Document reformatted. Added Table 1: Device summary on page 1. Updated Section 4: Package information on page 13 VND7N04, VND7N04-1, VNK7N04FM 5 Revision history Revision history Table 10. Document revision history Date Revision Changes 21-Jun-2004 1 Initial release. 25-Sep-2013 2 Updated Disclaimer DocID4336 Rev 2 16/17 17 VND7N04, VND7N04-1, VNK7N04FM Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. 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