VNI2140
Datasheet
Dual high-side smart power solid state relay
Features
Product status link
VNI2140J
Product label
•
•
•
•
•
•
•
•
•
•
•
•
•
Nominal current: 0.75 A per channel
Shorted-load protections
Junction overtemperature protection
Case overtemperature protection for thermal independence of the channels
Thermal case shutdown restart not simultaneous for the various channels
Protection against loss of ground
Current limitation 1 A per channel
Undervoltage shutdown
Open-load in OFF-state and short to VCC detection
Open-drain diagnostic outputs
3.3 V CMOS/TTL compatible inputs
Fast demagnetization of inductive loads
Conforms to IEC 61131-2
Applications
•
•
•
Programmable logic control
Industrial PC peripheral input/output
Numerical control machines
Description
The VNI2140J is a monolithic device designed using STMicroelectronics' VIPower
technology.
The device drives two independent resistive or inductive loads with one side
connected to ground. Active current limitation prevents a drop in system power
supply in cases of shorted-load, and built-in thermal shutdown protects the chip from
damage due to overtemperature and short-circuit.
In overload conditions, channel turns OFF and ON automatically to maintain the
junction temperature between TTSD and TR. If the case temperature reaches TCSD,
the overloaded channel is turned OFF and restarts only when case temperature
decreases down to TCR. In order to avoid high-peak current from the supply, when
more than one channel is overloaded the TCSD restart is not simultaneous. Non
overloaded channels continue to operate normally. The open-drain diagnostics output
indicates overtemperature conditions and open-load in OFF-state.
DS5977 - Rev 11 - September 2022
For further information contact your local STMicroelectronics sales office.
www.st.com
VNI2140
Block diagram
1
Block diagram
Figure 1. Block diagram
DS5977 - Rev 11
page 2/26
VNI2140
Pin connections
2
Pin connections
Figure 2. Pin connections (top view)
Table 1. Pin description
DS5977 - Rev 11
Pin
Name
1
NC
2
Type
Description
-
Not connected
Input 1
Logic input
Channel 1 input, 3.3 V CMOS/TTL compatible
3
Diag 1
Output/Open-drain
Channel 1 diagnostic in open-drain configuration
4
GND
Ground
Device ground connection
5
Diag 2
Output/Open-drain
Channel 2 diagnostic in open-drain configuration
6
Input 2
Logic input
Channel 2 input, 3.3 V CMOS/TTL compatible
7
VCC
Supply
Supply voltage
8
Output 2
Output
Channel 2 power stage output, internally protected
9
Output 2
Output
Channel 2 power stage output, internally protected
10
Output 1
Output
Channel 1 power stage output, internally protected
11
Output 1
Output
Channel 2 power stage output, internally protected
12
VCC
Supply
Supply voltage
TAB
TAB
Supply
Supply voltage
page 3/26
VNI2140
Maximum ratings
3
Maximum ratings
Table 2. Absolute maximum ratings
Symbol
Parameter
Value
Unit
45
V
V
VCC
Power supply voltage
-VCC
Reverse supply voltage
-0.3
IGND
DC ground reverse current
-250
IOUT
DC output current
IR
DC reverse output current (per channel)
IIN
Internally limited
mA
(1)
A
-5
A
Input pin current (per channel)
+/-10
mA
VIN
Input pin voltage
+VCC
V
VDIAG
Diag pin voltage
+VCC
V
IDIAG
Diag pin current
+/-10
mA
VESD
Electrostatic discharge (R = 1.5k Ω; C = 100 pF)
2000
V
EAS
Single pulse avalanche energy per channel, all channels driven
simultaneously at TAMB = 125 °C, IOUT = 1 A
300
mJ
PTOT
Power dissipation at TC = 25 °C
TJ
TSTG
Junction operating temperature
Storage temperature
Internally limited (1)
W
(1)
°C
Internally limited
-55 to 150
°C
1. Protection functions are intended to avoid IC damage in fault conditions and are not intended for continuous operation.
Continuous and repetitive operation of protection functions may reduce the IC lifetime.
DS5977 - Rev 11
page 4/26
VNI2140
Thermal data
4
Thermal data
Table 3. Thermal data
Symbol
Parameter
Rth(JC)
Thermal resistance junction-case (1)
Rth(JA)
Thermal resistance junction-ambient (2)
Value
Unit
1
°C/W
See Figure 11
°C/W
1. Per channel
2. When mounted using minimum recommended pad size on FR-4 board.
DS5977 - Rev 11
page 5/26
VNI2140
Electrical characteristics
5
Electrical characteristics
9 V < VCC < 36 V; -40 °C < TJ < 125 °C; unless otherwise specified
Table 4. Power section
Symbol
VCC
Parameter
Test conditions
Min.
Typ.
Max.
Unit
9
-
45
V
IOUT = 0.5 A at TJ = 25 °C
-
0.080
-
Ω
IOUT = 0.5 A at TJ = 125 °C
-
-
0.150
Ω
All channels in OFF-state
-
300
-
μA
ON-state with VIN = 5 V, TJ = 125 °C
-
1.9
4
mA
45
-
52
V
Supply voltage
RDS(ON)
ON-state resistance
IS
VCC supply current
VCLAMP
VCC clamp voltage
IS = 20 mA
OFF-state output voltage
VIN = 0 V, IOUT = 0 A
-
-
3
V
VIN = VOUT = 0 V
0
-
5
μA
-35
-
0
μA
-
-
0.5
mA
Min.
Typ.
Max.
Unit
VOUT(OFF)
IOUT(OFF)
IOUT(OFF1)
ILGND
OFF-state output current
Output current at GND
disconnection
VIN = 0 , VOUT = 4 V
VCC = VIN1 or VIN2 = VDIAG = VGND =
24 V; VOUT = 0 V
Table 5. Switching
Symbol
Parameter
td(ON)
Output current turn-on delay
time
-
8
-
µs
Output current rise time
-
15
-
µs
Turn-on response
-
-
35
µs
VCC = 24 V, RL = 48 Ω,
-
10
-
µs
Input rise time < 0.1 µs, TJ = 25 °C,
see Figure 6
-
7
-
µs
-
-
40
µs
Delay time for open-load
detection
-
500
-
µs
Turn-on voltage slope
-
3
-
V/µs
dV/dtm(OFF) Turn-off voltage slope
-
4
-
V/µs
Min.
Typ.
Max.
Unit
tr
td(ON) + tr
td(OFF)
tf
td(OFF) + tf
tDOL
dV/dt(ON)
Output current turn-off delay
time
Output current fall time
Turn-off response
Test conditions
Table 6. Logic inputs
Symbol
Test conditions
VIL
Input low level voltage
-
-
0.8
V
VIH
Input high level voltage
2.20
-
-
V
VI(HYST)
Input hysteresis voltage
-
0.15
-
V
VIN = 15 V
-
-
10
VIN = 36 V
-
-
210
IIN
DS5977 - Rev 11
Parameter
Input current
µA
page 6/26
VNI2140
Electrical characteristics
Table 7. Protection and diagnostic
Symbol
VDIAG
(1)
Parameter
Test conditions
Min.
Typ.
Max.
Unit
-
-
0.6
V
IDIAG = 1.5 mA (fault condition)
Diag voltage output low
VUSD
Undervoltage protection
7
-
9
V
VUSDHYS
Undervoltage hysteresis
0.4
0.5
-
V
ILIM
DC short-circuit current
VCC = 24 V, RLOAD ≤ 10 mΩ
1
-
2
A
Diag leakage current
VCC = 32 V
-
30
-
μA
2
3
4
V
ILDIAG
VOL
Open-load OFF-state voltage
VIN = 0 V
detection threshold
TTSD
Junction shutdown
temperature
150
170
-
°C
TR
Junction reset temperature
135
155
200
°C
THYST
Junction thermal hysteresis
7
15
-
°C
TCSD
Case shutdown temperature
125
139
146
°C
TCR
Case reset temperature
110
-
-
°C
TCHYST
Case thermal hysteresis
7
15
-
°C
VDEMAG
Output voltage at turn-OFF
VCC - 45
VCC - 50
VCC - 52
V
IOUT = 0.5 A; LLOAD ≥ 1 mH
1. Diag determination > 100 ms after the switching edge.
Figure 3. Current and voltage conventions
DS5977 - Rev 11
page 7/26
VNI2140
Truth table
6
Truth table
Table 8. Truth table
Inputn
Outputn
Diagn
L
L
H
H
H
H
L
L
H
H
L
L
L
L
X
H
L
X
Shorted-load
L
L
H
(current limitation)
H
X
H
L
Z(1)
L
H
H
H
L
H
L
H
H
H
Condition
Normal operation
Overtemperature
Undervoltage
Output voltage > VOL
Short to VCC
1. Depending on the external circuit.
Note:
DS5977 - Rev 11
X = don't care.
page 8/26
VNI2140
Switching waveforms
7
Switching waveforms
Figure 4. Switching waveforms
DS5977 - Rev 11
page 9/26
VNI2140
Switching waveforms
Figure 5. Switching waveforms (continued)
DS5977 - Rev 11
page 10/26
VNI2140
Switching waveforms
Figure 6. Switching parameter test conditions
Figure 7. Typical application circuit
DS5977 - Rev 11
page 11/26
VNI2140
Open-load
8
Open-load
In order to detect the open-load fault, a pull-up resistor must be connected between the VCC line and the output
pin.
In a normal condition, a current flows through the network made up of a pull-up resistor and a load. The voltage
across the load is less than VOLMIN and the DIAG pin is kept high.
This is the result in the condition:
Equation 1:
VCC [RLOAD / ( RLOAD + RPU )] < VOLMIN
or
Equation 2:
[(VCC / VOLMIN) - 1] RLOAD < RPU
When an open-load event occurs the voltage on the output pin rises to a value higher than VOLMAX (depending on
the pull-up resistor) and the diag pin goes down.
This is the result in the condition:
Equation 3:
RPU < (VCC - VOLMAX) / |IOUT(OFF1)MIN|
Figure 8. Open-load detection
DS5977 - Rev 11
page 12/26
VNI2140
Open-load
Figure 9. Turn-on/off to open-load
DS5977 - Rev 11
page 13/26
VNI2140
Package and PCB thermal
9
data
Package and PCB thermal data
Figure 10. PowerSSO-12 PC board
Figure 11. RthJA vs. PCB copper area in open box free-air condition
DS5977 - Rev 11
page 14/26
VNI2140
Package and PCB thermal
data
Figure 12. PowerSSO-12 thermal impedance junction ambient single pulse
Pulse calculation formula:
ZTHδ = RTH x δ + ZTHtp (1 - δ)
where δ = tp / T
Figure 13. Thermal fitting model of a double channel HSD in PowerSSO-12
DS5977 - Rev 11
page 15/26
VNI2140
Package and PCB thermal
data
Table 9. Thermal parameter
DS5977 - Rev 11
Area/island (cm2)
Footprint
2
8
R1 (°C/W)
0.1
-
-
R2 (°C/W)
0.2
-
-
R3 (°C/W)
7
-
-
R4 (°C/W)
10
10
9
R5 (°C/W)
22
15
10
R6 (°C/W)
26
20
15
C1 (W.s/°C)
0.0001
-
-
C2 (W.s/°C)
0.002
-
-
C3 (W.s/°C)
0.05
-
-
C4 (W.s/°C)
0.2
0.1
0.1
C5 (W.s/°C)
0.27
0.8
1
C6 (W.s/°C)
3
6
9
page 16/26
VNI2140
Reverse polarity protection
10
Reverse polarity protection
Reverse polarity protection can be implemented on-board using two different solutions:
1.
Placing a resistor (RGND) between IC GND pin and load GND
2.
Placing a diode between IC GND pin and load GND
If option 1 is selected, the minimum resistance value has to be selected according to the following equation:
RGND ≥ VCC / IGND
where IGND is the DC reverse ground pin current and can be found in Section 3 of this datasheet.
Power dissipated by RGND (when VCC < 0: during reverse polarity situations) is:
PD = (VCC)2 / RGND
If option 2 is selected, the diode has to be chosen by taking into account VRRM >|VCC| and its power dissipation
capability:
PD ≥ IS x VF
Note:
In normal conditions (no reverse polarity), due to the diode, there is a voltage drop between GND of the device
and GND of the system.
Figure 14. Reverse polarity protection
This schematic can be used with any type of load.
DS5977 - Rev 11
page 17/26
VNI2140
Package information
11
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages,
depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product
status are available at: www.st.com. ECOPACK is an ST trademark.
11.1
PowerSSO-12™ package information
Figure 15. PowerSSO-12™ package outline
DS5977 - Rev 11
page 18/26
VNI2140
PowerSSO-12™ package
information
Table 10. PowerSSO 12, mechanical data
Symbol
Dimensions [mm]
Min.
Typ.
Max.
A
1.250
-
1.620
A1
0.000
-
0.100
A2
1.100
-
1.650
B
0.230
-
0.410
C
0.190
-
0.250
D
4.800
-
5.000
E
3.800
-
4.000
e
-
0.800
-
H
5.800
-
6.200
h
0.250
-
0.500
L
0.400
-
1.270
k
0°
-
8°
X
1.900
-
2.500
Y
3.600
-
4.200
ddd
-
-
0.100
Figure 16. Suggested footprint
STMicroelectronics is not responsible for any PCB related issues. The footprint shown in the above figure is a
suggestion, which might not be in line with the customer PCB supplier design rules.
DS5977 - Rev 11
page 19/26
VNI2140
PowerSSO-12™ packing
12
information
PowerSSO-12™ packing information
Figure 17. PowerSSO-12™ tube shipment (no suffix)
Figure 18. PowerSSO-12™ tape and reel shipment (suffix “TR”)
DS5977 - Rev 11
page 20/26
VNI2140
Ordering information
13
Ordering information
Table 11. Ordering information
Part number
VNI2140J
VNI2140JTR
DS5977 - Rev 11
Package
PowerSSO-12
Packaging
Tube
Tape and reel
page 21/26
VNI2140
Revision history
Table 12. Document revision history
DS5977 - Rev 11
Date
Version
Changes
16-Dec-2008
1
Initial release.
29-Apr-2009
2
Updated Table 5 on page 6
03-Jul-2009
3
Updated features in cover page and Table 5 on page 6
27-Aug-2009
4
Updated Section 9: Reverse polarity protection
25-Mar-2010
5
Updated Cover page and Table 4 on page 5
26-Apr-2010
6
Updated Table 5 on page 6
21-Jul-2010
7
Updated Table 8 on page 7
15-Nov-2011
8
Updated Figure 18 on page 21
09-Nov-2017
9
Updated Table 4 on page 5 and Table 7 on page 6. Minor modifications
throughout document.
10-Dec-2019
10
Updated Section 9: Reverse polarity protection
13-Sep-2022
11
DS format changed; table 9: TCSD values (Typ. and Max.) changed. Reduced
the maximum value of ILGND. Other minor text changes.
page 22/26
VNI2140
Contents
Contents
1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
2
Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
3
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
4
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
5
Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
6
Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
7
Switching waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
8
Open-load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
9
Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
10
Reverse polarity protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
11
Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
11.1
PowerSSO-12™ package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
12
PowerSSO-12™ packing information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
13
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
List of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
List of figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
DS5977 - Rev 11
page 23/26
VNI2140
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Pin description . . . . . . . . . . . .
Absolute maximum ratings . . . .
Thermal data. . . . . . . . . . . . . .
Power section . . . . . . . . . . . . .
Switching . . . . . . . . . . . . . . . .
Logic inputs. . . . . . . . . . . . . . .
Protection and diagnostic . . . . .
Truth table . . . . . . . . . . . . . . .
Thermal parameter. . . . . . . . . .
PowerSSO 12, mechanical data
Ordering information. . . . . . . . .
Document revision history . . . . .
DS5977 - Rev 11
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page 24/26
VNI2140
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
DS5977 - Rev 11
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current and voltage conventions. . . . . . . . . . . . . . . . . . . . . . .
Switching waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switching waveforms (continued) . . . . . . . . . . . . . . . . . . . . . .
Switching parameter test conditions . . . . . . . . . . . . . . . . . . . .
Typical application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Open-load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Turn-on/off to open-load. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PowerSSO-12 PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RthJA vs. PCB copper area in open box free-air condition . . . . . .
PowerSSO-12 thermal impedance junction ambient single pulse.
Thermal fitting model of a double channel HSD in PowerSSO-12
Reverse polarity protection. . . . . . . . . . . . . . . . . . . . . . . . . . .
PowerSSO-12™ package outline . . . . . . . . . . . . . . . . . . . . . .
Suggested footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PowerSSO-12™ tube shipment (no suffix) . . . . . . . . . . . . . . . .
PowerSSO-12™ tape and reel shipment (suffix “TR”) . . . . . . . .
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. 2
. 3
. 7
. 9
10
11
11
12
13
14
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15
15
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18
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20
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page 25/26
VNI2140
IMPORTANT NOTICE – READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST
products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST
products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgment.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of
purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. For additional information about ST trademarks, refer to www.st.com/trademarks. All other product or service names
are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2022 STMicroelectronics – All rights reserved
DS5977 - Rev 11
page 26/26
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