VNW100N04

VNW100N04 "OMNIFET": FULLY AUTOPROTECTED POWER MOSFET Table 1. General Features Figure 1. Package Type Vclamp RDS(on) Ilim VNW100N04 42 V 0.012 Ω 100 A ■ LINEAR CURRENT LIMITATION ■ THERMAL SHUT DOWN ■ SHORT CIRCUIT PROTECTION ■ INTEGRATED CLAMP ■ LOW CURRENT DRAWN FROM INPUT PIN ■ DIAGNOSTIC FEEDBACK THROUGH INPUT PIN c u d ■ ESD PROTECTION ■ DIRECT ACCESS TO THE GATE OF THE POWER MOSFET (ANALOG DRIVING) ■ COMPATIBLE WITH STANDARD POWER MOSFET ■ STANDARD TO-247 PACKAGE (s) t c u od ) s t( e t le o s b -O l o bs o r P ) s t( c u d o r 3 2 1 P e et TO-247 O ) DESCRIPTION The VNW100N04, is a monolithic device made using STMicroelectronics VIPower M0 Technology, intended for replacement of standard power MOSFETS in DC to 50 KHz applications. Built-in thermal shut-down, linear current limitation and overvoltage clamp protect the chip in harsh enviroments. Fault feedback can be detected by monitoring the voltage at the input pin. r P e t e l o s ( t c u d o r eP s b t O e l o s b O Table 2. Order Codes Package Tube Tape and Reel TO-247 VNW100N04 – REV. 2 June 2004 1/12 VNW100N04 Figure 2. Block Diagram ) s t( c u d e t le o s b Table 3. Absolute Maximum Ratings Symbol VDS Parameter Drain-Source Voltage (Vin = 0) O ) Input Voltage ID Drain Current IR Reverse DC Output Current ) s t( c u d o r eP let o s b s ( t c O u d ) o r s ( t P c e u t d e l o r o s P b e t O e l o s b O VIN o r P Value Unit Internally Clamped V 18 V Internally Limited A –100 A Vesd Electrostatic Discharge (C = 100 pF, R =1.5 KΩ) 2000 V Ptot Total Dissipation at Tc = 25 °C 208 W Tj Operating Junction Temperature Internally Limited °C Tc Case Operating Temperature Internally Limited °C -55 to 150 °C Value Unit Tstg Storage Temperature Table 4. Thermal Data Symbol Parameter Rthj-case Thermal Resistance Junction-case Max 0.6 °C/W Rthj-amb Thermal Resistance Junction-ambient Max 30 °C/W 2/12 VNW100N04 ELECTRICAL CHARACTERISTICS (Tcase = 25°C unless otherwise specified) Table 5. Off Symbol VCLAMP Parameter Test Conditions Min. Typ. Max. Unit 42 48 V Drain-source Clamp Voltage ID = 50 A; Vin = 0 36 VCLTH Drain-source Clamp Threshold Voltage ID = 2 mA; Vin = 0 35 VINCL Input-Source Reverse Clamp Voltage Iin = –1 mA –1 IDSS Zero Input Voltage Drain Current (Vin = 0) VDS = 13 V; Vin = 0 VDS = 25 V; Vin = 0 IISS Supply Current from Input Pin VDS = 0 V; Vin = 10 V 250 Table 6. On (1) Symbol Parameter Test Conditions VIN(th) Input Threshold Voltage VDS = Vin; ID + Iin = 1 mA RDS(on) Static Drain-source On Resistance Vin = 10 V; ID = 50 A Vin = 5 V; ID = 50 A Table 7. Dynamic Symbol gfs (2) Parameter Forward Transconductance ) s ( t -O l o bs Test Conditions VDS = 13 V; ID = 50 A Output Capacitance o r P 0.8 Typ. Min. Typ. 40 60 VDS = 13 V; f = 1 MHz; Vin = 0 V 50 200 µA µA 500 µA ) s t( ) s t( Max. Unit 3 V c u d o r P e et c O u d ) o r s ( t P c e u t d e l o r o s P b e t O e l o s b O Coss –0.3 c u d Min. e t le o s b Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 % V 0.012 0.015 Ω Ω Max. Unit S 2000 3000 pF Typ. Max. Unit Note: 2. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. Table 8. Switching (3) Symbol td(on) tr td(off) tf td(on) tr td(off) tf (di/dt)on Qi Parameter Test Conditions Min. Turn-on Delay Time VDD = 15 V; Id = 50 A; 110 250 ns Rise Time Vgen = 10V; Rgen = 10 Ω 500 900 ns Turn-off Delay Time (see Figure 27) 1000 1800 ns 600 1000 ns Fall Time Turn-on Delay Time VDD = 15 V; Id = 50 A; 2.2 3.5 µs Rise Time Vgen = 10V; Rgen = 1000 Ω 3.5 6 µs Turn-off Delay Time (see Figure 27) 22 30 µs 12 18 µs Fall Time Turn-on Current Slope VDD = 15 V; ID = 50 A Vin = 10 V; Rgen = 10 Ω 55 A/µS Total Input Charge VDD = 15 V; ID = 50 A; Vin = 10 V 190 nC Note: 3. Parameters guaranteed by design/characterization. 3/12 VNW100N04 ELECTRICAL CHARACTERISTICS (cont’d) Table 9. Source Drain Diode Symbol Parameter Test Conditions Forward On Voltage ISD = 50 A; Vin = 0 trr (5) Reverse Recovery Time Qrr (5) Reverse Recovery Charge ISD = 50 A; di/dt = 100 A/µs VDD = 30 V; Tj = 25 °C (see test circuit, Figure 29) IRRM(5) Reverse Recovery Current VSD(4) Min. Typ. Max. Unit 1.6 V 800 ns 5 µC 15 A Note: 4. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 % 5. Parameters guaranteed by design/characterization. ) s t( Table 10. Protection Symbol Ilim Parameter Test Conditions Drain Current Limit Vin = 10 V; VDS = 13 V Vin = 5 V; VDS = 13 V tdlim(6) Step Response Current Limit Vin = 10 V Vin = 5 V Tjsh(6) Overtemperature Shutdown Tjrs(6) Overtemperature Reset Igf(6) Fault Sink Current Vin = 10 V; VDS = 13 V Vin = 5 V; VDS = 13 V Eas(6) Single Pulse Avalanche Energy starting Tj = 25 °C; VDD = 20 V Vin = 10 V; Rgen = 1 KΩ; L = 10 mH t c u -O PROTECTION FEATURES During normal operation, the Input pin is electrically connected to the gate of the internal power MOSFET. The device then behaves like a standard power MOSFET and can be used as a switch from DC to 50 KHz. The only difference from the user’s standpoint is that a small DC current (I iss) flows into the Input pin in order to supply the internal circuitry. The device integrates: – OVERVOLTAGE CLAMP PROTECTION: internally set at 42V, along with the rugged avalanche characteristics of the Power MOSFET stage give this device unrivalled ruggedness and energy handling capability. This feature is mainly important when driving inductive loads. – LINEAR CURRENT LIMITER CIRCUIT: limits the drain current Id to Ilim whatever the Input pin voltage. When the current limiter is active, the device operates in the linear region, so power dissipation may exceed the capability of the heatsink. Both case and junction temperatures increase, and if this phase lasts long enough, junction temperature may reach the overtemperature threshold Tjsh. od r P e t e l o s b t O e l o s b O o r eP 4/12 l o bs O ) s ( t c u d Max. Unit 50 50 65 65 A A 50 130 80 200 eP bs (s) Typ. 35 35 d o r t e l o Note: 6. Parameters guaranteed by design/characterization. uc Min. 170 c u d o r 155 P e et 4 ) s t( 50 20 µs µs °C °C mA mA J – OVERTEMPERATURE AND SHORT CIRCUIT PROTECTION: these are based on sensing the chip temperature and are not dependent on the input voltage. The location of the sensing element on the chip in the power stage area ensures fast, accurate detection of the junction temperature. Overtemperature cutout occurs at minimum 170°C. The device is automatically restarted when the chip temperature falls below 155°C. – STATUS FEEDBACK: In the case of an overtemperature fault condition, a Status Feedback is provided through the Input pin. The internal protection circuit disconnects the input from the gate and connects it instead to ground via an equivalent resistance of 100 Ω. The failure can be detected by monitoring the voltage at the Input pin, which will be close to ground potential. Additional features of this device are ESD protection according to the Human Body model and the ability to be driven from a TTL Logic circuit (with a small increase in RDS(on)). VNW100N04 Figure 3. Thermal Impedance Figure 4. Derating Curve ) s t( c u d Figure 5. Output Characteristics e t le o s b -O (s) t c u od r P e t e l o bs O ) s t( l o bs c u d o r P e et O ) s ( t c u d o r eP o r P Figure 6. Transconductance Figure 7. Static Drain-Source On Resistance vs Input Voltage Figure 8. Static Drain-Source On Resistance t e ol s b O 5/12 VNW100N04 Figure 9. Static Drain-Source On Resistance Figure 10. Input Charge vs Input Voltage ) s t( c u d Figure 11. Capacitance Variations e t le o s b -O (s) t c u od r P e t e l o Figure 13. Normalized On Resistance vs Temperature s b t O e l o s b O 6/12 ) s t( l o bs c u d o r P e et O ) s ( t c u d o r eP o r P Figure 12. Normalized Input Threshold Voltage vs Temperature Figure 14. Normalized On Resistance vs Temperature VNW100N04 Figure 15. Turn-on Current Slope Figure 16. Turn-on Current Slope ) s t( Figure 17. Turn-off Drain-Source Voltage Slope c u d e t le o s b -O (s) t c u od r P e t e l o o r eP s b t O e l o s b O ) s t( l o bs c u d o r P e et O ) s ( t c u d Figure 19. Switching Time Resistive Load o r P Figure 18. Turn-off Drain-Source Voltage Slope Figure 20. Switching Time Resistive Load 7/12 VNW100N04 Figure 21. Switching Time Resistive Load Figure 22. Current Limit vs Junction Temperature ) s t( c u d Figure 23. Step Response Current Limit e t le o s b -O (s) od t c u r P e t e l o s b t O e l o s b O 8/12 l o bs O ) s ( t c u d o r eP o r P ) s t( Figure 24. Source Drain Diode Forward Characteristics P e et c u d o r VNW100N04 Figure 25. Unclamped Inductive Load Test Circuits Figure 26. Unclamped Inductive Waveforms ) s t( Figure 27. Switching Times Test Circuits For Resistive Load c u d e t le o s b -O (s) t c u od r P e t e l o o r eP s b t O e l o s b O ) s t( l o bs c u d o r P e et O ) s ( t c u d Figure 29. Test Circuit For Inductive Load Switching And Diode Recovery Times o r P Figure 28. Input Charge Test Circuit Figure 30. Waveforms 9/12 VNW100N04 PACKAGE MECHANICAL Table 11. TO-247 Mechanical Data millimeters Symbol Min Typ Max A 4.85 5.15 A1 2.20 2.60 b 1.0 1.40 b1 2.0 2.40 b2 3.0 3.40 0.40 0.80 19.85 20.15 E 15.45 uc 15.75 e d o r 5.45 L 14.20 L1 3.70 18.50 ∅P 3.55 ∅R 4.50 S Package Weight ) (s s b O od r P e t e l o O ) s ( t c u d o r eP s b t O e l o s b O P025P Note: Drawing is not to scale. 4.30 c u d o r P e et Gr. 4.43 ) s t( 14.80 3.65 5.50 5.50 l o bs Figure 31. TO-247 Package Dimensions t c u eP t e l o L2 10/12 ) s t( c D VNW100N04 REVISION HISTORY Table 12. Revision History Date Revision Description of Changes September-1996 1 First Issue 18-June-2004 2 Stylesheet update. No content change. ) s t( c u d e t le o s b (s) -O od t c u r P e t e l o l o bs o r P ) s t( c u d o r P e et O ) s ( t c u d s b t O e l o s b O o r eP 11/12 VNW100N04 ) s t( c u d e t le o s b (s) -O t c u od r P e t e l o l o bs o r P ) s t( c u d o r P e et O ) s ( t c u d s b t O e l o s b O o r eP Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners © 2005 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States www.st.com 12/12