S24163S2.7T

SUMMIT MICROELECTRONICS , I nc. S24163 3 and 5 Volt Systems Precision RESET Controller with 16K I2C Memory FEATURES • Precision Supply Voltage Monitor — Active Low — Integrated memory write lockout • Guaranteed RESET (RESET#) assertion to VCC = 1V • Power-Fail Accuracy Guaranteed • No External Components • 3V and 5V system versions • Low Power CMOS — Active current less than 3mA — Standby current less than 25µA • Memory Internally Organized 2k X 8 — Two Wire Serial Interface (I2C™) – Bidirectional data transfer protocol – Standard 100KHz and Fast 400KHz • • High Reliability — Endurance: 100,000 erase/write cycles — Data retention: 100 years 8-Pin SOIC Packages OVERVIEW The S24163 is a power supervisory device with 16,384bits of serial E2PROM. It is fabricated using SUMMIT's advanced CMOS E2PROM technology and is suitable for both 3 and 5 volt systems. The S24163 is internally organized as 2048 x 8. It features the I2C serial interface and software protocol allowing operation on a simple two-wire bus. BLOCK DIAGRAM VCC 8 5kHz OSCILLATOR RESET PULSE GENERATOR 2 RESET# + – VTRIP RESET CONTROL 1.26V SCL SDA 6 5 MODE DECODE ADDRESS DECODER WRITE CONTROL DATA I/O E2PROM MEMORY ARRAY 4 2014 T BD 2.0 GND SUMMIT MICROELECTRONICS, Inc. • 300 Orchard City Drive, Suite 131 • Campbell, CA 95008 • Telephone 408-378-6461 • Fax 408-378-6586 • www.summitmicro.com © SUMMIT MICROELECTRONICS, Inc. 2000 2014 2.1 8/2/00 Characteristics subject to change without notice 1 S24163 PIN CONFIGURATION ENDURANCE AND DATA RETENTION The S24163 is designed for applications requiring up to 100,000 erase/write cycles and unlimited read cycles. It provides 100 years of secure data retention, with or without power applied, after the execution of 100,000 erase/write cycles. APPLICATIONS SMS24163 8-Pin PDIP or 8-Pin SOIC NC RESET# NC VSS 1 2 3 4 8 7 6 5 VCC NC SCL SDA 2014 T PCon 2.0 The S24163 is ideal for applications requiring low voltage and low power consumption. This device provides microcontroller RESET control and can be manually resettable. This device also uses a cost effective, spacesaving, 8-pin SOIC or PDIP plastic package. Typical applications include alarm devices, electronic locks, meters, keys, pagers and cellular phones. RESET CONTROLLER DESCRIPTION The device provides a precise reset output to a microcontroller and it’s associated circuitry ensuring correct system operation during power-up/down conditions and brownout situations. The output is open drain, allowing control of the reset function by multiple devices. During power-up the reset output remains in a fixed active state until VCC passes through the reset threshold and remains above the threshold for 200ms. The reset output is valid whenever VCC ≥ 1V. If VCC falls below the threshold for more than tGLITCH the device will immediately generate a reset and drive the output. The reset pin is an I/O; therefore, forcing the pin to the active state can also manually reset the device. Because the I/O needs to be an open drain, the internal timer can only be triggered by the leading edge of the input. The resulting reset output will either be tPURST, or the externally applied reset signal, whichever is longer. This can provide an affective debounce or reset signal extender solution. CHARACTERISTICS OF THE I2C BUS General Description The I2C bus was designed for two-way, two-line serial communication between different integrated circuits. The two lines are a serial data line (SDA), and a serial clock line (SCL). The SDA line must be connected to a positive supply by a pull-up resistor, located somewhere on the bus (See Figure 1). Data transfer between devices may be initiated with a START condition only when SCL and SDA are HIGH (bus is not busy). PIN DESCRIPTIONS SCL — Serial Clock: The SCL input is used to clock data into and out of the device. In the WRITE mode data must remain stable while SCL is HIGH. In the READ mode data is clocked out on the falling edge of SCL. SDA — Serial Data: The SDA pin is a bidirectional pin used to transfer data into and out of the device. Data may change only when SCL is LOW, except START and STOP conditions. It is an open-drain output and may be wireORed with any number of open-drain or open-collector outputs. RESET# — Reset: This is an active low open drain output. It is driven low whenever VCC is below VTRIP. It is also an input and can be used to debounce a switch input or perform signal conditioning. The pin has an internal pull-up and should be left unconnected if the signal is not used in the system. However, an external pull-up resistor must be connected when the pin is tied to a system RESET# line. VCC — Power: VCC is the voltage input, typically 2.7 to 5.5 volts. GND — Ground: Power return. NC — No Connect: The no connect inputs are not used. However, to ensure proper operation, they can be unconnected or tied to ground. They must not be tied to VCC. 2014 2.1 8/2/00 2 S24163 VCC SDA RESET SCL Master Transmitter/ Receiver Slave Transmitter/ Receiver Master Transmitter/ Receiver Slave Receiver Master Transmitter (24163) FIGURE 1. TYPICAL SYSTEM CONFIGURATION (µC/ µP) 2014 T fig01 2.0 SCL Data must remain stable while clock is HIGH. Change of data allowed Data must remain stable while clock is HIGH. SDA In tHD:DAT tSU:DAT tHD:DAT 2014 ILL4 1.0 FIGURE 2. INPUT DATA PROTOCOL SCL START Condition STOP Condition SDA In 2014 ILL5 1.0 FIGURE 3. START AND STOP CONDITIONS 2014 2.1 8/2/00 3 S24163 SCL from Master Data Output from Transmitter Data Output from Receiver Start Condition 1 8 9 tAA tAA ACKnowledge 2014 ILL6 1.0 FIGURE 4. ACKNOWLEDGE RESPONSE FROM RECEIVER Input Data Protocol One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during clock HIGH time, because changes on the data line while SCL is HIGH will be interpreted as start or stop condition (See Figure 2). START and STOP Conditions When both the data and clock lines are HIGH, the bus is said to be not busy. A HIGH-to-LOW transition on the data line, while the clock is HIGH, is defined as the “START” condition. A LOW-to-HIGH transition on the data line, while the clock is HIGH, is defined as the “STOP” condition (See Figure 3). DEVICE OPERATION The S24163 is a 16,384-bit serial E2PROM. The device supports the I2C bidirectional data transmission protocol. The protocol defines any device that sends data onto the bus as a “transmitter” and any device which receives data as a “receiver.” The device controlling data transmission is called the “master” and the controlled device is called the “slave.” Since it never initiates any data transfers the S24163 is always a “slave” device. Acknowledge (ACK) Acknowledge is a software convention used to indicate successful data transfers. The transmitting device, either the master or the slave, will release the bus after transmitting eight bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to ACKnowledge that it received the eight bits of data (See Figure 4). The S24163 will respond with an ACKnowledge after recognition of a START condition and its slave address byte. If both the device and a write operation are selected, the S24163 will respond with an ACKnowledge after the receipt of each subsequent 8-bit word. In the READ mode the S24163 transmits eight bits of data, then releases the SDA line, and monitors the line for an ACKnowledge signal. If an ACKnowledge is detected, and no STOP condition is generated by the master, the S24163 will continue to transmit data. If an ACKnowledge is not detected the S24163 will terminate further data transmissions and await a STOP condition before returning to the standby power mode. Device Addressing Following a start condition the master must output the address of the slave it is accessing. The most significant four bits of the slave address are the device type identifier (see figure 5). For the S24163 this is fixed as 1010[BHEX]. Word Address The next three bits of the slave address are an extension of the array’s address and are concatenated with the eight bits of address in the word address field, providing direct access to the 2,048 X 8 array. Read/Write Bit The last bit of the data stream defines the operation to be performed. When set to “1” a read operation is selected; when set to “0” a write operation is selected. DEVICE IDENTIFIER HIGH ORDER WORD ADDRESS 1 0 1 0 A10 A9 A8 R/W 2014 ILL7 1.0 FIGURE 5. SLAVE ADDRESS BYTE 2014 2.1 8/2/00 4 S24163 WRITE OPERATIONS The S24163 allows two types of write operations: byte write and page write. The byte write operation writes a single byte during the nonvolatile write period (tWR). The page write operation allows up to 16 bytes in the same page to be written during tWR. Byte WRITE After the slave address is sent (to identify the slave device, specify high order word address and a read or write operation), a second byte is transmitted which contains the low 8 bit addresses of any one of the 2,048 words in the array. Upon receipt of the word address, the S24163 responds with an ACKnowledge. After receiving the next byte of data, it again responds with an ACKnowledge. The master then terminates the transfer by generating a STOP condition, at which time the S24163 begins the internal write cycle. While the internal write cycle is in progress, the S24163 inputs are disabled, and the device will not respond to any requests from the master. Refer to Figure 6 for the address, ACKnowledge and data transfer sequence. Page WRITE The S24163 is capable of a 16-byte page write operation. It is initiated in the same manner as the byte-write operation, but instead of terminating the write cycle after the first data word, the master can transmit up to 15 more words of data. After the receipt of each word, the S24163 will respond with an ACKnowledge. The S24163 automatically increments the address for subsequent data words. After the receipt of each word, the four low order address bits are internally incremented by one. The high order five bits of the address byte remain constant. Should the master transmit more than sixteen words, prior to generating the STOP condition, the address counter will “roll over,” and the previously written data will be overwritten. As with the byte-write operation, all inputs are disabled during the internal write cycle. Refer to Figure 6 for the address, ACKnowledge and data transfer sequence. Acknowledges Transmitted from 24163 to Master Receiver If single byte-write only, Stop bit issued here. Acknowledges Transmitted from 24163 to Master Receiver SDA Bus Activity 1010 A AAR 10 9 8 W A C Word Address K AAAAAAAA 76543210 A C K Data Byte n A C K A Data Byte n+1 C K DDDDDDDD 76543210 Data Byte n+15 C K DDDDDDDD 76543210 A 0 DDDDDDDD 76543210 S T Device A10,A9,A8 Type A R Address Read/Write T 0= Write S T O P Slave Address Master Sends Read Request to Slave Master Writes Word Address to Slave Master Writes Data to Slave Master Writes Data to Slave Master Writes Data to Slave Master Transmitter to Slave Receiver Master Transmitter to Slave Receiver Master Transmitter to Slave Receiver Master Transmitter to Slave Receiver Master Transmitter to Slave Receiver Slave Transmitter to Master Receiver 2014 T fig06 2.0 Slave Transmitter to Master Receiver Slave Transmitter to Master Receiver Slave Transmitter to Master Receiver Slave Transmitter to Master Receiver Shading Denotes 24163 SDA Output Active FIGURE 6. PAGE/BYTE WRITE MODE 2014 2.1 8/2/00 5 S24163 Acknowledge Polling When the S24163 is performing an internal WRITE operation, it will ignore any new START conditions. Since the device will only return an acknowledge after it accepts the START, the part can be continuously queried until an acknowledge is issued, indicating that the internal WRITE cycle is complete. To poll the device, give it a START condition, followed by a slave address for a WRITE operation (See Figure 7). READ OPERATIONS Read operations are initiated with the R/W bit of the identification field set to “1.” There are four different read options: 1. 2. 3. 4. Current Address Byte Read Random Address Byte Read Current Address Sequential Read Random Address Sequential Read Internal WRITE Cycle In Progress; Begin ACK Polling Issue Start Issue Slave Address and R/W = 0 Issue Stop ACK Returned? No Yes (Internal WRITE Cycle is completed) Next operation a WRITE? Yes Issue Byte Address Issue Stop No Current Address Byte Read The S24163 contains an internal address counter which maintains the address of the last word accessed, incremented by one. If the last address accessed (either a read or write) was to address location n, the next read operation would access data from address location n+1 and increment the current address pointer. When the S24163 receives the slave address field with the R/W bit set to “1,” it issues an acknowledge and transmits the 8-bit word stored at address location n+1. The current address byte read operation only accesses a single byte of data. The master does not acknowledge the transfer, but does generate a stop condition. At this point, the S24163 discontinues data transmission. See Figure 8 for the address acknowledge and data transfer sequence. Proceed with WRITE Await Next Command 2014 ILL 9 1.0 FIGURE 7. ACKNOWLEDGE POLLING SDA Bus Activity 1 A AAR 10 9 8 W A C K Data Byte 1010 1 DDDDDDDD 76543210 1 S T O P S T Device Type A10,A9,A8 A Address Read/Write R 1= Read T Slave Address Master sends Read request to Slave Lack of ACK (low) from Master determines last data byte to be read Slave sends Data to Master Slave Transmitter to Master Receiver Master Transmitter to Slave Receiver Shading Denotes 24163 SDA Output Active 2014 T fig08 2.0 FIGURE 8. CURRENT ADDRESS BYTE READ MODE 2014 2.1 8/2/00 6 S24163 Random Address Byte Read Random address read operations allow the master to access any memory location in a random fashion. This operation involves a two-step process. First, the master issues a write command which includes the start condition and the slave address field (with the R/W bit set to WRITE) followed by the address of the word it is to read. This procedure sets the internal address counter of the S24163 to the desired address. After the word address acknowledge is received by the master, the master immediately reissues a start condition followed by another slave address field with the R/W bit set to READ. The S24163 will respond with an acknowledge and then transmit the 8-data bits stored at the addressed location. At this point, the master does not acknowledge the transmission but does generate the stop condition. The S24163 discontinues data transmission and reverts to its standby power mode. See Figure 9 for the address, acknowledge and data transfer sequence. SDA Bus Activity 1010 AAAR 10 9 8 W A C K Word Address A C K AAAR 10 9 8 W A C K Data Byte 0 AAA A AA AA 765 4 32 10 1010 1 D DD DD DD D 7 65 43 21 0 1 S T O P S T Device A10,A9,A8 Type A Address Read/Write R 0= Write T S T Device A10,A9,A8 Type A Address Read/Write R 1= Read T Slave Address Master sends Read request to Slave Master Writes Word Address to Slave Slave Address Master Requests Data from Slave Lack of ACK (low) from Master determines last data byte to be read Slave sends Data to Master Master Transmitter to Slave Receiver Shading Denotes 24163 SDA Output Active Master Transmitter to Slave Receiver Master Transmitter to Slave Receiver Slave Transmitter to Master Receiver Slave Transmitter to Master Receiver Slave Transmitter to Master Receiver Slave Transmitter to Master Receiver 2014 T fig09 2.0 FIGURE 9. RANDOM ADDRESS BYTE READ MODE 2014 2.1 8/2/00 7 S24163 Sequential READ Sequential READs can be initiated as either a current address READ or random access READ. The first word is transmitted as with the other byte read modes (current address byte READ or random address byte READ); however, the master now responds with an ACKnowledge, indicating that it requires additional data from the S24163. The S24163 continues to output data for each ACKnowledge received. The master terminates the sequential READ operation by not responding with an ACKnowledge, and issues a STOP conditions. During a sequential read operation, the internal address counter is automatically incremented with each acknowledge signal. For read operations, all address bits are incremented, allowing the entire array to be read using a single read command. After a count of the last memory address, the address counter will ‘roll-over’ and the memory will continue to output data. See Figure 10 for the address, acknowledge and data transfer sequence. Acknowledges from 24163 Acknowledge from Master Receiver Lack of Acknowledge from Master Receiver SDA Bus Activity 1010 S T Device A Type R Address T AAAR 10 9 8 W A C Word Address K AAAAAAAA 76543210 A C K AAAR 10 9 8 W A C K A First Data Byte C K DD DD DD DD 76 54 32 10 Last Data Byte 0 1010 1 DD DD DD DD 76 54 32 10 1 S T O P A10,A9,A8 Read/Write 0= Write S T Device A Type A10,A9,A80 R Address Read/Write T 1= Read Slave Address Master sends Read request to Slave Master Writes Word Address to Slave Slave Address Master Requests Data from Slave Slave sends Data to Master Lack of ACK (low) determines last data byte to be read Slave sends Data to Master Master Transmitter to Slave Receiver Master Transmitter to Slave Receiver Master Transmitter to Slave Receiver Slave Transmitter to Master Receiver Slave Transmitter to Master Receiver Slave Transmitter to Master Receiver Slave Transmitter to Master Receiver Slave Transmitter to Master Receiver Master Transmitter to Slave Receiver 2014 T fig10 2.0 Shading Denotes 24163 SDA Output Active FIGURE 10. SEQUENTIAL READ OPERATION (starting with a Random Address READ) 2014 2.1 8/2/00 8 S24163 ABSOLUTE MAXIMUM RATINGS Temperature Under Bias ............................................................................................................... -40°C to +85°C Storage Temperature ..................................................................................................................... -65°C to +125°C Soldering Temperature (less than 10 seconds) .............................................................................................. 300°C Supply Voltage ........................................................................................................................................... 0 to 6.5V Voltage on Any Pin ...................................................................................................................... -0.3V to VCC+0.3V ESD Voltage (JEDEC method) ...................................................................................................................... 2,000V NOTE: These are STRESS ratings only. Appropriate conditions for operating these devices are given elsewhere in this specification. Stresses beyond those listed here may permanently damage the part. Prolonged exposure to maximum ratings may affect device reliability. DC ELECTRICAL CHARACTERISTICS S24163, TA = -40°C to +85°C, VCC = 5V + 10% S24163-3, TA = -40°C to +85°C, VCC = 2.7V to 5.5V Symbol ICC ISB ILI ILO VIL VIH VOL Parameter Supply Current (CMOS) Standby Current (CMOS) Input Leakage Output Leakage Input Low Voltage Input High Voltage Output Low Voltage Conditions SCL = CMOS Levels @ 100KHz SDA = Open All other inputs = GND or VCC SCL = SDA = VCC All other inputs = GND VIN = 0 To VCC VOUT = 0 To VCC S0, S1, S2, SCL, SDA, RESET S0, S1, S2, SCL, SDA IOL = 3mA 0.7xVCC 0.4 VCC =5.5V VCC =3.3V VCC =5.5V VCC =3.3V Min Max 3 2 50 25 10 10 0.3xVCC Units mA mA µA µA µA µA V V V 2014 PGM T1 1.0 AC ELECTRICAL CHARACTERISTICS S24163, TA = -40°C to +85°C, VCC = 5V + 10% S24163-3, TA = -40°C to +85°C, VCC = 2.7V to 5.5V Symbol Parameter SCL Clock Frequency Clock Low Period Clock High Period Bus Free Time Start Condition Setup Time Start Condition Hold Time Stop Condition Setup Time Clock to Output Data Out Hold Time SCL and SDA Rise Time SCL and SDA Fall Time Data In Setup Time Data In Hold Time Noise Spike Width @ SCL, SDA Inputs Write Cycle Time Noise Suppression Time Constant SCL Low to SDA Data Out Valid SCL Low to SDA Data Out Change Before New Transmission Conditions 2.7V to 4.5V Min 0 4.7 4.0 4.7 4.7 4.0 4.7 0.3 0.3 1000 300 250 0 100 10 3.5 Max 100 4.5V to 5.5V Min Max 400 1.3 0.6 1.3 0.6 0.6 0.6 0.2 0.2 300 300 100 0 100 10 0.9 Units KHz µs µs µs µs µs µs µs µs ns ns ns ns ns ms fSCL tLOW tHIGH tBUF tSU:STA tHD:STA tSU:STO tAA tDH tR tF tSU:DAT tHD:DAT TI tWR 2014 PGM T2 1.0 2014 2.1 8/2/00 9 S24163 CAPACITANCE TA = 25°C, f = 100KHz Symbol CIN COUT Parameter Input Capacitance Output Capacitance Max 5 8 Units pF pF 2014 PGM T3 1.0 tR tF tH IGH tLOW tSU:STO SCL tSU:SDA tHD:SDA tHD:DAT tSU:DAT tBUF SDA In tDH tAA SDA Out 2014 ILL 13 1.0 FIGURE 11. BUS TIMING RESET CIRCUIT AC and DC ELECTRICAL CHARACTERISTICS TA = -40°C to +85°C Symbol VTRIP tPURST tRPD VRVALID tGLITCH VOLRS Reset Trip Point Power-Up Reset Timeout VTRIP to RESET Output Delay RESET Output Valid Glitch Reject Pulse Width RESET Output Low Voltage IOL – 1mA 1 Parameter Min 2.55 130 S24163-2.7 Max 2.7 270 5 1 30 0.4 Min 4.25 S24163–A Max 4.5 270 5 S24163–B Min 4.5 130 Max 4.75 270 5 1 Unit V ms µs V 30 0.4 ns V 130 30 0.4 2014 PGM T4 1.1 2014 2.1 8/2/00 10 S24163 tGLITCH VTRIP VRVALID tRPD tPURST tPURST VCC RESET tRPD RESET (S24162) 2014 ILL 14 1.0 FIGURE 12. RESET OUTPUT TIMING 8 Pin SOIC (Type S) Package JEDEC (150 mil body width) .050 (1.27) TYP. .050 (1.270) TYP. 8 Places .157 (4.00) .150 (3.80) .275 (6.99) TYP. 1 .196 (5.00) .189 (4.80) .030 (.762) TYP. 8 Places FOOTPRINT .061 (1.75) .053 (1.35) .020 (.50) x45° .010 (.25) .0192 (.49) .0138 (.35) .0098 (.25) .004 (.127) .05 (1.27) TYP. .035 (.90) .016 (.40) .244 (6.20) .228 (5.80) 8pn JEDEC SOIC ILL.2 2014 2.1 8/2/00 11 S24163 ORDERING INFORMATION S24163 Base Part Number Package S = 8 Lead 150mil SOIC S A T Tape & Reel Option Blank = Tube T = Tape & Reel Operating Voltage Range A = 4.5V to 5.5V VTRIP min. @ 4.25V B = 4.5V to 5.5V VTRIP min. @ 4.50V 2.7 = 2.7V to 5.5V VTRIP min. @ 2.55V 2014 Tree 2.0 NOTICE SUMMIT Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained herein reflect representative operating parameters, and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked, SUMMIT Microelectronics, Inc. shall not be liable for any damages arising as a result of any error or omission. SUMMIT Microelectronics, Inc. does not recommend the use of any of its products in life support or aviation applications where the failure or malfunction of the product can reasonably be expected to cause any failure of either system or to significantly affect their safety or effectiveness. Products are not authorized for use in such applications unless SUMMIT Microelectronics, Inc. receives written assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of SUMMIT Microelectronics, Inc. is adequately protected under the circumstances. © Copyright 2000 SUMMIT Microelectronics, Inc. I2C is a trademark of Philips Corporation. 2014 2.1 8/2/00 12