S42WD42SAP

S4242/S42WD42/S4261/S42WD61 Dual Voltage Supervisory Circuit With Watchdog Timer(S42WD61) (S42WD42) FEATURES • Precision Dual Voltage Monitor – VCC Supply Monitor - Dual reset outputs for complex microcontroller systems - Integrated memory write lockout function - No external components required • Second Voltage Monitor Output – Separate VLOW output – Generates interrupt to MCU – Generates RESET for dual supply systems - Guaranteed output assertion to VCC - 1V • Watchdog Timer (S42WD42, S42WD61) – 1.6s • Memory Internally Organized 2 x8 • Extended Programmable Functions Available on SMS24 • High Reliability – Endurance: 100,000 erase/write cycles – Data retention: 100 years OVERVIEW The S42xxx are a precision power supervisory circuit. It automatically monitors the device’s VCC level and will generate a reset output on two complementary open drain outputs. In addition to the VCC monitoring, the S42xxx also provides a second voltage comparator input. This input has an independent open drain output that can be wireOR’ed with the RESET I/O or it can be used as a system interrupt. The S42xxx also has an integrated 4k/16k-bit nonvolatile memory. The memory conforms to the industry standard two-wire serial interface. In addition to the reset circuitry, the S42WD42/S42WD61 also has a watchdog timer. BLOCK DIAGRAM VCC 8 SCL SDA 6 5 NONVOLATILE MEMORY ARRAY WRITE CONTROL PROGRAMMABLE RESET PULSE GENERATOR 2 RESET# + – VTRIP RESET CONTROL 7 PROGRAMMABLE WATCHDOG TIMER (S42WD42, S42WD61) 1 UV VSENSE 3 + – OV 1.26V 4 GND 2025 T BD 2.0 RESET VLOW# SUMMIT MICROELECTRONICS, Inc. • 300 Orchard City Drive, Suite 131 • Campbell, CA 95008 • Telephone 408-378-6461 • Fax 408-378-6586 • www.summitmicro.com © SUMMIT MICROELECTRONICS, Inc. 2000 2025 6.0 4/17/00 Characteristics subject to change without notice 1 S4242/S42WD42/S4261/S42WD61 ABSOLUTE MAXIMUM RATINGS Temperature Under Bias ............................................................................................................................... -40°C to +85°C Storage Temperature ..................................................................................................................................... -65°C to +125°C Soldering Temperature (less than 10 seconds) ................................................................................................................... 300°C Supply Voltage ............................................................................................................................................................. 0 to 6.5V Voltage on Any Pin ....................................................................................................................................... -0.3V to VCC+0.3V ESD Voltage (JEDEC method) .......................................................................................................................................... 2,000V NOTE: These are STRESS ratings only. Appropriate conditions for operating these devices are given elsewhere in this specification. Stresses beyond those listed here may permanently damage the part. Prolonged exposure to maximum ratings may affect device reliability. RECOMMENDED OPERATING CONDITIONS Temperature Commercial Industrial Min 0°C -40°C Max +70°C +85°C 2025 PGM T1.0 DC ELECTRICAL CHARACTERISTICS (over recommended operating conditions unless otherwise specified) Symbol ICC ISB ILI ILO VIL VIH VOL Parameter Supply Current (CMOS) Standby Current (CMOS) Input Leakage Output Leakage Input Low Voltage Input High Voltage Output Low Voltage Conditions SCL = CMOS Levels @ 100KHz SDA = Open All other inputs = GND or VCC SCL = SDA = VCC All other inputs = GND VIN = 0 To VCC VOUT = 0 To VCC SCL, SDA, RESET# (pin 2) SCL, SDA, RESET (pin7) IOL = 3mA SDA VCC =5.5V VCC =3.3V VCC =5.5V VCC =3.3V Min Max 3 2 50 25 10 10 0.3xVCC 0.7xVCC 0.4 Units mA mA µA µA µA µA V V V 2025 PGM T2.0 AC ELECTRICAL CHARACTERISTICS (over recommended operating conditions unless otherwise specified) Symbol Parameter SCL Clock Frequency Clock Low Period Clock High Period Bus Free Time Start Condition Setup Time Start Condition Hold Time Stop Condition Setup Time Clock to Output Data Out Hold Time SCL and SDA Rise Time SCL and SDA Fall Time Data In Setup Time Data In Hold Time Noise Spike Width @ SCL, SDA Inputs Write Cycle Time Noise Suppression Time Constant SCL Low to SDA Data Out Valid SCL Low to SDA Data Out Change Before New Transmission Conditions 2.7V to 4.5V Min 0 4.7 4.0 4.7 4.7 4.0 4.7 0.3 0.3 1000 300 250 0 100 10 3.5 Max 100 4.5V to 5.5V Min Max 400 1.3 0.6 1.3 0.6 0.6 0.6 0.2 0.2 300 300 100 0 100 10 0.9 Units KHz µs µs µs µs µs µs µs µs ns ns ns ns ns ms 2025 PGM T3.0 fSCL tLOW tHIGH tBUF tSU:STA tHD:STA tSU:STO tAA tDH tR tF tSU:DAT tHD:DAT TI tWR 2025 6.0 4/17/00 2 S4242/S42WD42/S4261/S42WD61 CAPACITANCE TA = 25°C, f = 100KHz Symbol CIN COUT Parameter Input Capacitance Output Capacitance Max 5 8 Units pF pF 2025 PGM T4.0 tR tF tHIGH tLOW SCL tSU:SDA tHD:DAT tSU:DAT tSU:STO tHD:SDA tBUF SDA In tAA tDH SDA Out 2025 Fig01 1.0 FIGURE 1. BUS TIMING START Condition SCL STOP Condition SDA In 2025 Fig02 1.0 FIGURE 2. START AND STOP CONDITIONS 2025 6.0 4/17/00 3 S4242/S42WD42/S4261/S42WD61 tGLITCH VCC VTRIP VRVALID tPURST tRPD tPURST RESET# tRPD RESET FIGURE 3. RESET OUTPUT TIMING 2025 T fig03 2.0 RESET CIRCUIT AC and DC ELECTRICAL CHARACTERISTICS TA=-40°C to +85°C Symbol VTRIP Parameter Reset Trip Point Part no. Suffix A (or) Blank B 2.7 Min. 4.250 4.50 2.7 Typ. 4.375 4.625 2.9 200 Max. 4.5 4.75 3.10 5 1 30 0.4 VCC-.75 1.20 1.20 1.20 1.20 1.25 1.25 1.25 1.25 1.30 1.30 1.30 1.30 5 5 1600 Unit V V V ms µs V ns V V V V V V µs µs ms 2025 PGM T5.2 tPURST tRPD VRVALID tGLITCH VOLRS VOHRS VULH VUHL VOLH VOHL tVD1 tVD2 tWDTO Reset Timeout VTRIP to RESET Output Delay RESET Output Valid to VCC min. Guarantee Glitch Reject Pulse Width note 1 RESET Output Low Voltage IOL = 1mA RESET High Voltage Output IOH = 800µA VSENSE Under-voltage threshold low to high VSENSE Under-voltage threshold high to low VSENSE Over-voltage threshold low to high VSENSE Over-voltage threshold high to low Delay to VLOW Active Delay to VLOW Released Watchdog timeout Period (S42WD61) (S42WD42) 2025 6.0 4/17/00 4 S4242/S42WD42/S4261/S42WD61 VULH VSENSE (Under-voltage detect) VUHL tVD1 tVD2 VLOW# 2025 T fig04 2.0 FIGURE 4. VSENSE UNDER-VOLTAGE FUNCTION RESET# (in) RESET# (out) tPURST tPURST RESET (out) 2025 T fig05 2.0 FIGURE 5. RESET AS AN INPUT 2025 6.0 4/17/00 5 S4242/S42WD42/S4261/S42WD61 PIN CONFIGURATIONS 8-Pin PDIP or 8-Pin SOIC PIN NAMES Symbol VLOW# Pin 1 2 3 4 5 6 7 8 Description Open drain output, active when VSENSE < 1.24V Active low I/O 2nd monitor voltage input.VLOW# output when < 1.24V Analog & digital ground Serial memory I/O data line Serial memory clock Active high I/O Supply voltage VLOW# RESET# VSENSE GND 1 2 3 4 8 7 6 5 VCC RESET SCL SDA RESET# VSENSE GND SDA SCL RESET VCC 2025 T PCon 2.0 PB_RST# VCC = 3.0V or 5.0V VBAT TO REGULATOR INTO (P1.5) S42xxx VBAT TRIP VLOW# RESET# VSENSE GND VCC RESET SCL SDA 8051 Type MCU RST SCL (P0.0) SDA (P0.1) I2C Peripheral RESET# SCL SDA 2025 T fig06 2.0 FIGURE 6. TYPICAL SYSTEM CONFIGURATION USING A PUSH BUTTON RESET AND BATTERY MONITOR CIRCUIT VCC = 5.0V ±10% SECOND CARD VOLTAGE 3.0V ±5% S42xxx VLOW# RESET# VSENSE GND VCC RESET SCL SDA General Purpose MCU SCL SDA RESET# I2C Peripheral RESET# SCL SDA 2025 T fig07 2.0 FIGURE 7. TYPICAL SYSTEM CONFIGURATION FOR DUAL RESET WITH VCC MONITOR AND 3.3VOLT MONITOR 2025 6.0 4/17/00 6 S4242/S42WD42/S4261/S42WD61 PIN DESCRIPTIONS Serial Clock (SCL) - The SCL input is used to clock data into and out of the device. In the WRITE mode, data must remain stable while SCL is HIGH. In the READ mode, data is clocked out on the falling edge of SCL. Serial Data (SDA) - The SDA pin is a bidirectional pin used to transfer data into and out of the device. Data may change only when SCL is LOW, except START and STOP conditions. It is an open-drain output and may be wireORed with any number of open-drain or open-collector outputs. RESET# - RESET# is an active low open-drain output. It should be tied high through a pull-up resistor connected to VCC. RESET# is an I/O, therefore it may also be used to condition a RESET# signal generated by another device; it can also be used to debounce a pushbutton input. RESET - RESET is an active high open drain (PFET) output. It should be tied low through a pull-down resistor connected to ground. RESET is an I/O, therefore it may also be used to condition a RESET signal generated by another device. VSENSE - The VSENSE input is used as a second voltage sensing input. The pin is tied to a comparator that uses the precision internal 1.25V reference. VLOW# - VLOW# is an active low open drain output driven low whenever VSENSE is below 1.25V. It is not a timed output and only responds to the state of VSENSE. ENDURANCE AND DATA RETENTION The S42xxx is designed for applications requiring 100,000 erase/write cycles and unlimited read cycles. It provides 100 years of secure data retention, with or without power applied, after the execution of 100,000 erase/write cycles. Reset Controller Description The S42xxx provides a precision RESET controller that ensures correct system operation during brown-out and power-up/-down conditions. It is configured with two open drain RESET outputs; pin 7 is an active high output and pin 2 is an active low output. For proper operation pin 7 should be tied low through a pull-down resistor while pin 2 should be tied high through a resistor connected to VCC. During power-up, the RESET outputs remain active until VCC reaches the VTRIP threshold and will continue driving the outputs for tPURST (200 msec)after reaching VTRIP. The RESET outputs will be valid so long as VCC is > 1.0V. During power-down, the RESET outputs will begin driving active when VCC falls below VTRIP. The RESET pins are I/Os; therefore, the S42xxx can act as a signal conditioning circuit for an externally applied reset. The inputs are edge triggered; that is, the RESET input will initiate a reset timeout after detecting a low to high transition and the RESET# input will initiate a reset timeout after detecting a high to low transition. Refer to the applications information section for more details on device operation as a reset conditioning circuit. Voltage Sensor Description VSENSE is an auxiliary voltage detection circuit. Its threshold is set at 1.25V and it generates a VLOW# output for an under-voltage condition. Because the VLOW# output is open-drain, it can be wire-ORed with the RESET# output or tied directly to an IRQ input on a microcontroller. 2025 6.0 4/17/00 7 S4242/S42WD42/S4261/S42WD61 SCL from Master Data Output from Transmitter Data Output from Receiver Start Condition 1 8 9 tAA tAA FIGURE 8. ACKNOWLEDGE RESPONSE FROM RECEIVER ACKnowledge 2025 ILL8.0 CHARACTERISTICS OF THE I2C BUS General Description The I2C bus was designed for two-way, two-line serial communication between different integrated circuits. The two lines are: a serial data line (SDA), and a serial clock line (SCL). The SDA line must be connected to a positive supply by a pull-up resistor, located somewhere on the bus (See Figure 6). Data transfer between devices may be initiated with a START condition only when SCL and SDA are HIGH (bus is not busy). Input Data Protocol One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during clock HIGH time, because changes on the data line while SCL is HIGH will be interpreted as start or stop condition, refer to Figure 2. START and STOP Conditions When both the data and clock lines are HIGH, the bus is said to be not busy. A HIGH-to-LOW transition on the data line, while the clock is HIGH, is defined as the “START” condition. A LOW-to-HIGH transition on the data line, while the clock is HIGH, is defined as the “STOP” condition (See Figure 2). DEVICE OPERATION The S42xxx is a 16K-bit serial E2PROM. The device supports the I2C bidirectional data transmission protocol. The protocol defines any device that sends data onto the bus as a “transmitter” and any device which receives data as a “receiver.” The device controlling data transmission is called the “master” and the controlled device is called the “slave.” In all cases, the S42xxx will be a “slave” device, since it never initiates any data transfers. Acknowledge (ACK) Acknowledge is a software convention used to indicate successful data transfers. The transmitting device, either the master or the slave, will release the bus after transmitting eight bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to ACKnowledge that it received the eight bits of data (See Figure 8). The S42xxx will respond with an ACKnowledge after recognition of a START condition and its slave address byte. If both the device and a write operation are selected, the S42xxx will respond with an ACKnowledge after the receipt of each subsequent 8-bit word. In the READ mode, the S42xxx transmits eight bits of data, then releases the SDA line, and monitors the line for an ACKnowledge signal. If an ACKnowledge is detected, and no STOP condition is generated by the master, the S42xxx will continue to transmit data. If an ACKnowledge is not detected, the S42xxx will terminate further data transmissions and awaits a STOP condition before returning to the standby power mode. Device Addressing Following a start condition the master must output the address of the slave it is accessing. The most significant four bits of the slave address are the device type identifier (see figure 7). For the S42xxx this is fixed as 1010[B]. Word Address The next three bits of the slave address are an extension of the array’s address and are concatenated with the eight bits of address in the word address field, providing direct access to the 2,048 x8 array of the S4261 and S42WD61. A10 and A9 are “Don’t Care” on S4242 and S42WD42. Read/Write Bit The last bit of the data stream defines the operation to be performed. When set to “1,” a read operation is selected; when set to “0,” a write operation is selected. DEVICE IDENTIFIER HIGH ORDER WORD ADDRESS 1 0 1 0 * A10 * A9 A8 R/W *S4261/S42WD61 only 2025 ILL9.1 FIGURE 9. SLAVE ADDRESS BYTE 8 2025 6.0 4/17/00 S4242/S42WD42/S4261/S42WD61 WRITE OPERATIONS The S42xxx allows two types of write operations: byte write and page write. The byte write operation writes a single byte during the nonvolatile write period (tWR). The page write operation allows up to 16 bytes in the same page to be written during tWR. Byte WRITE After the slave address is sent (to identify the slave device, specify high order word address and a read or write operation), a second byte is transmitted which contains the low 8 bit addresses of any one of the 2,048 words in the array. Upon receipt of the word address, the S42xxx responds with an ACKnowledge. After receiving the next byte of data, it again responds with an ACKnowledge. The master then terminates the transfer by generating a STOP condition, at which time the S42xxx begins the internal write cycle. While the internal write cycle is in progress, the S42xxx inputs are disabled, and the device will not respond to any requests from the master. Refer to Figure 10 for the address, ACKnowledge and data transfer sequence. Page WRITE The S42xxx is capable of a 16-byte page write operation. It is initiated in the same manner as the byte-write operation, but instead of terminating the write cycle after the first data word, the master can transmit up to 15 more words of data. After the receipt of each word, the S42xxx will respond with an ACKnowledge. The S42xxx automatically increments the address for subsequent data words. After the receipt of each word, the four low order address bits are internally incremented by one. The high order five bits of the address byte remain constant. Should the master transmit more than sixteen words, prior to generating the STOP condition, the address counter will “roll over,” and the previously written data will be overwritten. As with the byte-write operation, all inputs are disabled during the internal write cycle. Refer to Figure 10 for the address, ACKnowledge and data transfer sequence. Acknowledges Transmitted from 42xxx to Master Receiver If single byte-write only, Stop bit issued here. Acknowledges Transmitted from 42xxx to Master Receiver SDA Bus Activity 1010 A AAR 10 9 8 W A C Word Address K AAAAAAAA 76543210 A C K Data Byte n A C K A Data Byte n+1 C K DDDDDDDD 76543210 Data Byte n+15 C K DDDDDDDD 76543210 A 0 DDDDDDDD 76543210 S T Device A10,A9,A8 Type A R Address Read/Write T 0= Write S T O P Slave Address Master Sends Read Request to Slave Master Writes Word Address to Slave Master Writes Data to Slave Master Writes Data to Slave Master Writes Data to Slave Master Transmitter to Slave Receiver Master Transmitter to Slave Receiver Master Transmitter to Slave Receiver Master Transmitter to Slave Receiver Master Transmitter to Slave Receiver Slave Transmitter to Master Receiver 2025 ILL10.1 Slave Transmitter to Master Receiver Slave Transmitter to Master Receiver Slave Transmitter to Master Receiver Slave Transmitter to Master Receiver Shading Denotes 42xxx SDA Output Active FIGURE 10. PAGE/BYTE WRITE MODE 2025 6.0 4/17/00 9 S4242/S42WD42/S4261/S42WD61 Acknowledge Polling When the S42xxx is performing an internal WRITE operation, it will ignore any new START conditions. Since the device will only return an acknowledge after it accepts the START, the part can be continuously queried until an acknowledge is issued, indicating that the internal WRITE cycle is complete. To poll the device, give it a START condition, followed by a slave address for a WRITE operation (See Figure 9). Internal WRITE Cycle In Progress; Begin ACK Polling READ OPERATIONS Read operations are initiated with the R/W bit of the identification field set to “1.” There are four different read options: 1. 2. 3. 4. Current Address Byte Read Random Address Byte Read Current Address Sequential Read Random Address Sequential Read Issue Start Issue Slave Address and R/W = 0 Issue Stop Current Address Byte Read The S42xxx contains an internal address counter which maintains the address of the last word accessed, incremented by one. If the last address accessed (either a read or write) was to address location n, the next read operation would access data from address location n+1 and increment the current address pointer. When the S42xxx receives the slave address field with the R/W bit set to “1,” it issues an acknowledge and transmits the 8bit word stored at address location n+1. The current address byte read operation only accesses a single byte of data. The master does not acknowledge the transfer, but does generate a stop condition. At this point, the S42xxx discontinues data transmission. See Figure 12 for the address acknowledge and data transfer sequence. ACK Returned? No Yes (Internal WRITE Cycle is completed) Next operation a WRITE? Yes Issue Byte Address Issue Stop No Proceed with WRITE Await Next Command 2025 ILL11.0 FIGURE 11. ACKNOWLEDGE POLLING SDA Bus Activity 1 A AAR 10 9 8 W A C K Data Byte 1010 1 DDDDDDDD 76543210 1 S T O P S T Device Type A10,A9,A8 A Address Read/Write R 1= Read T Slave Address Master sends Read request to Slave Lack of ACK (low) from Master determines last data byte to be read Slave sends Data to Master Slave Transmitter to Master Receiver Master Transmitter to Slave Receiver Shading Denotes 42xxx SDA Output Active 2025 ILL12.1 FIGURE 12. CURRENT ADDRESS BYTE READ MODE 2025 6.0 4/17/00 10 S4242/S42WD42/S4261/S42WD61 Random Address Byte Read Random address read operations allow the master to access any memory location in a random fashion. This operation involves a two-step process. First, the master issues a write command which includes the start condition and the slave address field (with the R/W bit set to WRITE) followed by the address of the word it is to read. This procedure sets the internal address counter of the S42xxx to the desired address. After the word address acknowledge is received by the master, the master immediately reissues a start condition followed by another slave address field with the R/W bit set to READ. The S42xxx will respond with an acknowledge and then transmit the 8-data bits stored at the addressed location. At this point, the master does not acknowledge the transmission but does generate the stop condition. The S42xxx discontinues data transmission and reverts to its standby power mode. See Figure 13 for the address, acknowledge and data transfer sequence. SDA Bus Activity 1010 ** AAAR 10 9 8 W A C K Word Address A C K AAAR 10 9 8 W A C K Data Byte 0 AAA A AA AA 765 4 32 10 1010 1 D DD DD DD D 7 65 43 21 0 1 S T O P S T Device A10,A9,A8 Type A Address Read/Write R 0= Write T S T Device A10,A9,A8 Type A Address Read/Write R 1= Read T Slave Address Master sends Read request to Slave Master Writes Word Address to Slave Slave Address Master Requests Data from Slave Lack of ACK (low) from Master determines last data byte to be read Slave sends Data to Master Master Transmitter to Slave Receiver Shading Denotes 42xxx SDA Output Active Master Transmitter to Slave Receiver Master Transmitter to Slave Receiver Slave Transmitter to Master Receiver Slave Transmitter to Master Receiver Slave Transmitter to Master Receiver Slave Transmitter to Master Receiver 2025 ILL13.1 * S4261/S42WD61 only FIGURE 13. RANDOM ADDRESS BYTE READ MODE 2025 6.0 4/17/00 11 S4242/S42WD42/S4261/S42WD61 Sequential READ Sequential READs can be initiated as either a current address READ or random access READ. The first word is transmitted as with the other byte read modes (current address byte READ or random address byte READ); however, the master now responds with an ACKnowledge, indicating that it requires additional data from the S42xxx. The S42xxx continues to output data for each ACKnowledge received. The master terminates the sequential READ operation by not responding with an ACKnowledge, and issues a STOP conditions. During a sequential read operation, the internal address counter is automatically incremented with each acknowledge signal. For read operations, all address bits are incremented, allowing the entire array to be read using a single read command. After a count of the last memory address, the address counter will ‘roll-over’ and the memory will continue to output data. See Figure 14 for the address, acknowledge and data transfer sequence. Acknowledges from 42xxx Acknowledge from Master Receiver Lack of Acknowledge from Master Receiver SDA Bus Activity 1010 S T Device A Type R Address T *** AAAR 10 9 8 W A C Word Address K AAAAAAAA 76543210 A C K AAAR 10 9 8 W A C K A First Data Byte C K DD DD DD DD 76 54 32 10 Last Data Byte 0 1010 1 DD DD DD DD 76 54 32 10 1 S T O P A10,A9,A8 Read/Write 0= Write S T Device A Type A10,A9,A80 R Address Read/Write T 1= Read Slave Address Master sends Read request to Slave Master Writes Word Address to Slave Slave Address Master Requests Data from Slave Slave sends Data to Master Lack of ACK (low) determines last data byte to be read Slave sends Data to Master Master Transmitter to Slave Receiver Master Transmitter to Slave Receiver Master Transmitter to Slave Receiver Slave Transmitter to Master Receiver Slave Transmitter to Master Receiver Slave Transmitter to Master Receiver Slave Transmitter to Master Receiver Slave Transmitter to Master Receiver Master Transmitter to Slave Receiver 2025 ILL14.1 Shading Denotes 42xxx SDA Output Active * S4261/S42WD61 only FIGURE 14. SEQUENTIAL READ OPERATION (starting with a Random Address READ) 2025 6.0 4/17/00 12 S4242/S42WD42/S4261/S42WD61 Watchdog Timer Operation The S42WD42/S42WD61 has a watchdog timer with a nominal timeout period of 1.6 seconds. Whenever the watchdog times out it will generate a reset output on both RESET# and RESET. The watchdog timer will reset to t0 whenever the S42WD42/S42WD61 issues an ACKnowledge. Therefore, the host system will need to issue a start condition, followed by a valid address and command. It can be a normal command as in the sequence of reading or writing to the memory, or it can be a dummy command issued solely for the purpose of resetting the watchdog timer. Refer to Figure 17 for detailed sequence of operations. The watchdog timer will be held in the reset state during power-on while VCC is less than VTRIP. Once VCC exceeds VTRIP, the watchdog will continue to be held in a reset state for the duration of tPURST. After tPURST, the timer will be released and begin counting. If either reset input is asserted the watchdog timer will be reset and remain in the reset condition until either tPURST has expired or the reset input is released, whichever is longer. If the watchdog times out and no action is taken by the host, the S42xxx will drive the reset outputs active for the duration of tPURST at which point it will release the outputs and begin the watchdog timer again. Refer to Figure 18 for detailed sequence of operations. S T A R T1010x x x R W S T O P SCL and SDA Idle A C K ACK response from S42xxx Resets The Watchdog Timer S T A R T1010x x x R W S T O P SCL and SDA Idle A C K S T A R T1010x x x R W S T O P tPURST A C K RESET# t < 1.6sec t0 t0 t > 1.6sec t0 2025 T fig17 2.0 FIGURE 17. SEQUENCE ONE S T A R T1010x x x SCL and SDA Idle A C K Watchdog Timer t0 tPURST RESET# t > 1.6sec t0 t > 1.6sec t0 2025 T fig18 2.0 S T A R T1010x x x R W S T O P SCL and SDA Idle R W S T O P A C K No Affect On tPURST FIGURE 18. SEQUENCE TWO 2025 6.0 4/17/00 13 S4242/S42WD42/S4261/S42WD61 8 Pin PDIP (Type P) Package .375 (9.525) PIN 1 INDICATOR .250 (6.350) .300 (7.620) .070 (1.778) .0375 (0.952) .015 (.381) Min. SEATING PLANE .130 (3.302) .060 ± .005 (1.524) ± .127 TYP. .100 (2.54) TYP. .130 (3.302) .018 (.457) TYP. 5°-7°TYP. (4 PLCS) 0°-15° .350 (8.89) .009 ± .002 (.229 ± .051) 8pn PDIP/P ILL.3 8 Pin SOIC (Type S) Package JEDEC (150 mil body width) .050 (1.27) TYP. .050 (1.270) TYP. 8 Places .157 (4.00) .150 (3.80) .275 (6.99) TYP. 1 .196 (5.00) .189 (4.80) .030 (.762) TYP. 8 Places FOOTPRINT .061 (1.75) .053 (1.35) .020 (.50) x45° .010 (.25) .0192 (.49) .0138 (.35) .0098 (.25) .004 (.127) .05 (1.27) TYP. .035 (.90) .016 (.40) .244 (6.20) .228 (5.80) 8pn JEDEC SOIC ILL.2 2025 6.0 4/17/00 14 S4242/S42WD42/S4261/S42WD61 ORDERING INFORMATION S42 xxx Base Part Number Prefix Suffix 42 = 4k Bits 61 = 16k Bits WD42 = 4k, Watchdog timer WD61 = 16k, Watchdog timer P A VTRIP A = 4.5V B = 4.75V 2.7 = 2.7V Blank = 4.5V Package P = PDIP S = SOIC 2025 6.0 4/17/00 15 S4242/S42WD42/S4261/S42WD61 NOTICE SUMMIT Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained herein reflect representative operating parameters, and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked, SUMMIT Microelectronics, Inc. shall not be liable for any damages arising as a result of any error or omission. SUMMIT Microelectronics, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless SUMMIT Microelectronics, Inc. receives written assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of SUMMIT Microelectronics, Inc. is adequately protected under the circumstances. I2C is a trademark of Philips Corporation. © Copyright 2000 SUMMIT Microelectronics, Inc. 2025 6.0 4/17/00 16