SMH4802

SUMMIT MICROELECTRONICS, Inc. SMH4802 Preliminary Information See Last Page Programmable -48V Hot-Swap Controller with Forced Shut Down FEATURES & APPLICATIONS l Soft Start Power Supply l Live Insertion into a -48V backplane l Programmable Control of a DC/DC Converter w I2C Power On/Off Control l Highly Programmable Circuit Breaker w Active In-rush Current Limiting w Over-current Filter Circuit Breaker Immunity to Voltage Steps and Current Spikes l Programmable Forced Shutdown Timer l Internal Shunt Regulator Allows a Wide Supply Range l 14-pin SOIC and 16-pin SSOP packages APPLICATIONS l -48V Power Distribution w w w w Telecom Line Cards Central Office Switching High Availability Servers Hot Board Insertion INTRODUCTION The SMH4802 is designed to control in-rush current during hot swapping of plug-in cards operating in a distributed power environment. The device drives an external power MOSFET switch that connects the supply to the load and protects against over-current conditions that might disrupt the host supply. It also provides undervoltage and over-voltage monitoring of the host power supply. When the source and drain voltages of the external MOSFETs are within specification it will provide a Power Good logic output that can be used to enable a DC/DC converter. Additional features of the device include: temperature sense or master enable input, a 5V reference output for expanding monitor functions, and duty-cycle or latched over-current protection modes. An internal Shunt regulator allows a wide supply range. The SMH4802 -48V Hot-Swap Controller also features a simple software I2C Power On/Off Interface for remote power control applications. Programming of configuration, control and calibration values by the user can be simplified with the SMX3200 interface adapter and a windows based GUI supplied by Summit. SIMPLIFIED APPLICATION DRAWING –48V Ret RD 4 5 14 SDA I2C Header SCL VDD 8 UV PG# 12 V+ Out+ On/ DC/DC Off V– Out– 9 OV SMH4802 FS# 10 3 EN/TS VSS 7 CBSENSE VGATE 6 2 DRAIN SENSE 5VREF 1 11 –48V A RS VSS 2062 SAD –48V B Figure 1. The drawing illustrates the SMH4802 in a typical line-card application. It should be noted this is just an example, and the specific component values are purposely not shown. Pin numbers reflect SOIC package. ©SUMMIT MICROELECTRONICS, Inc., 2003 • 1717 Fox Drive • San Jose, CA 95131 • Phone 408-436-9890 • FAX 408-436-9897 • www.summitmicro.com Characteristics subject to change without notice 2062 2.3 6/19/03 SMH4802 Preliminary Information GENERAL DESCRIPTION The SMH4802 is an integrated power controller for hot swappable add-in cards. The device operates from a wide supply range and generates the signals necessary to drive an isolated output DC/DC converter. As a typical add-in board is inserted into the powered backplane, physical connections must first be made with the chassis to discharge any electrostatic voltage potentials. The board then contacts the long pins on the backplane that provide power and ground. As soon as power is applied, the device starts up, but does not immediately apply power to the output load. Under-voltage and over-voltage circuits inside the controller verify the input voltage is within the user-specified range. Once these requirements are met, the hot-swap controller enables VGATE to turn on the external power MOSFET. The VGATE output is current limited to IVGATE, allowing the slew rate to be easily modified using external passive components. During the controlled turn-on period the VDS of the MOSFET is monitored by the DRAIN SENSE input. When DRAIN SENSE drops below 2.5V, and VGATE is greater than VDD – VGT, the PG# output can begin turning on the DC/DC converter. Steady state operation is maintained as long as all conditions are normal. Any of the following events may cause the device to disable the DC/DC controller by shutting down the power MOSFET: an under-voltage or over-voltage condition on the host power supply; an overcurrent event detected on the CBSENSE input; a failure of the power MOSFET sensed via the DRAIN SENSE pin; the master enable (EN/TS) falling below 2.5V; or the FS# input being driven low by events on the secondary side of the DC/DC controller. If one of these events occurs the SMH4802 can be configured so VGATE shuts off and either latches into an off state or recycles power after a cooling down period, tCYC. FUNCTIONAL BLOCK DIAGRAM VDD 14 12VREF PROGRAMMABLE SHUTDOWN TIMER + 10 FS# DRAIN 1 SENSE – 11 5.0VREF 200kΩ EN/TS 3 + Prog. Ref. – + – PROGRAMMABLE DELAY 12 PG# UV 8 OV 9 5V 12V 2.5V VSS 7 50kΩ 50kΩ SCL 5 SDA 4 I2C INTERFACE LOGIC PROGRAMMED DELAY 50mV + – DUTY CYCLE TIMER CBSENSE 6 PROGRAMMED Quick-Trip + – Figure 2. Functional Block diagram. Pin numbers reflect SOIC package. 2 2062 2.3 6/19/03 SUMMIT MICROELECTRONICS, Inc. + – OV/UV FILTER PROGRAMMABLE DELAY VGATE SENSE 2 VGATE 2062 BD SMH4802 Preliminary Information PIN CONFIGURATION 14-Pin SOIC DRAIN SENSE VGATE EN/TS SDA SCL CBSENSE VSS 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD nc PG# 5VREF FS# OV UV 2062 14 PCon 2062 16 PCon 16-Pin SSOP DRAIN SENSE VGATE EN/TS nc SDA SCL CBSENSE VSS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD nc PG# nc 5VREF FS# OV UV PIN DESCRIPTIONS Pin No. Type Pin Name DRAIN SENSE Pin Description The DRAIN SENSE input monitors the voltage at the drain of the MOSFET (the measure is with respect to VSS). An internal 10µA source pulls the DRAIN SENSE signal towards the 5VREF level. DRAIN SENSE must be held below 2.5V to enable the PG# output. The VGA E output is a high side drive output, nearly equal to VDD, used to turn T on an external power MOSFET This signal supplies a constant current output . (100µA typical) which allows easy adjustment of the MOSFET turn-on slew rate. The ENable/T mperature Sense input is the master enable input. VGA E will be e T disabled if EN/TS is less than 2.5V This pin has an internal 200kΩ pullup to 5V . . SDA is the bidirectional serial data pin. It is configured as an open drain output. There is an internal 50kΩ resistor connected to 5VREF . The SCL input is used to clock data into and out of the configuration registers. In the write mode data must remain stable on SDA while SCL is HIGH. In the read mode data is clocked out on the falling edge of SCL. There is an internal 50kΩ resistor connected to 5VREF . 1 I 2 O VGA E T 3 4 I I/O EN/TS SDA 5 I SCL 6 I The Circuit Breaker SENSE input is used to detect over-current conditions across an external, low value sense resistor (RS) tied in series with the power MOSFET . CBSENSE A voltage drop of greater than 50mV across the resistor for longer than tCBD will trip the circuit breaker. T disable CBSENSE connect the pin directly to VSS. A o programmable Quick-T ip sense point is also available. r VSS VSS is connected to the, negative side of the supply. All inputs and the 5VREF output are referenced to VSS. The UV pin is used as an under-voltage supply monitor, typically in conjunction with an external resistor ladder. VGA E will be disabled if UV is less than 2.5V T . A programmable internal hysteresis is available on the UV input, adjustable in increments of 62.5mV A filter delay is also available on the UV input. . 7 PWR 8 I UV Note: Pin numbers reflect the 14 Pin SOIC package. 2062 Pin Table A SUMMIT MICROELECTRONICS, Inc. 2062 2.3 6/19/03 3 SMH4802 Preliminary Information PIN DESCRIPTIONS (Continued) Pin No. 9 Type I Pin Name OV Pin Description The OV pin is used as an under-voltage supply monitor, typically in conjunction with an external resistor ladder. VGA E will be disabled if OV is greater than T 2.5V A filter delay is also available on the OV input. . The Forced Shutdown pin is an active low input that causes VGA E and the PG# T output to be shut down at any time after an internal hold-off timer has expired. The hold-off timer allows supervisory circuits on the secondary side (which are not powered up initially) to control shut down of the SMH4802 via an optoisolator. This input has no pullup resistor. This is a 5V output reference voltage that may be used to expand the logic input functions on the SMH4802. The reference output is with respect to VSS. PG# is an open-drain, active-low output with no internal pullup resistor. It can be used to switch a Ioad or enable a DC/DC converter. PG# is enabled after 3 events: VGA E reaches VDD - VGT , the Drain Sense voltage is less than 2.5V T , and the programmed delay time has expired. V ltage on this pin cannot exceed o 12V as referenced to VSS. No connection VDD is the positive supply connection. An internal shunt regulator connected between VDD and VSS develops approximately 12V that supplies the SMH4802. A resistor Must be placed in series with the VDD pin to limit the regulator current (RD in the application illustrations). 2062 Pin Table B 10 I FS# 11 O 5VREF 12 O PG# 13 nc nc 14 PWR VDD Note: Pin numbers reflect the 14 Pin SOIC package. 4 2062 2.3 6/19/03 SUMMIT MICROELECTRONICS, Inc. SMH4802 Preliminary Information ABSOLUTE MAXIMUM RATINGS* Temperature Under Bias ..................... –55°C to 125°C Storage Temperature .......................... –65°C to 150°C Lead Solder Temperature (10 secs) .................. 300°C Terminal Voltage with Respect to VSS: VDD ............................................. –0.5V to VDD OV, UV, DRAIN SENSE, SCL, SDA, FS#, CBSENSE ........................ –0.5V to VDD +0.5V EN/TS ....................................................... 10V PG# .................................. –0.5V to VDD +0.5V VGATE ........................................... VDD +0.5V RECOMMENDED OPERATING CONDITIONS Temperature Range ............ (Industrial) –40°C to 85°C .......................................... (Commercial) –5°C to 70°C TJ(Max) ................................................................ 150°C RΘJ-A ..................................... * Q 88°C/W; R 115°C/W RΘJ-C ....................................... * Q 37°C/W; R 40°C/W Note — The device is not guaranteed to function outside its operating rating. Stresses listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. * Q 14 pin SOIC; R 16 pin SSOP. DC OPERATING CHARACTERISTICS (Over Recommended Operating Conditions; Voltages are relative to VSS, except VGT) Symbol VDD 5VREF ILOAD5 IDD VUV VUVHYST VOV VOVHYST VGATE IGATE VSENSE ISENSE VCB Parameter Supply voltage 5V reference output 5V reference output current Power supply current Under-Voltage threshold Under-Voltage hysteresis Over-Voltage threshold Over-Voltage hysteresis VGATE output voltage VGATE current output DRAIN SENSE threshold DRAIN SENSE current output Circuit breaker threshold Programmable Quick Trip circuit breaker threshold Off VEN/TS VEN/TSHYST VOL IIL VGT EN/TS threshold EN/TS hysteresis Output low voltage PG# Input current EN/TS Gate threshold (VGT = VDD – VGATE) IDD = 3mA IDD = 3mA IOL = 3mA VIL = VSS 0.7 0 100 1.8 3.0 2.475 2.500 10 0.4 2.525 IDD = 3mA VSENSE = VSS IDD = 3mA 2.475 –9 40 100 2.500 –10 50 200 VQCB 100 60 2.525 –11 60 IDD = 3mA IDD = 3mA IDD = 3mA IDD = 3mA 2.475 Conditions IDD = 3mA IDD = 3mA IDD = 3mA Min. 11 4.75 –1 2 2.475 2.500 63 2.500 10 VDD 2.525 Typ. 12 5.00 Max. 13 5.25 1 10 2.525 Units V V mA mA V mV V mV V µA V µA mV mV mV mV — V mV V µA V 2062 Elect Table SUMMIT MICROELECTRONICS, Inc. 2062 2.3 6/19/03 5 SMH4802 Preliminary Information AC OPERATING CHARACTERISTICS Symbol Description Min. Typ. 5 50* tCBD Programmable 50mV Circuit Breaker Delay (filter) 150 400 5* 20 tPGD Programmable Power Good Delay 80 160 tQTSD tCYC Quick T ip Shut Down r Circuit breaker cycle time 5 Off* 5 tPUVF Programmable Under-/Over-V ltage Filter o 80 160 0.5 tSD Startup Delay Q 5 80 * 160 * = Default value Q After UV and OV become valid there is a delay — tSD — that precedes the turn on of VGATE. See Figure 6. R Fast Shut Down delay from Fault to the beginning of VGATE off. Max. Units µs ms 200 2.5 ns s s — ms ms ms ms ms ms ms 2062 AC Table 6 2062 2.3 6/19/03 SUMMIT MICROELECTRONICS, Inc. SMH4802 Preliminary Information I2C 2-WIRE SERIAL INTERFACE AC OPERATING CHARACTERISTICS Symbol fSCL tLOW tHIGH tBUF tSU:STA tHD:STA tSU:STO tAA tDH tR tF tSU:DAT tHD:DAT TI tWR Parameter SCL clock frequency Clock low period Clock high period Bus free time Start condition setup time Start condition hold time Stop condition setup time Clock edge to valid output Data Out hold time SCL and SDA rise time SCL and SDA fall time Data In setup time Data In hold time Noise filter SCL and SDA Write cycle time Noise suppression 250 0 100 5 SCL low to valid SDA (cycle n) SCL low (cycle n + 1) to SDA change Before new transmission Conditions Min. 0 4.7 4.0 4.7 4.7 4.0 4.7 0.2 0.2 1000 300 3.5 Max. 100 Units kHz µs µs µs µs µs µs µs µs ns ns ns ns ns ms 2062 Intf. Table I2C 2-WIRE SERIAL INTERFACE AC OPERATING CHARACTERISTICS Figure 3 shows a timing diagram for the Bus Interface Memory timing. One bit of data is transferred during each clock pulse. Note that data must remain stable when the clock is high. tR tF tHIGH tLOW SCL tSU:SDA tHD:DAT tSU:DAT tSU:STO tHD:SDA tBUF SDA In tAA tDH SDA Out 2050 Fig09 2.0 Figure 3. Bus Interface Memory Timing SUMMIT MICROELECTRONICS, Inc. 2062 2.3 6/19/03 7 SMH4802 Preliminary Information APPLICATIONS INFORMATION Powering VDD The 12V shunt regulator between the VDD and VSS pins allows the SMH4802 to operate over a wide range of supply voltages. It is necessary to use a series dropping resistor (RD) between the host power supply and the VDD pin in order to bias the shunt regulator and limit current into the device. System Enable The EN/TS input provides an active high comparator input that may be used as a master enable or temperature sense input. Under-/Over-Voltage Sensing The Under-Voltage (UV) and Over-Voltage (OV) inputs provide a set of comparators that act in conjunction with an external resistor divider network to sense when the host supply voltage exceeds the user defined limits. If the input to the UV pin rises above 2.5V, and the input to the OV pin falls below 2.5V, the power-up sequence may be initiated. If UV falls below 2.5V, or OV rises above 2.5V, the PG# and VGATE outputs will be shut down immediately. Under-/Over-Voltage Filtering The SMH4802 may also be configured so that an out of tolerance condition on UV/OV will not shut off the output immediately. A filter delay can be inserted so that only sustained under-voltage or over-voltage conditions will shut off the output. An out of tolerance condition on UV/ OV for longer than the filter delay time (tUOFLTR) will latch the VGATE and PG outputs in the off state if the UV/OV filter option is enabled. The Under-/Over-Voltage Filtering feature is disabled in the default configuration of the device. Under-Voltage Hysteresis The Under-Voltage comparator input may be configured with a programmable level of hysteresis. The compare level may be set in steps (up to 15) of 62.5mV below 2.5V. The default under-voltage hysteresis level is set to 62.5mV. Soft Start Slew Rate Control Once all of the preconditions for powering up the DC/DC converters have been met, the SMH4802 provides a means to soft start the external power FET limiting the in-rush current. Current limiting is generally needed due to the bulk capacitance across the power rails of the DC/DC converters. The VGATE output of the SMH4802 is current limited to IVGATE, allowing the slew rate to be easily modified using external passive components. 8 Load Control — Turning on a DC/DC Converter Once power has been ramped to the DC/DC converter, two conditions must be met before the PG# output can be asserted: the DRAIN SENSE voltage must be below 2.5V, and the VGATE voltage must be greater than VDD – VGT. The DRAIN SENSE input ensures the power MOSFET is not absorbing too much steady state power from operating at a high VDS. (This sensor remains active at all times, except during the current regulation period). The VGATE sensor ensures the power MOSFET is operating well into its saturation region before allowing the loads to be switched on. Once VGATE reaches VDD – VGT this sensor is latched. After the external MOSFET is properly switched on, the PG# output will be asserted after a delay of tPGD. The delay time is programmable from 5ms to 160ms. NOTE: The PG# output has a 12V withstand capability, so high voltages must not be connected to this pin. A bipolar transistor or an opto-isolator can be used to boost the withstand voltage to that of the host supply. Force Shutdown — Secondary Feedback The Force Shutdown signal (FS#) is an active low input that provides a method of receiving feedback from the secondary side of the DC/DC controllers. A built-in holdoff timer allows the SMH4802 to ignore the state of the FS# input until the time period expires. The FS# input must be driven high by the end of this time period. If not, a low level on this input will shut off the VGATE and PG# outputs. The purpose of the hold-off timer is to allow enough time for devices on the secondary side of the DC/DC controller to power-up and stabilize. This unique feature of the SMH4802 allows supervisory circuits, such as an SMS44, to control the shutdown of the primary side soft start circuit, even though the secondary side initially has no power. Circuit Breaker Operation The SMH4802 provides a number of circuit breaker functions to protect against over current conditions. A sustained over-current event could damage the host supply and/or the load circuitry. The board’s load current passes through a series resistor (RS) connected between the MOSFET source (which is tied to CBSENSE) and VSS. The breaker trips (Figure 4) whenever the voltage drop across RS is greater than 50mV for more than tCBD (a programmable filter delay ranging from 10µs to 500µs). 2062 2.3 6/19/03 SUMMIT MICROELECTRONICS, Inc. SMH4802 Preliminary Information APPLICATIONS INFORMATION (Continued) 2.5V UV CBSENSE tCBD 50mV tPUVF tCYC VGATE VGATE 2062 Fig05 2062 Fig04 Figure 4. Under-/Over-Voltage Filter Timing Figure 5. Circuit Breaker Cycle Mode Power-on Timing Figure 6 illustrates some power on sequences, including the UV and OV differentials to their reference, and Power Good cascading. Refer to the AC operating characteristics table for more information on the tCBD timing. VDD 11 ≤ VDD ≤ 13