SMH4804

SMH4804 -48V Programmable Hot Swap Sequencing Power Controller – – FEATURES AND APPLICATIONS INTRODUCTION The SMH4804 is a user-programmable -48V power supply controller designed to control the hot-swapping of plug-in cards and to sequence supplies in a distributed power environment. The SMH4804 drives an external power MOSFET switch that connects the bus side supply to the card side load and controls in-rush current while providing both current regulation and over-current protection. When the source and drain voltages of the external MOSFET are within specification, the SMH4804 asserts four PG[4:1]# power-good logic outputs either simultaneously or sequenced at programmable intervals to enable DC-DC converters to distribute card side power. Additional features of the device include: UV and OV monitor, master enable or temperature sense input (EN/ TS), 2.5V and 5V reference outputs for expanding monitor functions, two Pin-Detect enable inputs (PD1# and PD2#) for card insertion verification, and duty-cycle or latched over-current protection modes. All features are programmed in nonvolatile registers through the I2C interface which is simplified with the SMX3200 interface adapter and Windows GUI software available from Summit Microelectronics. Engineers can program the device directly in-circuit with units of voltage, current and time, allowing fast design cycles. Features: • Soft Starts Main Power Supply on Card Insertion or System Power Up • In-Rush Current Limiting • Master Enable to Allow System Control of Power Up or Down • Programmable Independent Control of up to 4 DC/DC Converters via 4 Power Good Signals, PG[4:1]# • Highly Programmable Circuit Breaker Level and Mode – Programmable Quick-Trip™ Value, Current Limiting, Duty Cycle Times, and Over-Current Filter • Programmable Host Voltage Fault Monitoring – Programmable UV/OV Filter and UV Hysteresis • Programmable Fault Mode: Latched or Duty Cycle • Internal Shunt Regulator Allows for a Wide Supply Range (typically -32 to -72 Volts) • I2C 2-Wire Serial Bus Interface for Programming, Power On/Off and Operational Status Applications: • Telecom Hot-Swap Card • Distributed Power Architectures • Power-on LAN, IEEE 802.3 – SIMPLIFIED APPLICATION DRAWING 9 571 9 ' 'XDO 00%' 9 6KRUW 3LQV 9 ' 9 ' 5 .  5 .  966  5 .  29  5' . : 5  5    9'' 3' 3'  95()  95()  )6  $  $  $  6'$  6&/   9LQ 9RXW   2Q2II  9RXW  9LQ 9 , & 3*  60+ 89 'UDLQ6HQVH &%6HQVH 3*  3*       9LQ 9RXW  2Q2II 9RXW  9LQ 9 9*DWH 3*   1RWH     9LQ 9RXW 2Q2II   9RXW 9LQ 9    & Q) 5   5 .  5 . & Q) ' 00%' ' 9 ' 9 & Q) 5  & Q)   9LQ 9RXW  2Q2II   9LQ 9RXW 9 4 ,5)1 1RWH  6DIHW\ LVRODWLRQ LQWHUIDFH PD\ EH UHTXLUHG 6HH $SSV 6HFWLRQ Figure 1. SMH4804 Simplified Application Diagram © SUMMIT Microelectronics, Inc. 2002 • 300 Orchard City Drive #131 • Campbell CA 95006 • Phone 408 378-6461 • Fax 408 378-6596 • www.summitmicro.com 2050 3.7 10/30/02 1 Functional Block Diagram – SMH4804 FUNCTIONAL BLOCK DIAGRAM SCL 11 SDA 10 2.5VREF 20 ENPGA ENPGB ENPGC 23 22 21 50kΩ 27 PG4# 50kΩ VDD 12VREF 28 50kΩ PROGRAMMING STEERING LOGIC 50kΩ 50kΩ PROGRAMMABLE DELAY 24 PG3# 50kΩ 200kΩ PROGRAMMABLE DELAY + – + PROG REF – + P. D. FILTER PROGRAMMABLE DELAY 25 EN/TS PD1# PD2# 50kΩ 4 10µA + – 26 PG2# 5 6 UV 15 PG1# 17 1 DRAIN SENSE 5V 12V 2.5V VSS A0 A1 A2 MODE RESET# 14 2 13 16 9 8 PROGRAMMABLE DELAY 50mV CBSENSE 12 Programmable Quick Response Ref. Voltage 2 – Three @ 50kΩ 50kΩ 50kΩ DEVICE ADDRESS DECODE P. D. FILTER + – + – OV OV/UV FILTER 19 5.0VREF VGATE SENSE 3 VGATE FAULT LATCH AND DUTY CYCLE TIMER 7 FAULT# Programmable Shutdown Timer 18 FS# 2050 BD Figure 2. SMH4804 Block Diagram 2050 3.7 10/30/02 Summit Microelectronics SMH4804 –\ Functional Description FUNCTIONAL DESCRIPTION The SMH4804 integrated hot swap power controller operates within a wide supply range, typically -32 to -72 volts, and generates the signals necessary to drive isolatedoutput DC/DC converters. The general start-up procedure is as follows: • A physical connection must first be made with the chassis to discharge any electrostatic voltage potentials when a typical add-in board is inserted into the powered backplane. • The board then contacts the long pins on the backplane that provide power and ground. • As soon as power is applied the device starts up, but does not immediately apply power to the output load. • Under-voltage and over-voltage circuits inside the controller verify that the input voltage is within a userspecified range. • The SMH4804 senses the PD1# and PD2# pin detection signals to indicate the card is seated properly. These requirements must be met for a Pin Detect Delay period of tPDD. Once this time has elapsed, the hot-swap controller enables VGATE to turn on the external power MOSFET switch. The VGATE output is current limited to IVGATE, allowing the slew rate to be easily modified using external passive components. During the controlled turn-on period the VDS of the MOSFET is monitored by the drain sense input. When DRAIN SENSE drops below 2.5V, and VGATE rises above VDD – VGT, the SMH4804 asserts the PG1# through PG4# power good outputs to enable the DC/ DC controllers. The ENPGA, ENPGB, and ENPGC Power Good Enable inputs may be used to activate or deactivate specific output loads. Steady-state operation is maintained as long as all conditions are normal. Any of the following events may cause the device to disable the DC/DC controllers by shutting down the power MOSFET: • an under-voltage or over-voltage condition on the host power supply. • an over-current event detected on the CBSENSE input • a failure of the power MOSFET sensed via the DRAIN SENSE pin. • the PD1#/PD2# pin detect signals becoming invalid. • the master enable (EN/TS) falls below 2.5V. • the FS# input is driven low by events on the secondary side of the DC/DC controllers. The SMH4804 may be configured so that after any of these events occurs, the VGATE output shuts off and either latches into an off state, or recycles power after a cooling down period, tCYC. Summit Microelectronics Powering VDD The SMH4804 contains an internal shunt regulator on the VDD pin that prevents the voltage from exceeding 12V. It is necessary to use a dropper resistor (RD) between the host power supply and the VDD pin in order to limit current into the device and prevent possible damage. The dropper resistor allows the device to operate across a wide range of system supply voltages, typically -32 V to -72V, and also helps protect the device against common-mode power surges. Refer to the Applications Section for help on calculating the RD resistance value. Hot-Swap Verification There are several enabling inputs that allow the host to control the SMH4804. The Pin Detect signals (PD1# and PD2#) are two active low enables that are generally used to indicate that the add-in circuit card is properly seated. These inputs must be held low for a pin-detect delay period of tPDD before a power-up sequence may be initiated. This is typically done by clamping the inputs to VSS through the implementation of an ejector switch, or alternatively through the use of staggered pins at the card-cage interface. The pin detect delay (tPDD) timing parameter is controlled by bits 1:0 of register 9. Refer to Register 9 - Address 1001 on page 38 for more information. Two shorter pins, arranged at opposite ends of the connector, force the card to be fully seated before both pin detects are enabled. Care must be taken not to exceed the maximum voltage rating of these pins during the insertion process. Refer to details in the Applications Section for proper circuit implementation. Note that the PD1# and PD2# inputs are enabled or disabled using bit 0 of Register 3. Refer to Register 3 - Address 0011 on page 32 for more information. The EN/TS input provides an active high comparator input that may be used as a master enable or temperature sense input. This input signal must exceed 2.5V (nominal) for proper operation. Refer to the Pin Descriptions on page 10 for more information. Under-/Over-Voltage Sensing The Under-Voltage (UV) and Over-Voltage (OV) inputs provide a set of comparators that act in conjunction with an external resistive divider ladder to sense whether or not the host supply voltage is within the user-defined limits. The power-up sequence is initiated when the input to the UV pin rises above 2.5V and the input to the OV pin falls below 2050 3.7 10/30/02 3 Functional Description 2.5V for a period of at least tPDD (Pin Detect Delay time). The tPDD filter helps prevent spurious start-up sequences while the card is being inserted. If UV falls below 2.5V or OV rises above 2.5V, the PG[4:1]# and VGATE outputs are disabled immediately. SMH4804 The falling voltage compare level may be set in steps of 62.5mV below 2.5V. The rising voltage compare level is fixed at 2.5V. The default under-voltage hysteresis level is set to 62.5mV. In default conditions the SMH4804 is not in an under-voltage state once the UV voltage rises above 2.5V; and after that an under-voltage occurrence is not recognized until the UV voltage falls below 2.4375V (2.5V – 62.5mV). Under-/Over-Voltage Filtering The SMH4804 can be configured so that an out-oftolerance condition on UV/OV does not shut off the output immediately. Instead, a filter delay may be inserted so that only sustained under-voltage or over-voltage conditions can shut off the output. An out-of-tolerance condition on UV/OV for longer than the filter delay time (tUOFLTR in Figure 3) causes the VGATE and PG[4:1]# outputs to shut off when the UV/OV filter option is enabled using bits 2:1 of Register 4. The under-/over-voltage filtering feature is disabled (bits 2:1 = 00) in the default configuration. Refer to Register 4 Address 0100 on page 33 for more information on the filter delay options. The UV and OV filters are enabled and disabled by programming bits 3 and 2 of Register 6 respectively. Refer to Register 6 - Address 0110 on page 36 for more information. Note that the delay values in Register 4 are only valid if the corresponding over or under voltage filtering is enabled using bits 3:2 of Register 6. Figure 3 shows the timing for the under-/over-voltage filter. Soft Start Slew Rate Control Once all of the preconditions for powering up the DC/DC controllers have been met as explained in the previous sections, the SMH4804 provides a means to soft start the external power MOSFET. It is important to limit in-rush current to prevent damage to the add-in card or disruptions to the host power supply. For example, charging the filter capacitance too quickly (normally required at the input of the DC/DC controllers) may generate very high current. The VGATE output of the SMH4804 is current limited to IVGATE, allowing the slew rate to be easily modified using external passive components. The slew rate may be found by dividing IVGATE by the gate-to-drain capacitance placed on the external FET. Load Control — Sequencing the Secondary Supplies The PG1# through PG4# output pins are used to enable the external DC/DC controllers. Once the card is inserted, the SMH4804 samples the PD1# and PD2# pin detect input pins to determine if the card as been inserted properly. It then monitors the state of the UV and OV input pins to assure there is no under-voltage or over-voltage condition present. Once these conditions are met, and the EN/TS pin is greater than 2.5V, the SMH4804 asserts the VGATE output to turn on the external MOSFET. During the time it takes to turn the MOSFET on, the SMH4804 monitors the system for an over-current condition via the CBSENSE input pin. In addition, the device internally monitors the voltage level on the VGATE output pin. This is shown by the ‘VGATE Sense’ block in Figure 2. Once power has been ramped to the DC/DC controllers, two conditions must be met before the PG[4:1]# outputs can be enabled: • the DRAIN SENSE input voltage must be below 2.5V. • the VGATE voltage must be greater than VDD – VGT, where VGT is the gate threshold. The DRAIN SENSE input helps ensure that the power MOSFET is not absorbing too much steady state power from operating at a high VDS. This sensor remains active at all times (except when current regulation is enabled). The Summit Microelectronics 2.5V OV / UV tUOFLTR FAULT# 2050 Fig07 Figure 3. Under-/Over-Voltage Filter Timing Under-/Over-Voltage Latching An additional option for an out-of-tolerance condition on UV/ OV is to latch the VGATE and PG[4:1]# outputs off such that a return to normal UV/OV operation does not turn them back on. In this case the FAULT# output is asserted. Under-Voltage Hysteresis The Under-Voltage comparator input may be configured with a programmable level of hysteresis using Register 7. 4 2050 3.7 10/30/02 SMH4804 VGATE sensor makes sure that the power MOSFET is operating well into its saturation region before allowing the loads to be switched on. Once VGATE reaches VDD – VGT this sensor is latched. PG1# Functional Description tPGD When the external MOSFET is properly switched on the PG[4:1]# outputs may be enabled. Output PG1# is activated first, followed by PG2# after a delay of tPGD, PG3# after another tPGD delay, and PG4# after a final tPGD delay. The delays built into the SMH4804 allow timed sequencing of power to the loads. The delay times are programmable from 50µs to 160ms using bits 3:2 of Register 3 and bit 3 of Register 9. Refer to Register 3 - Address 0011 on page 32 and Register 9 - Address 1001 on page 38 for more information. The ENPGA, ENPGB, and ENPGC input pins in Figure 5 are used to enabled the PG[4:1]# outputs. The ENPGA pin controls the PG[4:2]# outputs. If ENPGA is deasserted by external logic, the SMH4804 disables the PG[4:2]# outputs and they enter the high-impedance state. The ENPGA input must be asserted in order for PG[4:2]# to be driven by the SMH4804. The ENPGB pin controls the PG[4:3]# outputs. If ENPGB is deasserted by external logic, the SMH4804 disables the PG[4:3]# outputs and they enter the high-impedance state. The ENPGB input must be asserted in order for PG[4:3]# to be driven by the SMH4804. The ENPGC pin controls the PG[4]# output. If ENPGC is deasserted by external logic, the SMH4804 disables the PG[4]# outputs and the output enters the high-impedance state. The ENPGC input must be asserted in order for PG[4]# to be driven by the SMH4804. This cascaded control mechanism is useful for enabling supplies that have dependencies based on the other voltages in the system. The PG[4:1] outputs have a 12V withstand capability, so high voltages must not be connected to these pins. Bipolar transistors or opto-isolators can be used to boost the withstand voltage to that of the host supply. Refer to Figure 18 for connectivity information. Figure 5 shows the relationship between the PG[4:1]# and the ENPG[C:A] signals. ENPGA tPGD PG2# ENPGB tPGD PG3# ENPGC PG4# 2050 Fig02 2.1 Figure 4. PG Output and ENPG Input Relationship Forced Shutdown — Secondary Feedback The Forced Shutdown signal (FS#) is an active low input that provides a method of receiving feedback from the secondary side of the DC/DC controllers. A built-in shutdown timer allows the SMH4804 to ignore the state of the FS# input until the timer period expires. The timer period is defined in bits 2:0 of Register 5. The FS# input must be driven high by the end of this timer period. A low level on this input causes a Fault condition, driving the FAULT# pin low and shutting off the VGATE and PG[4:1]# outputs. The purpose of the shutdown timer is to allow enough time for devices on the secondary side of the DC/DC controllers to power up and stabilize. This feature allows supervisory circuits such as an SMS44 to control the shutdown of the primary side soft start circuit, even though the secondary side initially has no power. Alternatively, the FS# input can be programmed to act as a fourth ENPG input controlling the PG1# output. This is combined with an option to independently enable PG1# with no affect on the other PG[4:2]# outputs, or it can be programmed so PG1# is the enabling output for the other outputs. Summit Microelectronics 2050 3.7 10/30/02 5 Functional Description Circuit Breaker Operation The SMH4804 provides a number of circuit breaker functions to protect against over-current conditions. A sustained over-current event could damage the host supply and/or the load circuitry. The board’s load current passes through a series resistor (RS) connected between the MOSFET source (which is tied to CBSENSE) and VSS. The breaker trips whenever the voltage drop across RS is greater than 50mV for more than tCBD (a programmable filter delay ranging from 10µs to 500µs). The circuit breaker cycle time is controlled via bit 0 of Register 4. RESET# TCBD CBSENSE SMH4804 50mV TPDD VGATE TCBRST Figure 5 shows the circuit breaker duty cycle operation with RESET# high. 2050 Fig04 2.1 Figure 6. Circuit Breaker Reset with RESET# Low Quick-TripTM Circuit Breaker TCBD CBSENSE 50mV TCBD TCYC VGATE The SMH4804 provides a Quick-Trip™ feature that causes the circuit breaker to trip immediately if the voltage drop across 56 exceeds VQCB. The Quick-Trip level may be set to 60mV, 100mV (default), 200mV, or the feature may be disabled. Refer to bits 1:0 of Register 2 - Address 0010 on page 31 for more information. Figure 7 shows the circuit breaker ‘Quick Trip’ response.In this figure, the voltage rises above VQCB, causing VGATE to be deasserted. 2050 Fig03 1.0 Figure 5. Circuit Breaker Duty Cycle Operation with RESET# High Figure 6 shows the behavior of VGATE and CBSENSE immediately after RESET# is deasserted. The circuit breaker cycle time can be programmed to a value of either 2.5 seconds of 5 seconds depending on the system configuration. Refer to bit 0 of Register 4 - Address 0100 on page 33 for more information on selecting the circuit breaker cycle time.