SMS46GR00

SUMMIT MICROELECTRONICS, Inc. SMS46 PRELIMINARY INFORMATION 1 (SEE LAST PAGE) Quad Programmable Precision Supervisory Controller With Independent Resets and 4k-Bit Nonvolatile Memory FEATURES Operational from any of four Voltage Monitoring Inputs Four Independent Programmable Reset Outputs Programmability allows monitoring any voltage between 0.6V and 5.6V with no external components Programmable 5mV steps in the low range Programmable Watchdog Timer Programmable Reset Pulse Width Fault Status Register 4k-Bit Nonvolatile General Purpose Memory APPLICATIONS Desktop/Notebook/Tablet Computers Multi-voltage Systems Telecom/Network Servers Portable Battery-powered Equipment Set-top Boxes Data-storage Equipment INTRODUCTION The SMS46 is a highly programmable voltage supply controller and supervisory circuit designed specifically for advanced systems that need to monitor multiple voltages. The SMS46 can monitor four separate voltages without the need of any external voltage divider circuitry. This alleviates the need for factory-trimmed threshold voltages and the use of external components to accommodate different supply voltages and tolerances. The SMS46 has four programmable independant reset outputs to control different devices for varying reset conditions such as UV, OV, watchdog and user pushbutton applications. The SMS46 watchdog timer has a user programmable time-out period and it can be placed in an idle mode for system initialization or system debug. All of the functions are user accessible through an industry standard I2C serial interface. Programming of configuration, control and calibration values by the user is simplified with the SMX3200 interface adapter and Windows GUI software obtainable from Summit Microelectronics. SIMPLIFIED APPLICATION DRAWING I2C Vpullup (0 to +12V) 7 3.3V Monitored 2.5V Supplies 1.8V 1.2V RESET# From uP 16 2 3 14 1 15 V0 V1 V2 V3 MR# WLDI GND 8 0.1µF VDD_CAP 12 6 9 10 11 4 5 13 LCD A2 A1 SDA SCL RESET#0 uP/DSP ASIC/FPGA Logic SMS46 RESET#1 RESET#2 RESET#3 Figure 1 - Precision Quad Power Supply Monitor can monitor any voltage over the range of 0.6V to 5.6V. One of the four supplies must be above 2.7V to power the SMS46. ©SUMMIT MICROELECTRONICS, Inc., 2004 • 1717 Fox Dr. • San Jose, CA 95131 • Phone 408-436-9890 • FAX 408-436-9897 • 2083 1.1 06/04/04 Characteristics subject to change without notice www.summitmicro.com 1 SMS46 Preliminary Information FUNCTIONAL BLOCK DIAGRAM VDD_CAP 50kΩ CONFIGURATION REGISTER 11 RESET#0 MR# 1 V0 16 NV DAC + REF – PROGRAMMABLE RESET PULSE GENERATOR 4 RESET#1 5 RESET#2 V1 2 NV DAC + REF – 13 RESET#3 V2 3 NV DAC + REF – SERIAL BUS CONTROL LOGIC 9 SDA 10 SCL 7 A2 6 A1 V3 14 NV DAC + REF – PROGRAMMABLE WATCHDOG TIMER SUPPLY ARBITRATION 50kΩ 15 WLDI 4K-BIT NV MEMORY VDD_CAP V0 V1 V2 V3 12 8 VDD_CAP GND 2 2083 1.1 06/04/04 SUMMIT MICROELECTRONICS, Inc. SMS46 Preliminary Information PIN CONFIGURATION PIN NAMES Pin 1 MR# V1 V2 RESET#1 RESET#2 A1 A2 GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 V0 WLDI V3 RESET#3 VDD_CAP RESET#0 SCL SDA Name MR# V1 V2 RESET#1 RESET#2 A1 A2 GND SDA SCL RESET#0 VDD_CAP RESET#3 V3 WLDI V0 Function Manual reset input Voltage supply and monitor input Voltage supply and monitor input Reset#1 output Reset#2 output Address input Address input Power supply return Serial data I/O Serial data clock Reset#0 output Power supply output Reset#3 output Voltage supply and monitor input Watchdog timer interrupt Voltage supply and monitor input 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SUMMIT MICROELECTRONICS, Inc. 2083 1.1 06/04/04 3 SMS46 Preliminary Information ABSOLUTE MAXIMUM RATINGS* Temperature Under Bias ........................ –55°C to 125°C Storage Temperature ............................. –65°C to 150°C Lead Solder Temperature (10s) ........................... 300 °C Terminal Voltage with Respect to GND: V0, V1, V2, and V3 ......... –0.3V to 6.0V RESET#0-3 ..................... –0.3V to 15V All Others ....................... –0.3V to 6.0V Junction Temperature.......................…….....…...150°C ESD Rating per JEDEC……………………..….…..2000V Latch-Up testing per JEDEC………..…….......…±100mA *Note - Stresses beyond the listed Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. RECOMMENDED OPERATING CONDITIONS Industrial Temperature Range............... –40ºC to +85ºC. Commercial Temperature Range..............–5ºC to +70ºC. VSUPPLY Supply Voltage............................2.7V to 5.5V VSUPPLY = Device supply voltage provided by the highest VX input. Package Thermal Resistance (θJA) 16 Lead SSOP…………………….………….…23oC/W Moisture Classification Level 1 (MSL 1) per J-STD- 020 RELIABILITY CHARACTERISTICS Data Retention………………….…………..…..100 Years Endurance……………………….…..…….100,000 Cycles DC OPERATING CHARACTERISTICS (Over Recommended Operating Conditions; Voltages are relative to GND) Symbol Parameter Notes 1V min. refers to a valid reset output being generated Min. 1.0 Typ. Max. 5.5 Unit V VDD Operating supply voltage Memory read/write operations: at least one of the V inputs must be at or above VDD min. VDD ≤ 5.5V; V0 trip point 4.7V; V1, V2, V3 = GND; MR# = VDD; all outputs floating Configuration register or memory access 2.7 5.5 V 200 400 3 µA mA V V % mV kΩ IDD Supply current Programmable threshold VPTH Range (low range) VPTH Programmable threshold Range (high range) VPTHACC VHYST RPU VOL VIL VIH Programmable threshold Accuracy VRST hysteresis Pull-up resistance Low voltage output Reset threshold voltage range V0 to V3 (5mV increments) Reset threshold voltage range V0 to V3 (15mV increments) VPTH is the programmed threshold setpoint within the VPTH Range See Note 1 below MR# and WLDI pins ISINK = 1mA, VVDD_CAP ≥ 2.7V ISINK = 200µA, VVDD_CAP = 1.0V 0.6 1.8 –1.0 VPTH TBD 50 1.875 5.625 1.0 0.3 0.3 0.6 0.7 × VDD V V V V Input threshold Note 1: Low Range Hysteresis = 4.2 X (Vtrip - 0.5 volts) mV. For Vtrip = 1.0 volts, Hysteresis = 2.1 mV (0.21 %), High Range Hysteresis = 12.6 X (Vtrip -0.5 volts) mV. For Vtrip = 5.0 volts, Hysteresis = 56.7 mV (1.13%). 4 2083 1.1 06/04/04 SUMMIT MICROELECTRONICS, Inc. SMS46 Preliminary Information AC OPERATING CHARACTERISTICS (Over Recommended Operating Conditions; Voltages are relative to GND) Symbol Parameter Notes Min. 19 Typ. 25 50 100 200 20 OFF Max. 31 63 125 250 Unit ms ms ms ms µs — tPRTO Programmable reset pulse width 38 75 150 tDRST Vin to RESET# delay 100mV overdrive 300 tPWDTO Programmable Watchdog timer period 600 1200 2400 4800 TMR TDMRRST MR# input pulse width Delay from MR# low to RESET# low Minimum pulse required to bring Reset active 400 800 1600 3200 6400 300 200 500 1000 2000 4000 8000 ms ms ms ms ns ns SUMMIT MICROELECTRONICS, Inc. 2083 1.1 06/04/04 5 SMS46 Preliminary Information PIN DESCRIPTIONS V0, V1, V2, V3 (16, 2, 3, 14) These inputs are used as the voltage monitor inputs and as the voltage supply for the SMS46. Internally they are actively diode ORed and the input with the highest voltage potential will be the default supply voltage (VDD_CAP). The RESET# outputs will be valid if any one of the four inputs is above 1V. However, for full device operation at least one of the inputs must be at 2.7V or higher. The sensing threshold for each input is independently programmable in 5mV increments from 0.6V to 1.875V or 15mV increments from 1.8V to 5.625V. Also, the occurrence of an under- or over-voltage condition that is detected as a result of the threshold setting can be used to generate a RESET#0-3. The programmable nature of the threshold voltage eliminates the need for external voltage divider networks. GND Power supply return. MR# (1) The manual reset input always generates a RESET#0-3 output whenever it is driven low. The duration of the RESET# output pulse will be initiated when MR# goes low and it will stay low for the duration of MR# low pulse plus the programmed reset time-out period (tPRTO). MR# must be held low during a configuration register write or read. This signal is pulled up internally through a 50kΩ resistor. RESET#0-3 (11, 4, 5, 13) The reset outputs are active low open drain outputs. They are driven low whenever the MR# input is low or whenever a triggering under-voltage or over-voltage condition exists on the corresponding input channel or when the Watchdog timer expires. The four voltage monitor inputs are always functioning, but their ability to generate a reset is programmable (configuration register 4). Refer to Figures 2, 3 and 5 for a detailed illustration of the relationship between MR#, RESET#0-3 and the VIN levels. VPTH-UV V0 — V3 tPRTO RESET# tDRST Figure 3 - RESET# Timing VDD_CAP (12) The VDD_CAP pin connects to the internal supply voltage for the SMS46. A capacitor is placed on this pin to filter supply noise as well as hold up the device in the event of power failure. The voltage on this node is determined by the highest input voltage. Loading of this pin should be minimized to prevent excessive power dissipation in the part. WLDI (15) Watchdog input. A low to high transition on the WLDI input will clear the watchdog timer, effectively starting a new time-out period. This signal is pulled up internally through a 50kΩ resistor. If WLDI is stuck low and no low-to-high transition is received within the programmed tPWDTO period (programmed watch dog time-out) the RESET#0-3 outputs will be driven low. Holding WLDI high will not block the Watchdog from timing out and generating a reset. Refer to Figure 4 for a detailed illustration of the relationship between RESET#0-3 and WLDI. A1, A2 (6, 7) A1 and A2 are the address inputs. When addressing the SMS46 memory or configuration registers the address inputs distinguish which one of four possible devices sharing the common bus is being addressed. SDA (9) SDA is the serial data input/output pin. It should be tied to VDD_CAP through a pull-up resistor. MR# tDMRRST RESET# tPRTO Figure 2 - RESET# Timing with MR# 6 2083 1.1 06/04/04 SUMMIT MICROELECTRONICS, Inc. SMS46 Preliminary Information PIN DESCRIPTIONS (CONTINUED) SCL (10) SCL is the serial clock input. It should be tied to VDD_CAP through a pull-up resistor. t0 tPWDTO t0 t0 t0 t0 tPRTO RESET# tPRTO WLDI 2047 Fig04 3.0 tPWDTO Figure 4 - Watchdog and WLDI Timing V0 V P T H -U V R ESET#0 tD R S T tPR TO V P T H -O V V1 R ESET#1 tDR ST tPR TO Figure 5 - V0-1 Inputs and Resulting RESET# Behavior with V0 set to UV and V1 set to OV sensing. SUMMIT MICROELECTRONICS, Inc. 2083 1.1 06/04/04 7 SMS46 Preliminary Information DEVICE OPERATION AND CONFIGURATION REGISTERS SUPPLY AND MONITOR FUNCTIONS The V0, V1, V2, and V3 inputs are internally ORed so that any one of the four can act as the device supply. The RESET# outputs will be guaranteed true so long as one of the four pins is at or above 1V. Note: for performing a memory operation (Read or Write) and to have the ability to change configuration register contents at least one supply input must be above 2.7V. Read/Write operations require a 0.1µF capacitor from the VDD_CAP node to GND. For optimum performance connect capacitors from each of the Vx inputs to GND. Locate the capacitors as physically close to the SMS46 as possible. Associated with each input is a comparator with a programmable threshold for detection of under-voltage or overvoltage conditions on any of the four supply inputs. The threshold can be programmed in 5mV increments anywhere within the range of 0.6V to 1.875V or 15mV increments within the range of 1.8V to 5.625V. Configuration registers 0, 1, 2, and 3 adjust the thresholds for V0, V1, V2, and V3 respectively. If the value contained in any register is all zeroes, the corresponding threshold will be 0.6V. If the contents were low range 05HEX the threshold would then be 0.625V [0.6V + (5 × 0.005V)]. All four registers are configured as 8-Bit registers. D7 MSB 1 0 0 D6 1 0 0 D5 1 0 0 D4 1 0 0 D3 1 0 0 D2 1 0 1 D1 1 0 1 D0 LSB 1 0 0 Action Highest threshold adjustment = 5.625V (High Range) Lowest threshold adjustment = 0.6V (Low Range) Threshold = 0.6V + (6×0.005V) = 0.625V (e.g.) Table 1. Configuration Registers 0, 1, 2, and 3 RESET# FUNCTION Each RESET# output has a programmable source for activation. Configuration register 4 is used for enabling the activation source. A monitor input can be programmed to activate on either an under-voltage or over-voltage condition, but not both conditions. When this condition ceases, each individual RESET# output will remain active for tPRTO (programmable reset time-out). The reset threshold voltage range for V0 to V3 can be set for 5mV increments below 1.875V (low Range = "0") or for 15mV increments above 1.8V (high range = "1") using Bits D3:0. The RESET#0-3 outputs have two hardwired sources for activation: the MR# input and Watchdog timer. All D7 MSB V3 D6 V2 D5 V1 D4 V0 D3 V3 D2 V2 D1 V1 D0 LSB V0 Action RESET# outputs will remain active so long as MR# is low, and will continue driving the RESET# outputs for tPRTO (programmable reset time out) after MR# returns high. The MR# input cannot be bypassed or disabled. Refer to Figures 1, 2 and 3 for a detailed illustration of the relationships among the affected signals. The SMS46 provides the option of the monitors triggering on either an under-voltage or over-voltage condition. The low-order four bits of configuration register 5 program these options. WATCHDOG TIMER The SMS46 contains an independent timer that can be programmed. The Watchdog generates all RESET#s if it times out. The timer is cleared by a low to high transition on WLDI and will reset all four RESET#. If the watchdog should time-out the device status can be monitored in the status register (Table 4). Refer to Figure 3 which illustrates the action of RESET#0-3 with respect to the Watchdog timer and the WLDI input. Voltage Threshold Range Select RESET Trigger Enable 0 1 0 1 0 1 0 1 Low Range High Range Table 2. Configuration Register 4 8 2083 1.1 06/04/04 SUMMIT MICROELECTRONICS, Inc. SMS46 Preliminary Information DEVICE OPERATION AND CONFIGURATION REGISTERS (CONTINUED) Action Writing a 0 enables undervoltage detection for the selected V input Writing a 1 enables overvoltage detection for the selected V input D3 MSB V3 0 D2 V2 0 D1 V1 0 D0 LSB V0 0 Action OFF 400ms 800ms 1600ms 3200ms 6400ms D2 WD2 0 0 1 1 1 1 D1 WD1 0 1 0 0 1 1 D0 LSB WD0 0 1 0 1 0 1 1 1 1 1 Table 3. Configuration Register 5 (D0 through D3) If WLDI is held low the timer will free-run generating a series of resets. When RESET# returns high (after tPRTO) the timer is reset to time zero. Register 6 is also used to set the programmable reset time-out period (tPRTO). D7 MSB V3 0 1 D6 V2 0 1 D5 V1 0 1 D4 LSB V0 0 1 Table 6. Configuration Register 6 (D0, D1, D2) Action Reading a 1 indicates the source of out of limit fault D7 MSB D6 Address Select Lock x AS0 0 1 x x Action DTI = 1010, responds only when address bits = A2 & A1 logic states DTI = 1011, responds only when address bits = A2 & A1 logic states Config. Reg. Read/Write enabled Config. Reg. Read/Write locked out 1 Table 4. Status Register 5 (D4 through D7) D7 MSB Read1 Only 1 1 1 1 D6 RTO1 0 0 1 1 D5 RTO0 0 1 0 1 D4 Read Only x x x x D3 Read Only x x x x Action tPRTO = 25ms tPRTO = 50ms tPRTO = 100ms tPRTO = 200ms x 0 1 Note 1 - Setting this bit will cause a permanent Read/Write Lock out. Table 7. Configuration Register 7 (D7, D6) Bits D5 through D0 are not used. Table 5. Configuration Register 6 (D3 through D7) Note 1 - Read Only bit D7 is set to a 1. Read only bits D4 and D3 are revision control and the value indicates the status code of the device (ie. 01 is status code 1). SUMMIT MICROELECTRONICS, Inc. 2083 1.1 06/04/04 9 SMS46 Preliminary Information DEVELOPMENT HARDWARE & SOFTWARE SMX3200 PROGRAMMER The end user can use the summit SMX3200 programming cable and software that have been developed to operate with a standard personal computer. The programming cable interfaces directly between a PC’s parallel port and the target application. The application’s values are entered via an intuitive graphical user interface employing dropdown menus. The latest revisions of all software and an application brief describing the SMX3200 is available from the website (www.summitmicro.com). The Windows GUI software will generate the data and send it in I2C serial bus format so that it can be directly downloaded to the SMS46 via the programming Dongle and cable. An example of the connection interface is shown in Figure 6. When design prototyping is complete, the software can generate a HEX data file that should be transmitted to Summit for approval. Summit will then assign a unique customer ID to the HEX code and program production devices before the final electrical test operations. This will ensure proper device operation in the end application. D1 1N4148 VDD_CAP Top view of straight 0.1" x 0.1 closed-side connector. SMX3200 interface cable connector. Pin 10, Reserved Pin 8, Reserved Pin 6, MR# Pin 4, SDA Pin 2, SCL Pin 9, 5V Pin 7, 10V Pin 5, Reserved Pin 3, GND Pin 1, GND SMS46 MR# SDA SCL 10 8 6 4 2 9 7 5 3 1 C1 0.1µF GND Figure 6 - SMX3200 Programmer I2C serial bus connections to program the SMS46. 10 2083 1.1 06/04/04 SUMMIT MICROELECTRONICS, Inc. SMS46 Preliminary Information I2C INTERFACE MEMORY OPERATION Data for the configuration registers and the memory array are read and written via an industry standard two-wire interface. The bus was designed for two-way, two-line serial communication between different integrated circuits. The two lines are a serial data line (SDA) and a serial clock line (SCL). The SDA line must be connected to a positive supply by a pull-up resistor, located somewhere on the bus. See Memory Operating Characteristics: Table 8 and Figure 7. Input Data Protocol The protocol defines any device that sends data onto the bus as a transmitter and any device that receives data as a receiver. The device controlling data transmission is called the Master and the controlled device is called the Slave. In all cases the SMS46 will be a Slave device, since it never initiates any data transfers. One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during clock high time because changes on the data line while SCL is high will be interpreted as start or stop condition. MIN 0 4.7 4.0 Before new transmission 4.7 4.7 4.0 4.7 SCL low to valid SDA (cycle n) SCL low (cycle n+1) to SDA change 0.2 0.2 1000 300 250 0 Noise suppression 100 5 3.5 TYP MAX 100 Units kHz µs µs µs µs µs µs µs µs ns ns ns ns ns ms 2047 Table10 4.0 Symbol fSCL tLOW tHIGH tBUF tSU:STA tHD:STA tSU:STO tAA tDH tR tF tSU:DAT tHD:DAT TI tWR Parameter SCL clock frequency Clock low period Clock high period Bus free time (1) Star t condition setup time Star t condition hold time Stop condition setup time Clock edge to valid output Data Out hold time SCL and SDA rise time (1) SCL and SDA fall time (1) Data In setup time Data In hold time Noise filter SCL and SDA Write cycle time Conditions Note (1): These values are guaranteed by design. Table 8. Memory Operating Characteristics tR tF tHIGH tLOW SCL tSU:STA tHD:DAT tSU:DAT tSU:STO tHD:STA tBUF SDA In tAA tDH SDA Out 2047 Fig09 Figure 7 - Memory Operating Characteristics SUMMIT MICROELECTRONICS, Inc. 2083 1.1 06/04/04 11 SMS46 Preliminary Information I2C INTERFACE (CONTINUED) START and STOP Conditions When both the data and clock lines are high the bus is said to be not busy. A high-to-low transition on the data line, while the clock is high, is defined as the Start condition. A low-to-high transition on the data line, while the clock is high, is defined as the Stop condition. See Figure 8. D7 MSB D6 D5 D4 D3 D2 D1 D0 LSB R/W x Address Bits Device Type SMS46 1 1 0 0 0 0 1 1 1 0 1 x Bus x MSB x Configuration Register Memor y (default) Alternate Memor y START Condition SCL STOP Condition 1 Table 9. Slave Addresses SDA In 2047 Fig10 Figure 8 - START and STOP Conditions Read/Write Bit The last bit of the data stream defines the operation to be performed. When set to 1 a Read operation is selected; when set to 0 a Write operation is selected. WRITE OPERATIONS Acknowledge (ACK) Acknowledge is a software convention used to indicate successful data transfers. The transmitting device, either the Master or the Slave, will release the bus after transmitting eight bits. During the ninth clock cycle the receiver will pull the SDA line low to Acknowledge that it received the eight bits of data. The Master will leave the SDA line high (NACK) when it terminates a read function. The SMS46 will respond with an Acknowledge after recognition of a Start condition and its slave address byte. If both the device and a write operation are selected the SMS46 will respond with an Acknowledge after the receipt of each subsequent 8-Bit word. In the READ mode the SMS46 transmits eight bits of data, then releases the SDA line, and monitors the line for an Acknowledge signal. If an Acknowledge is detected and no Stop condition is generated by the Master, the SMS46 will continue to transmit data. If a NACK is detected the SMS46 will terminate further data transmissions and await a Stop condition before returning to the standby power mode. Device Addressing Following a Start condition the Master must output the address of the Slave it is accessing. The most significant four bits of the Slave address are the device type identifier/address. For the SMS46 the default is 1010BIN. The next two bits are the Bus Address. The next bit (the 7th) is the MSB of the memory address. The SMS46 allows two types of Write operations: byte Write and page Write. A byte Write operation writes a single byte during the nonvolatile write period (tWR). The page Write operation, limited to the memory array, allows up to 16 bytes in the same page to be written during tWR. Byte Write After the Slave address is sent (to identify the Slave device and select either a Read or Write operation), a second byte is transmitted which contains the low order 8 bit address of any one of the 512 words in the array. Upon receipt of the word address the SMS46 responds with an Acknowledge. After receiving the next byte of data it again responds with an Acknowledge. The Master then terminates the transfer by generating a Stop condition, at which time the SMS46 begins the internal Write cycle. While the internal Write cycle is in progress the SMS46 inputs are disabled and the device will not respond to any requests from the Master. Page Write (memory only) The SMS46 is capable of a 16-byte page Write operation. It is initiated in the same manner as the byte Write operation, but instead of terminating the Write cycle after the first data word the Master can transmit up to 15 more bytes of data. After the receipt of each byte the SMS46 will respond with an Acknowledge. The SMS46 automatically increments the address for subsequent data words. After the receipt of each word the low order address bits are internally incremented by one. SUMMIT MICROELECTRONICS, Inc. 12 2083 1.1 06/04/04 SMS46 Preliminary Information I2C INTERFACE (CONTINUED) The high order bits of the address byte remain constant. Should the Master transmit more than 16 bytes, prior to generating the Stop condition, the address counter will rollover and the previously written data will be overwritten. As with the byte Write operation, all inputs are disabled during the internal Write cycle. Refer to Figure 11 for the address, Acknowledge, and data transfer sequence. Master SDA Slave S T A R Device Type Bus T Address Address Typical Write Operation (Standard memory device type) A AA A AA AA 7 65 4 32 10 A C K A C K DDDDDDDD 76543210 A C K S T O P 1010 R BB AAA/ 218W Up to 15 additional bytes can be written before issuing the stop. N AS CT KO P Master SDA Slave S T A R T Typical Reading Operation (Alternate memory device type) BB R AAA/ 218W A C K AAAAAAAA 76543210 S T AA CR KT 1 01 1 1 01 1 BBAR AA / 218W A C K DDDDDDDD 76543210 Master SDA Slave S T A R T Writing Configuration Registers R BB AAX/ W 21 A C K S T O P DDDDDDDD 76543210 A C K A C K 1 00 1 CCCCCCCC 76543210 Master SDA Slave S T A R T Reading the Configuration Register BB R AAX/ 21 W A C K CCCCCCCC 76543210 S T AA CR KT N AS CT KO P 1 00 1 1 00 1 BB R AAX/ 21 W A C K DDDDDDDD 76543210 2047 Fig11 Figure 9 - Read and Write Operations SUMMIT MICROELECTRONICS, Inc. 2083 1.1 06/04/04 13 SMS46 Preliminary Information I2C INTERFACE (CONTINUED) Acknowledge Polling When the SMS46 is performing an internal Write operation it will ignore any new Start conditions. Since the device will only return an acknowledge after it accepts the Start the part can be continuously queried until an acknowledge is issued, indicating that the internal Write cycle is complete. See the flow chart for the proper sequence of operations for polling. Current Address Read (memory only) The SMS46 contains an internal address counter which maintains the address of the last word accessed, incremented by one. If the last address accessed (either a Read or Write) was to address location n, the next Read operation would access data from address location n+1 and increment the current address pointer. When the SMS46 receives the Slave address field with the R/W bit set to 1 it issues an acknowledge and transmits the 8-Bit word stored at address location n+1. The current address byte Read operation only accesses a single byte of data. The Master sets the SDA line to NACK and generates a stop condition. At this point the SMS46 discontinues data transmission. Random Address Read (Register and Memory) Random address Read operations allow the Master to access any memory location in a random fashion. This operation involves a two-step process. First, the Master issues a write command which includes the start condition and the Slave address field (with the R/W bit set to Write), followed by the address of the word it is to Read. This procedure sets the internal address counter of the SMS46 to the desired address. After the word address acknowledge is received by the Master it immediately reissues a Start condition, followed by another Slave address field with the R/W bit set to READ. The SMS46 will respond with an Acknowledge and then transmit the 8 data bits stored at the addressed location. At this point the Master sets the SDA line to NACK and generates a Stop condition. The SMS46 discontinues data transmission and reverts to its standby power mode. Sequential READ (Memory Only) Sequential Reads can be initiated as either a current address Read or random access Read. The first word is transmitted as with the other byte Read modes (current address byte Read or random address byte Read); however, the Master now responds with an Acknowledge, indicating that it requires additional data from the SMS46. The SMS46 continues to output data for each Acknowledge received. The Master terminates the sequential Read operation by responding with a NACK, and issues a Stop condition. During a sequential Read operation the internal address counter is automatically incremented with each Acknowledge signal. For Read operations all address bits are incremented, allowing the entire array to be read using a single Read command. After a count of the last memory address the address counter will rollover and the memory will continue to output data. Write Cycle In Progress Issue Start Issue Stop Issue Slave Address and R/W = 0 ACK Returned Yes No Next Operation a Write? Yes Issue Address No Issue Stop Proceed With Write Await Next Command 2047 Fig12 Figure 10 - Write Flow Chart READ OPERATIONS Read operations are initiated with the R/W bit of the identification field set to 1. There are two different Read options: 1. Current Address Byte Read, and 2. Random Address Byte Read. 14 2083 1.1 06/04/04 SUMMIT MICROELECTRONICS, Inc. SMS46 Preliminary Information APPLICATIONS V0 V1 V2 V3 D1 2 1 4 3 5 J1 6 8 7 10 9 1 16 2 3 14 12 10 9 6 7 C1 MR# RESET#0 RESET#1 V0 RESET#2 V1 RESET#3 V2 V3 SMS46 VDD_CAP SCL SDA WLDI A1 A2 GND 8 11 4 5 13 15 2047 Fig13 Figure 11 - Application Schematic NOTES: 1. C1 is a 0.1µF. 2. Connector J1 is an SMX3200 (see Figure 6). 3. D1 is a 1N4148 SUMMIT MICROELECTRONICS, Inc. 2083 1.1 06/04/04 15 SMS46 Preliminary Information DEFAULT CONFIGURATION REGISTER SETTINGS - SMS46GC-238 R eg ister R 00 R 01 R 02 R 03 R 04 R 05 R 06 R 07 C o n ten ts 56 28 A0 14 F3 X0 C5 40 F u n ctio n V 0 thresho ld set to 3 .09 0V V 1 thresho ld set to 2 .40 0V V 2 thresho ld set to 1 .40 0V V 3 thresho ld set to 0 .70 0V R eset T rigger source set for all ch an nels, V 0, V 1 set to hig h ran ge and V 2, V 3 set to lo w ra nge U pper b its are vola tile statu s ind ication of input supp ly conditio n. V 0, V 1, V 2 and V 3 set to m onitor U V U nder V oltag e. R eset tim eout set to 100m s, W atchdog T im er set to 1.6s. B its D 4 and D 3 ind icate revisio n contro l. E E m em ory s la ve address is 1011, C onfig uration registers are un lock ed. The default device ordering number is SMS46GC-238, is programmed as described above and tested over the commercial temperature range. PACKAGE 16 PIN SSOP PACKAGE 0.189 - 0.197 (4.80 - 5.00) Ref. JEDEC MO-137 0.228 - 0.244 (5.79 - 6.20) Inches (Millimeters) Pin 1 0.150 - 0.157 (3.81 - 3.99) 0.053 - 0.069 (1.35 - 1.75) 0.007 - 0.010 (0.18 - 0.25) 0” Min to 8” Max 0.016 - 0.050 (0.41 - 1.27) 0.025 (0.635) 0.008 - 0.012 (0.20 - 0.31) 0.059 MAX (1.50) 0.004 - 0.010 (0.10 - 0.25) 16 Pin SSOP 16 2083 1.1 06/04/04 SUMMIT MICROELECTRONICS, Inc. SMS46 Preliminary Information PART MARKING SUMMIT SMS46G Summit Part Number xx Status Tracking Code (Blank, MS, ES, 01, 02,...) (Summit Use) Annn AYYWW Pin 1 Identifier Date Code (YYWW) Lot tracking code (Summit use) Part Number suffix (Contains Customer specific ordering requirements) Drawing not to scale Product Tracking Code (Summit use) ORDERING INFORMATION SM S46 G C nnn P a r t N u m b e r S u ffix (s e e p a g e 1 7 ) S p e c if ic r e q u ir e m e n t s a r e c o n t a in e d in t h e s u f f ix s u c h a s H e x c o d e , H e x c o d e r e v is io n , e t c . S u m m it P a r t Num ber Package G =16 Lead SSO P Tem p Range C = C o m m e r c ia l B la n k = I n d u s t r ia l NOTICE NOTE 1 - This is a Preliminary Information data sheet that describes a Summit product currently in pre-production with limited characterization. SUMMIT Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained herein reflect representative operating parameters, and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked, SUMMIT Microelectronics, Inc. shall not be liable for any damages arising as a result of any error or omission. SUMMIT Microelectronics, Inc. does not recommend the use of any of its products in life support or aviation applications where the failure or malfunction of the product can reasonably be expected to cause any failure of either system or to significantly affect their safety or effectiveness. Products are not authorized for use in such applications unless SUMMIT Microelectronics, Inc. receives written assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of SUMMIT Microelectronics, Inc. is adequately protected under the circumstances. Revision 1.1 - This document supersedes all previous versions. Please check the Summit Microelectronics, Inc. web site at www.summitmicro.com for data sheet updates. © Copyright 2004 SUMMIT MICROELECTRONICS, Inc. I2C is a trademark of Philips Corporation. 17 PROGRAMMABLE ANALOG FOR A DIGITAL WORLD™ SUMMIT MICROELECTRONICS, Inc. 2083 1.1 06/04/04