SPN4850

SPN4850 N-Channel Enhancement Mode MOSFET DESCRIPTION The SPN4850 is the N-Channel logic enhancement mode power field effect transistors are produced using high cell density , DMOS trench technology. This high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage application , notebook computer power management and other battery powered circuits where high-side switching . FEATURES 60V/7.2A,RDS(ON)= 27mΩ@VGS= 10V 60V/6.8A,RDS(ON)= 32mΩ@VGS= 4.5V Super high density cell design for extremely low RDS (ON) Exceptional on-resistance and maximum DC current capability SOP – 8P package design APPLICATIONS DC/DC Converter Load Switch PIN CONFIGURATION(SOP – 8P) PART MARKING 2009 / 04 / 05 Ver.2 Page 1 SPN4850 N-Channel Enhancement Mode MOSFET PIN DESCRIPTION Pin 1 2 3 4 5 6 7 8 ORDERING INFORMATION Part Number SPN4850S8RG SPN4850S8RGB Symbol S S S G D D D D Description Source Source Source Gate Drain Drain Drain Drain Package SOP- 8P SOP- 8P Part Marking SPN4850 SPN4850 ※ SPN4850S8RG : 13” Tape Reel ; Pb – Free ※ SPN4850S8RGB : 13” Tape Reel ; Pb – Free ; Halogen -Free ABSOULTE MAXIMUM RATINGS (TA=25℃ Unless otherwise noted) Parameter Drain-Source Voltage Gate –Source Voltage Continuous Drain Current(TJ=150℃) Pulsed Drain Current Avalanche Current Power Dissipation Operating Junction Temperature Storage Temperature Range Thermal Resistance-Junction to Ambient TA=25℃ TA=70℃ TA=25℃ TA=70℃ Symbol VDSS VGSS ID IDM IAS PD TJ TSTG RθJA Typical 60 ±20 Unit V V A A A W ℃ ℃ ℃/W 7.2 6.8 40 15 2.5 1.6 -55/150 -55/150 80 2009 / 04 / 05 Ver.2 Page 2 SPN4850 N-Channel Enhancement Mode MOSFET ELECTRICAL CHARACTERISTICS (TA=25℃ Unless otherwise noted) Parameter Static Drain-Source Breakdown Voltage Gate Threshold Voltage Gate Leakage Current Zero Gate Voltage Drain Current On-State Drain Current Drain-Source On-Resistance Forward Transconductance Diode Forward Voltage Dynamic Total Gate Charge Gate-Source Charge Gate-Drain Charge Input Capacitance Output Capacitance Reverse Transfer Capacitance Turn-On Time Turn-Off Time Symbol Conditions Min. Typ Max. Unit V(BR)DSS VGS=0V,ID=250uA VGS(th) VDS=VGS,ID=250uA IGSS IDSS ID(on) RDS(on) gfs VSD Qg Qgs Qgd Ciss Coss Crss td(on) tr td(off) tf VDD=30V,RL=30Ω ID≡1.0A,VGEN=10V RG=6Ω VDS=30VGS=0V f=1MHz VDS=0V,VGS=±20V VDS=48V,VGS=0V VDS=48V,VGS=0V TJ=85℃ VDS≥5V,VGS =10V VGS= 10V,ID=7.2A VGS=4.5V,ID=6.8A VDS=15V,ID=6.2A IS=1.7A,VGS =0V 60 1.0 3.0 ±100 1 5 25 0.023 0.027 25 0.8 25 4.2 5.3 950 180 115 10 10 25 12 20 20 50 25 1400 0.027 0.032 1.2 30 V nA uA A Ω S V VDS=30V,VGS=10V ID= 6A nC pF nS 2009 / 04 / 05 Ver.2 Page 3 SPN4850 N-Channel Enhancement Mode MOSFET TYPICAL CHARACTERISTICS 2009 / 04 / 05 Ver.2 Page 4 SPN4850 N-Channel Enhancement Mode MOSFET TYPICAL CHARACTERISTICS 2009 / 04 / 05 Ver.2 Page 5 SPN4850 N-Channel Enhancement Mode MOSFET TYPICAL CHARACTERISTICS 2009 / 04 / 05 Ver.2 Page 6 SPN4850 N-Channel Enhancement Mode MOSFET SOP- 8 PACKAGE OUTLINE 2009 / 04 / 05 Ver.2 Page 7 SPN4850 N-Channel Enhancement Mode MOSFET Information provided is alleged to be exact and consistent. SYNC Power Corporation presumes no responsibility for the penalties of use of such information or for any violation of patents or other rights of third parties which may result from its use. No license is granted by allegation or otherwise under any patent or patent rights of SYNC Power Corporation. Conditions mentioned in this publication are subject to change without notice. This publication surpasses and replaces all information previously supplied. SYNC Power Corporation products are not authorized for use as critical components in life support devices or systems without express written approval of SYNC Power Corporation. ©The SYNC Power logo is a registered trademark of SYNC Power Corporation ©2004 SYNC Power Corporation – Printed in Taiwan – All Rights Reserved SYNC Power Corporation 9F-5, No.3-2, Park Street NanKang District (NKSP), Taipei, Taiwan 115 Phone: 886-2-2655-8178 Fax: 886-2-2655-8468 ©http://www.syncpower.com 2009 / 04 / 05 Ver.2 Page 8