TPS61252

TPS61252 www.ti.com SLVSAG3 – SEPTEMBER 2010 TINY 1.5-A BOOST CONVERTER WITH ADJUSTABLE INPUT CURRENT LIMIT Check for Samples: TPS61252 1 FEATURES Resistor Programmable Input Current Limit – ±20% Current Accuracy at 500 mA over Full Temperature Range – Programmable from 100 mA up to 1500 mA Up to 92% Efficiency VIN Range from 2.3 V to 6.0 V Power Good Indicates Appropriate Output Voltage Level Adjustable Output Voltage up to 6.5 V 100% Duty-Cycle Mode When VIN > VOUT Load Disconnect and Reverse Current Protection • • • • Short Circuit Protection Typical Operating Frequency 3.25 MHz Available in a 2×2-mm QFN-8 Package APPLICATIONS • • • • • USB Host Supplies from a Single Li-Ion Battery Current Limited Applications Li-Ion Applications Audio Applications RF-PA Buffer • • • • • • DESCRIPTION The TPS61252 device provides a power supply solution for products powered by either a three-cell alkaline, NiCd or NiMH battery, or an one-cell Li-Ion or Li-polymer battery. The wide input voltage range is ideal to power portable applications like mobile phones or for computer peripherals. The device has a resistor programmable (RILIM) input current limit and is suitable for a wide variety of applications. During light loads the device will automatically enter skip mode (PFM), which allows the converter to maintain the required output voltage, while only drawing 30 mA from the battery. This will allow maximum efficiency at lowest quiescent currents. TPS61252 allows the use of small inductors and input capacitors to achieve a small solution size. The possibility to reduce the current limit by a external resistor offers the potential use of physically even smaller inductors with lower rated current to further reduce total solution sizes of the power supply. During shutdown, the load is completely disconnected from the battery. The TPS61252 is available in a 8-pin QFN package measuring 2×2 mm (DSG). L1 1H VOUT L VIN VOUT 5.0 V R1 768 k CFF 100 pF R4 1M R2 243 k COUT 22 µF VIN 2.3 V to 6.0 V C1 10 µF EN ILIM FB RILIM 20 k GND PG Power Good Output TPS61252 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010, Texas Instruments Incorporated TPS61252 SLVSAG3 – SEPTEMBER 2010 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. AVAILABLE DEVICE OPTION TA –40°C to 85°C (1) (2) OUTPUT VOLTAGE Adjustable (1) PACKAGE MARKING QTI PACKAGE 8-Pin QFN PART NUMBER (2) TPS61252DSG Contact TI for other fixed output voltage options For detailed ordering information please check the PACKAGE OPTION ADDENDUM section at the end of this datasheet. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) MIN Voltage range (2) Temperature range ESD rating (3) (1) (2) (3) VIN, VOUT, SW, EN, PG, FB, ILIM Operating junction, TJ Storage, Tstg Human Body Model - (HBM) Charge Device Model - (CDM) –0.3 –40 –65 MAX 7 150 150 2 0.5 UNIT V °C °C kV kV Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability. All voltages are with respect to network ground terminal. ESD testing is performed according to the respective JESD22 JEDEC standard. THERMAL INFORMATION TPS61252 THERMAL METRIC qJA qJCtop qJB yJT yJB qJCbot (1) Junction-to-ambient thermal resistance Junction-to-case (top) thermal resistance Junction-to-board thermal resistance Junction-to-top characterization parameter Junction-to-board characterization parameter Junction-to-case (bottom) thermal resistance (1) DSG 8 PINS 80.2 93.5 54.2 0.9 59.3 20 UNITS °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. 2 Submit Documentation Feedback Product Folder Link(s): TPS61252 Copyright © 2010, Texas Instruments Incorporated TPS61252 www.ti.com SLVSAG3 – SEPTEMBER 2010 RECOMMENDED OPERATING CONDITIONS MIN Supply voltage at VIN Output voltage at VOUT Programmable valley switch current limit set by RILIM Operating free air temperature range, TA Operating junction temperature range, TJ 2.3 3.0 100 –40 –40 NOM MAX UNIT 6.0 6.5 1500 85 125 V V mA °C °C ELECTRICAL CHARACTERISTICS Over recommended free air temperature range, typical values are at TA = 25°C. Unless otherwise noted, specifications apply for condition VIN = EN = 3.6 V, VOUT = 5.0 V. DC/DC STAGE PARAMETER VFB Feedback voltage Maximum line regulation Maximum load regulation f rDS(on) Oscillator frequency High side switch on resistance Low side switch on resistance Reverse leakage current into VOUT IV(CL) IQ ISD OVP Programmable valley switch current limit Quiescent current Shutdown current Input over voltage protection threshold Falling Rising Falling Hysteresis 2.3 V ≤ VIN ≤ 6.0 V 2.3 V ≤ VIN ≤ 6.0 V Clamped to GND or VIN Rising referred to VFB Falling referred to VFB 92.5 87.5 95 90 10 140 20 1.0 0.5 97.5 92.5 EN = GND ILIM pin set to VIN RILIM = 20 kΩ (500mA) PFM enabled, device is not switching -20 30 0.85 6.4 6.5 2.0 0.1 0.4 2.1 3.5 1500 +20 TEST CONDITIONS MIN 1.182 TYP 1.2 0.5 0.5 3250 200 130 3.5 MAX 1.218 UNIT V % % kHz mΩ mΩ µA mA % µA mA V V V V V V µA % % µs °C °C CONTROL STAGE VUVLO VIL VIH Under voltage lockout threshold EN input low voltage EN input high voltage EN, PG input leakage current Power Good threshold voltage Power good delay Overtemperature protection Overtemperature hysteresis Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS61252 3 TPS61252 SLVSAG3 – SEPTEMBER 2010 www.ti.com PIN ASSIGNMENTS GND 1 d ose d Exp al Pa rm The 8 VIN 7 SW 6 EN 5 PG VOUT 2 FB 3 ILIM 4 Table 1. TERMINAL FUNCTIONS TERMINAL NAME EN FB GND ILIM PG SW VIN VOUT Exposed Thermal Pad NO. 6 3 1 4 5 7 8 2 I O I I O I/O I I Enable input. (1 enabled, 0 disabled) Voltage feedback pin Ground Adjustable input valley current limit. Can be connected to VIN for maximum current. Output power good (1 good, 0 failure; open drain) Connection for Inductor Supply voltage for power stage Boost converter output Must be soldered to achieve appropriate power dissipation and for mechanical reasons. Must be connected to GND. DESCRIPTION 4 Submit Documentation Feedback Product Folder Link(s): TPS61252 Copyright © 2010, Texas Instruments Incorporated TPS61252 www.ti.com SLVSAG3 – SEPTEMBER 2010 FUNCTIONAL BLOCK DIAGRAM SW VOUT VIN Gate Drive NMOS PMOS Valley Current Sense Softstart VREF Thermal Shutdown Undervoltage Lockout EN Control Logic Input Current Sense Averaging Circuit gm 1V VREF2 IAVE Error Amp. PG VOUT ILIM GND Error Amplifier Pulse Modulator PWM FB Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS61252 5 TPS61252 SLVSAG3 – SEPTEMBER 2010 www.ti.com PARAMETER MEASUREMENT INFORMATION L1 L VOUT VOUT VIN VIN EN ILIM FB R1 C2 C3 R4 C1 R2 R3 GND PG Power Good Output U1 Table 2. List of Components REFERENCE U1 L1 C1 C2 C3 R1 R2 R3 R4 DESCRIPTION TPS61252 1.0 mH, 2.1 A, 27 mΩ, 2.8 mm x 2.8 mm x 1.5 mm 1 x 4.7 mF, 10 V, 0805, X7R ceramic 1 x 100 pF, 50 V, 0603, COG ceramic 2 × 22 mF, 10 V, 0805, X7R ceramic MANUFACTURER Texas Instruments DEM2815C, TOKO GRM21BR71A475KA73, Murata GRM1885C1H101JA01B, Murata GRM21BR61A226ME51, Murata Depending on the output voltage of TPS61252, 1%, (all measurements with 5 V output voltage uses 768 kΩ) Depending on the output voltage of TPS61252, 1%, (all measurements with 5 V output voltage uses 240 kΩ) Depending on the input current limit of TPS61252, 1% 1 MΩ, 1% any 6 Submit Documentation Feedback Product Folder Link(s): TPS61252 Copyright © 2010, Texas Instruments Incorporated TPS61252 www.ti.com SLVSAG3 – SEPTEMBER 2010 TYPICAL CHARACTERISTICS TABLE OF GRAPHS DESCRIPTION Efficiency vs Output current (VOUT = 5.0 V, ILIM = 1.5 A) vs Output current in 100% Duty-Cycle Mode (VOUT = 5.0 V, ILIM = 1.5 A) vs Input voltage (VOUT = 5.0 V, ILoad = {10; 100; 1000 mA}) , ILIM = 1.5 A Maximum output current Output voltage Waveforms vs Input voltage (TPS61252, VOUT = 5.0 V) vs Output current (VOUT = 5.0 V, ILIM = 1.5 A) Load transient response (VIN < VOUT, ILIM = 500mA, Load change from 20 mA to 300 mA) Load transient response (VIN > VOUT, ILIM = 1000mA, Load change from 50 mA to 550 mA) Startup after enable (VOUT = 5.0 V, VIN = 3.6 V, ILIM = 500mA) Startup after enable (VOUT = 5.0 V, VIN = 3.6 V, ILIM = 1000mA) Startup after enable in 500 mA load (VOUT = 5.0 V, VIN = 3.6 V, ILIM = 1000mA) EFFICIENCY vs OUTPUT CURRENT 100 VI = 3.6 V 90 80 70 VI = 2.3 V VI = 2.7 V VI = 4.2 V FIGURE Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 EFFICIENCY vs OUTPUT CURRENT – IN 100% DUTY CYCLE MODE 100 VI = 5.5 V 90 80 VI = 6 V 70 Efficiency - % Efficiency - % VI = 3.3 V 60 50 40 30 20 10 0 0.0001 0.001 60 50 40 30 20 VO = 5 V, Ilim = max 0.01 0.1 IO - Output Current - A 1 10 0 0.001 0.01 0.1 IO - Output Current - A VO = 5 V, Ilim = max 1 Figure 1. Figure 2. Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS61252 7 TPS61252 SLVSAG3 – SEPTEMBER 2010 www.ti.com EFFICIENCY vs INPUT VOLTAGE 100 90 80 70 IO = 100 mA IO = 10 mA IO - Output Current - A MAXIMUM OUTPUT CURRENT vs INPUT VOLTAGE 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 2.3 IO (I_Lim = 1.5 A) IO (I_Lim = 1 A) IO = 1000 mA Efficiency - % 60 50 40 30 20 10 0 2.3 VO = 5 V, Ilim = max 2.7 3.1 3.5 3.9 4.3 4.7 5.1 VI - Input Voltage - V 5.5 5.9 IO (I_Lim = 0.5 A) IO (I_Lim = 0.2 A) IO (I_Lim = 0.1 A) 2.8 3.3 3.8 4.3 4.8 VI - Input Voltage - V 5.3 5.8 Figure 3. OUTPUT VOLTAGE vs OUTPUT CURRENT 5.1 5.075 5.05 VI = 2.3 V 5.025 5 4.975 VI = 4.2 V 4.95 4.925 4.9 0.00001 VI = 3.6 V VI = 3.3 V VI = 2.7 V Figure 4. LOAD TRANSIENT RESPONSE ILIM = 500 mA (20 to 300 mA) VIN = 3.6 V, ILIM = 0.5 A VOUT 100mV/div; 4.77V offset VO - Output Voltage - V Output Current @ 1 200mV/div Inductor Current 0.5A/div; 1.5A offset Time = 500 s/div 0.0001 0.001 0.01 IO - Output Current - A 0.1 1 Figure 5. Figure 6. 8 Submit Documentation Feedback Product Folder Link(s): TPS61252 Copyright © 2010, Texas Instruments Incorporated TPS61252 www.ti.com SLVSAG3 – SEPTEMBER 2010 LOAD TRANSIENT RESPONSE ILIM = 1000 mA (50 to 550 mA) VIN = 3.6 V, ILIM = 1.0 A STARTUP AFTER ENABLE ILIM = 500mA, NO LOAD VIN = 3.6 V, ILIM = 0.5 A VOUT 2.0V/div; -2V offset VOUT 100mV/div; 4.77V offset Output Current @ 1 500mV/div Inductor Current 0.5A/div; 0.5A offset Inductor Current 0.5A/div; 1.5A offset Voltage @ SW pin 2.0V/div; 8V offset Time = 500 s/div Time = 100 s/div Figure 7. STARTUP AFTER ENABLE ILIM = 1000mA, NO LOAD VIN = 3.6 V, ILIM = 1.0 A VOUT 2.0V/div; -2V offset Figure 8. STARTUP AFTER ENABLE ILIM = 1000mA, 500 mA LOAD VIN = 3.6 V, ILIM = 1.0 A VOUT 2.0V/div; -2V offset Inductor Current 0.5A/div; 0.5A offset Inductor Current 0.5A/div; 0.5A offset Voltage @ SW pin 2.0V/div; 8V offset Voltage @ SW pin 2.0V/div; 8V offset Time = 100 s/div Time = 100 s/div Figure 9. Figure 10. Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS61252 9 TPS61252 SLVSAG3 – SEPTEMBER 2010 www.ti.com DETAILED DESCRIPTION OPERATION The TPS61252 Boost Converter operates as a quasi-constant frequency adaptive on-time controller. In a typical application the frequency will be 3.25 MHz and is defined by the input to output voltage ratio and does not vary from moderate to heavy load currents. At light load currents the converter will automatically enter Power Save Mode and operates then in PFM (Pulse Frequency Modulation) mode. During pulse-width-modulation (PWM) operation the converter uses a unique fast response quasi-constant on-time valley current mode controller scheme which offers very good line and load regulation allowing the use of small ceramic input and output capacitors. Based on the VIN/VOUT ratio, a simple circuit predicts the required on-time. At the beginning of the switching cycle, the low-side NMOS switch is turned-on and the inductor current ramps up to a peak current that is defined by the on-time and the inductance. In the second phase, once the peak current is reached, the current comparator trips, the on-timer is reset turning off the switch, and the current through the inductor then decays to an internally set valley current limit. Once this occurs, the on-timer is set to turn the boost switch back on again and the cycle is repeated. The TPS61252 controls the input current through intelligent adjustment of a valley current limit that corrects the value in a way that it almost turns out as an average input current limit. The current can be adjusted with an accuracy of ±20%. This architecture with adaptive slope compensation provides excellent transient load response and requires minimal output filtering. Internal softstart and loop compensation simplifies the design process while minimizing the number of external components. CURRENT LIMIT OPERATION The current limit circuit employs a valley current sensing scheme. Current limit detection occurs during the off time through sensing of the voltage drop across the synchronous rectifier. The output voltage is reduced as the power stage of the device operates in a constant current mode. The maximum continuous output current (IOUT(CL)), before entering current limit (CL) operation, can be defined by Equation 1. 1 IOUT(CL) = (1 - D) g (IV(CL) + DIL ) 2 (1) The duty cycle (D) can be estimated by Equation 2 V gh D = 1 - IN VOUT and the peak-to-peak current ripple (ΔIL) is calculated by Equation 3 V gD DIL = IN Lg f (2) (3) The output current, IOUT(DC), is the average of the rectifier current waveform. When the load current is increased such that the lower peak is above the current limit threshold, the off-time is increased to allow the current to decrease to this threshold before the next on-time begins. When the current limit is reached the output voltage decreases if the load is further increased. SOFTSTART The TPS61252 has an internal softstart circuit that controls the ramp-up of the current during start-up and prevents the converter from inrush current that exceeds the set current limit. For typical 100 µs the current is ramped to the set current limit. After reaching the current limit threshold it stays there until VIN = VOUT then the converter starts switching and boosting up the voltage to its nominal output voltage. During the complete start-up the input current does not exceed the current limit that is set by resistor RILIM. 10 Submit Documentation Feedback Product Folder Link(s): TPS61252 Copyright © 2010, Texas Instruments Incorporated TPS61252 www.ti.com SLVSAG3 – SEPTEMBER 2010 POWER-SAVE MODE The TPS61252 integrates a power save mode to improve efficiency at light load. In power save mode the converter only operates when the output voltage trips below a set threshold voltage. It ramps up the output voltage with several pulses and goes into power save mode once the output voltage exceeds the set threshold voltage. During the power save operation when the output voltage is above the set threshold the converter turns off some of the inner circuits to save energy. The PFM mode is left and PWM mode entered in case the output current can no longer be supported in PFM mode. 100% DUTY-CYCLE MODE If VIN > VOUT the TPS61251 offers the lowest possible input-to-output voltage difference while still maintaining current limit operation with the use of the 100% duty-cycle mode. In this mode, the PMOS switch is constantly turned on. During this operation the output voltage follows the input voltage and will not fall below the programmed value if the input voltage decreases below VOUT. The output voltage drop during 100% mode depends on the load current and input voltage, and the resulting output voltage is calculated as: VOUT = VIN - (DCR + rDS(on) ) g IOUT (4) with: DCR is the DC resistance of the inductor rDS(on) is the typical on-resistance of the PMOS switch ENABLE The device is enabled by setting EN pin to a voltage above 1 V. At first, the internal reference is activated and the internal analog circuits are settled. Afterwards, the output voltage ramps up controlled by the softstart circuitry. The output voltage reaches its nominal value as fast as the current limit settings and the load condition allows it. The EN input can be used to control power sequencing in a system with several DC/DC converters. The EN pin can be connected to the output of another converter, to drive the EN pin high and getting a sequencing of supply rails. With EN = GND, the device enters shutdown mode. UNDER-VOLTAGE LOCKOUT (UVLO) The under voltage lockout circuit prevents the device from malfunctioning at low input voltages and the battery from excessive discharge. It disables the output stage of the converter once the falling VIN trips the under-voltage lockout threshold VUVLO which is typically 2.0V. The device starts operation once the rising VIN trips VUVLO threshold plus its hysteresis of 100 mV at typ. 2.1V. Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS61252 11 TPS61252 SLVSAG3 – SEPTEMBER 2010 www.ti.com POWER GOOD The device has a built in power good function to indicate whether the output voltage operates within appropriate levels. The power good output (PG) is set high after the feedback voltage reaches 95% of its nominal value and stays there until the feedback voltage falls below 90 % of the nominal value. The power good is operable as long as the converter is enabled and VIN is present. If the converter is disabled by pulling the EN pin low the PG open drain output is high resistive. That means it follows the voltage it is connected to via the pull-up resistor. If the converter is controlled by an external enable signal and the power good should indicate that the output is turned off the application circuit below should be used. L1 1H VOUT L VIN VOUT R1 768 k CFF 100 pF VIN 2.3 V to 6.0 V C1 10 µF 3.0 V to 6.5 V COUT 22 µF EN ILIM RILIM 20 k FB R2 243 k GND PG Power Good Output U1 Enable Logic Input R4 1 M INPUT OVER VOLTAGE PROTECTION This converter has a input over voltage protection that protects the device from damage due to a voltage higher than the absolute maximum rating of the input allows. If 6.5 V (typ.) at the input is exceeded the converter completely shuts down to protect its inner circuitry. If the input voltage drops below 6.4 V (typ.) it turns on the device again and enters normal start up. LOAD DISCONNECT AND REVERSE CURRENT PROTECTION Regular boost converters do not disconnect the load from the input supply and therefore a connected battery will be discharge during shutdown. The advantage of TPS61252 is that this converter is disconnecting the output from the input of the power supply when it is disabled. In case of a connected battery it prevents it from being discharge during shutdown of the converter. THERMAL REGULATION The TPS61252 contains a thermal regulation loop that monitors the die temperature. If the die temperature rises to values above 110 °C, the device automatically reduces the current to prevent the die temperature from further increasing. Once the die temperature drops about 10 °C below the threshold, the device will automatically increase the current to the target value. This function also reduces the current during a short-circuit-condition. THERMAL SHUTDOWN As soon as the junction temperature, TJ, exceeds 140°C (typical) the device enters thermal shutdown. In this mode, the High Side and Low Side MOSFETs are turned-off. When the junction temperature falls about 20 °C below the thermal shutdown, the device continuous the operation. 12 Submit Documentation Feedback Product Folder Link(s): TPS61252 Copyright © 2010, Texas Instruments Incorporated TPS61252 www.ti.com SLVSAG3 – SEPTEMBER 2010 APPLICATION INFORMATION EXAMPLE During the following Application Information section one specific example will be used to define and work with the different equations. Parameter Input Voltage Minimum Input Voltage Output Voltage Input Current Limit set by RILIM Feedback Voltage Switching Frequency Estimated Efficiency Inductor Value of Choice Symbol VIN VIN(min) VOUT ILIM VFB f h L1 Value 3.6 2.6 5.0 1000 1.2 3.25 90 1.0 Unit V V V mA V MHz % µH OUTPUT VOLTAGE SETTING The output voltage can be calculated by Equation 5: æ Rö VOUT = VFB g ç 1 + 1 ÷ R2 ø è (5) To minimize the current through the feedback divider network, R2 should be between 180k and 360k. The sum of R1 and R2 should not exceed ~1MΩ, to keep the network robust against noise. Regarding the example, R1 is 768 kΩ and R2 is 240 kΩ. An external feed forward capacitor C1 is required for optimum load transient response. The value of C1 should be 100pF. The connection from FB pin to the resistor divider should be kept short and away from noise sources, such as the inductor or the SW line. INPUT CURRENT LIMIT The input current limit is set by selecting the correct external resistor value. Equation 6 is a guideline for selecting the correct resistor value: 1.0V RILIM = g 10,000 ILIM (6) For a current limit of 1A the resistor value will be 10 kΩ MAXIMUM OUTPUT CURRENT The maximum output current is set by RILIM and the input to output voltage ratio and can be calculated by Equation 7: V gh IOUT(max) » ILIM g IN VOUT (7) Following the example IOUT(max) will be 648 mA at 3.6 V input voltage and will decrease with lower input voltage values due to the energy conservation. INDUCTOR SELECTION As for all switching power supplies two main passive components are required for storing the energy during operation. This is done by an inductor and an output capacitor. The inductor must be connected between VIN pin and SW pin to make sure that the TPS61252 device operates. To select the right inductor current rating the programmed input current limit as well as the current ripple through the inductor is necessary. An estimation of the maximum peak inductor current can be done using Equation 8. Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS61252 13 TPS61252 SLVSAG3 – SEPTEMBER 2010 www.ti.com IL(max) = ILIM + DIL = ILIM + VIN(min) g D Lg f with D = 1 - VIN(min) g h VOUT (8) Regarding the above example the current ripple (ΔIL) will be 426 mA and therefore an inductor with a rated current of about 1.5 A should be used. The TPS61252 is designed to work with inductor values between 1.0 µH and 2.2 µH. For typical applications a 1.5 µH inductor is recommended. Regarding the conversion factor and the need of a sufficient output current the rated current for the inductor drives into lower inductance values. Therefore the inductor value can be reduced down to 1.0 µH without degrading the stability. Reduced inductance values increase the current ripple that needs to be included in the peak current calculation for the inductor (Equation 8). Using standard boost converters the current through the inductor is defined by the switch current limit of the converters switches and therefore bigger inductors have to be chosen. TPS61252 allows you to reduce the current limit to the needs of the application regardless the maximum switch current limit of the converter. Programming a lower current value allows the use of smaller inductors without the danger to get into saturation. OUTPUT CAPACITOR For the output capacitor, it is recommended to use small ceramic capacitors placed as close as possible to the VOUT and GND pins of the IC. If, for any reason, the application requires the use of large capacitors which cannot be placed close to the IC, a smaller ceramic capacitor in parallel to the large one is highly recommended. This small capacitor should be placed as close as possible to the converters VOUT and GND pins. To get an estimate of the recommended minimum output capacitance, Equation 9 can be used. CMIN = IOUT g (VOUT - VIN ) (9) f g DV g VOUT Where ΔV is the maximum allowed output ripple. With a chosen ripple voltage of 10 mV, a minimum effective capacitance of 9.6 mF is needed regarding the example. The total ripple will be larger due to the ESR of the output capacitor. This additional component of the ripple can be calculated using Equation 10 VESR = IOUT g RESR (10) To maintain control loop stability a capacitor with twice the value (I. e. 22 µF) of the calculated minimum capacitance is required be used due to DC Bias effects. There are no additional requirements regarding minimum ESR. Larger capacitors cause lower output voltage ripple as well as lower output voltage drop during load transients but the total output capacitance value should not exceed values above 50 µF. INPUT CAPACITOR Multilayer ceramic capacitors are an excellent choice for input decoupling of the step-up converter as they have extremely low ESR and are available in small form factors. The input capacitors should be located as close as possible to the device. While a 10mF input capacitor is sufficient for most applications, larger values may be used to reduce input current ripple without limitations. Also low ESR tantalum capacitors may be used. NOTE DC Bias effect: High capacitance ceramic capacitors have a DC Bias effect, which will have a strong influence on the final effective capacitance. Therefore the right capacitor value has to be chosen very carefully. Package size and voltage rating in combination with dielectric material are responsible for differences between the rated capacitor value and the effective capacitance. A 10 V rated 0805 capacitor with 10 µF can have a effective capacitance of less than 5 µF at an output voltage of 5 V. 14 Submit Documentation Feedback Product Folder Link(s): TPS61252 Copyright © 2010, Texas Instruments Incorporated TPS61252 www.ti.com SLVSAG3 – SEPTEMBER 2010 CHECKING LOOP STABILITY The first step of circuit and stability evaluation is to look from a steady-state perspective at the following signals: • Switch node, SW • Inductor current, IL • Output ripple voltage, VOUT(AC) These are the basic signals that need to be measured when evaluating a switching converter. When the switching waveform shows large duty cycle jitter or the output voltage or inductor current shows oscillations, the regulation loop may be unstable. This is often a result of board layout and/or L-C combination. As the next step in the evaluation of the regulation loop, the load transient response is tested. The time between the load transient takes place and the turn on of the PMOS switch, the output capacitor must supply all of the current required by the load. VOUT immediately shifts by an amount equal to ΔI(LOAD) x ESR, where ESR is the effective series resistance of COUT. ΔI(LOAD) begins to charge or discharge COUT generating a feedback error signal used by the regulator to return VOUT to its steady-state value. The results are most easily interpreted when the device operates in PWM mode. During this recovery time, VOUT can be monitored for settling time, overshoot or ringing that helps judge the converter’s stability. Without any ringing, the loop has usually more than 60° of phase margin. Because the damping factor of the circuitry is directly related to several resistive parameters (e.g., MOSFET rDS(on)) that are temperature dependant, the loop stability analysis has to be done over the input voltage range, load current range, and temperature range. LAYOUT CONSIDERATIONS For all switching power supplies, the layout is an important step in the design, especially at high peak currents and high switching frequencies. If the layout is not carefully done, the regulator could show stability problems as well as EMI problems. Therefore, use wide and short traces for the main current path and for the power ground tracks. The input capacitor, output capacitor, and the inductor should be placed as close as possible to the IC. Use a common ground node for power ground and a different one for control ground to minimize the effects of ground noise. Connect these ground nodes at any place close to one of the ground pins of the IC. The feedback divider should be placed close to the IC to keep the feedback connection short. To lay out the ground, short traces and wide are recommended. This avoids ground shift problems, which can occur due to superimposition of power ground current and the feedback divider. Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPS61252 15 TPS61252 SLVSAG3 – SEPTEMBER 2010 www.ti.com 10mm (0.39in) GND VIN 7mm (0.27in) COUT CIN L1 R2 RILIM VOUT R1 CFF GND Figure 11. Suggested Layout (Top) THERMAL INFORMATION The implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added heat sinks and convection surfaces, and the presence of other heat-generating components affect the power-dissipation limits of a given component. Three basic approaches for enhancing thermal performance are listed below: • Improving the power dissipation capability of the PCB design – E.g. increase of the GND plane on the top layer which is connected to the exposed thermal pad – Use thicker cupper layer • Improving the thermal coupling of the component to the PCB • Introducing airflow in the system Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists, special care must be paid to thermal dissipation issues in board design. The maximum junction temperature (TJ) of the TPS61252 is 150°C. 16 Submit Documentation Feedback Product Folder Link(s): TPS61252 Copyright © 2010, Texas Instruments Incorporated PACKAGE OPTION ADDENDUM www.ti.com 2-Oct-2010 PACKAGING INFORMATION Orderable Device TPS61252DGST TPS61252DSGR TPS61252DSGT (1) Status (1) Package Type Package Drawing WSON WSON WSON DSG DSG DSG Pins 8 8 8 Package Qty 250 3000 250 Eco Plan TBD TBD TBD (2) Lead/ Ball Finish Call TI Call TI Call TI MSL Peak Temp Call TI Call TI Call TI (3) Samples (Requires Login) Samples Not Available Purchase Samples Purchase Samples PREVIEW ACTIVE ACTIVE The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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