TC14433AEPG

1 TC14433 TC14433A 3-1/2 DIGIT A/D CONVERTERS FEATURES s s s s s s s s s s s Accuracy ................... ±0.05% of Reading ±1 Count Two Voltage Ranges ............. 1.999V and 199.9 mV Up to 25 Conversions Per Second ZIN > 1000M Ohms Single Positive Voltage Reference Auto-Polarity and Auto-Zero Overrange and Underrange Signals Available Operates in Auto-Ranging Circuits Uses On-Chip System Clock or External Clock Wide Supply Range .................... e.g., ±4.5V to ±8V Package Available .................................. 24-Pin DIP 24-Pin CerDIP, 28-Pin SOIC and 28-Pin PLCC GENERAL DESCRIPTION The TC14433 is a low power, high-performance, monolithic CMOS 3-1/2 digit A/D converter. The TC14433 combines both analog and digital circuits on a single IC, thus minimizing the number of external components. This dualslope A/D converter provides automatic polarity and zero correction with the addition of two external resistors and two capacitors. The full-scale voltage range of this ratiometric IC extends from 199.9 millivolts to 1.999 volts. The TC14433 can operate over a wide range of power supply voltages, including batteries and standard 5-volt supplies. The TC14433 will interface with the TC7211A LCD display driver. The TC14433A features improved performance over the industry standard TC14433. Rollover, which is the measurement of identical positive and negative signals, is guaranteed to have the same reading within one count for the TC14433A. Power consumption of the TC14433A is typically 4 mW, approximately one-half that of the industry standard TC14433. 2 3 4 5 6 7 APPLICATIONS s s s s s s s s Portable Instruments Digital Voltmeters Digital Panel Meters Digital Scales Digital Thermometers Remote A/D Sensing Systems MPU Systems See Application Notes 19 and 21 ORDERING INFORMATION Part No. TC14433AEJG TC14433AELI TC14433AEPG TC14433COG TC14433EJG TC14433ELI TC14433EPG Package 24-Pin CerDIP 28-Pin PLCC 24-Pin Plastic DIP 24-Pin SOIC 24-Pin CerDIP 28-Pin PLCC 24-Pin Plastic DIP Temp.Range – 40°C to +85°C – 40°C to +85°C – 40°C to +85°C 0°C to +70°C – 40°C to +85°C – 40°C to +85°C – 40°C to +85°C FUNCTIONAL BLOCK DIAGRAM 20–23 MULTIPLEXER Q 0 –Q 3 BCD DATA DS 1 –DS 4 DIGIT STROBE RC 10 CLK1 11 CLK0 CLOCK 1'S 16–19 LATCHES POLARITY DETECT 10'S 100'S 1,000'S OVERFLOW 2 1 3 8 CO2 OFFSET 15 OR OVERRANGE CONTROL LOGIC 4 R 1 DISPLAY END OF UPDATE 9 14 CONVERSION DU EOC 5 R1 / C1 CMOS ANALOG SUBSYSTEM 6 C 1 7 CO 1 VREF REFERENCE VOLTAGE VAG ANALOG GROUND VX ANALOG INPUT VDD = PIN 24 VSS = PIN 13 VEE = PIN 12 INTEGRATOR 8 TC14433/A-6 10/21/96 TELCOM SEMICONDUCTOR, INC. 3-127 3-1/2 DIGIT A/D CONVERTERS TC14433 TC14433A ABSOLUTE MAXIMUM RATINGS* Supply Voltage (VDD – VEE) ...................... – 0.5V to +18V Voltage on Any Pin, Reference to VEE ....................... – 0.5V to (VDD + 0.5) DC Current, Any Pin .............................................. ±10mA Operating Temperature Range ............... – 40°C to +85°C Power Dissipation (TA < 70°C) Plastic PLCC .......................................................1.0W Plastic DIP .......................................................940mW SOIC ................................................................ 940mW CerDIP ............................................................... 1.45W Storage Temperature Range ................ – 65°C to +160°C Lead Temperature (Soldering, 10 sec) ................. +300°C *This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS: VDD = +5V, VEE = – 5V, C1 = 0.1µF (mylar), CO = 0.1µF, RC = 300kΩ, R1 = 470kΩ @ VREF = 2V, R1 = 27kΩ @ VREF = 200mV, unless otherwise specified. Symbol Parameter Analog Input SYE Rollover Error (Positive and Negative Full Scale Symmetry Linearity Output Reading (Note 1) Stability Output Reading (Note 2) Zero Output Reading Bias Current: Analog Input Reference Input Analog Ground Common-Mode Rejection Test Conditions 200mV Full Scale VIN –VIN = +VIN VREF = 2V VREF = 200mV VX = 1.99V, VREF = 2V VX = 199mV, VREF = 200mV VX = 0V, VREF = 2V TA = +25°C Min Typ Max –1 — +1 – 40°C < TA < +85°C Min Typ Max — — — Unit Counts NL SOR ZOR IIN – 0.05 – 1 count — — — — — — — +0.05 — — — 0 ±20 ±20 ±20 65 +0.05 +1 count 2 3 0 ±100 ±100 ±500 — — — — — — — — — — — — — — — — — — — — — — — — — — — — %rdg LSD LSD pA CMRR Digital VOL VOH IOH IOL fCLK IDU Power IQ VX = 1.4V, VREF = 2V, fOC = 32kHz VSS = 0V, "0" Level VSS = – 5V, "0" Level VSS = 0V, "1" Level VSS = – 5V, "1" Level VSS = 0V, VOH = 4.6V Source VSS = – 5V, VOH = 5V Source VSS = 0V, VOL = 0.4V Sink VSS = – 5V, VOL = – 4.5V Sink RC = 300kΩ dB Output Voltage Pins 14 to 23 (Note 3) Output Voltage Pins 14 to 23 (Note 3) Output Current Pins 14 to 23 Output Current Pins 14 to 23 Clock Frequency Input Current – DU Quiescent Current — — 4.95 4.95 – 0.2 – 0.5 0.51 1.3 — — 0 –5 5 5 – 0.36 – 0.9 0.88 2.25 66 ±0.00001 0.05 –4.95 — — — — — — — ±0.3 — — 4.95 4.95 – 0.14 – 0.35 0.36 0.9 — — — — — — — — — — — — 0.05 – 4.95 — — — — — — — ±1 V V mA mA kHz µA PSRR Supply Rejection VDD to VEE, ISS = 0, 14433A: VDD = 5, VEE = – 5 VDD = 8, VEE = –8 VDD to VEE, ISS = 0, 14433: VDD = 5, VEE = – 5 VDD = 8, VEE = –8 VDD to VEE, ISS = 0, VREF = 2V VDD = 5, VEE = – 5 — — — — — 0.4 1.4 0.9 1.8 0.5 2 4 2 4 — — — — — — — — — — — 3.7 7.4 3.7 7.4 — mA mV/V 3-128 TELCOM SEMICONDUCTOR, INC. 3-1/2 DIGIT A/D CONVERTERS TC14433 TC14433A NOTES: 1. Accuracy — The accuracy of the meter at full-scale is the accuracy of the setting of the reference voltage. Zero is recalculated during each conversion cycle. The meaningful specification is linearity. In other words, the deviation from correct reading for all inputs other than positive full-scale and zero is defined as the linearity specification. 2. The LSD stability for 200mV scale is defined as the range that the LSD will occupy 95% of the time. 3. Pin numbers refer to 24-pin DIP. 1 2 3 4 5 PIN CONFIGURATIONS VAG 1 VREF 2 VX 3 R1 4 R1/C1 5 24 VDD 23 Q3 22 Q2 21 Q1 20 Q0 VAG 1 VREF 2 VX 3 R1 4 R1/C1 5 C1 6 CO1 7 CO2 8 DU 9 CLK1 10 CLK0 11 VEE 12 24 VDD 23 Q3 22 Q2 21 Q1 20 Q0 1 TC14433COG (SOIC) 18 DS2 17 DS3 16 DS4 15 OR 14 EOC 13 VSS 19 DS C1 6 19 DS1 TC14433AEPG CO1 7 TC14433EPG 18 DS 2 CO2 8 TC14433AEJG 17 DS TC14433EJG 3 (PDIP) 16 DS4 DU 9 (CerDIP) CLK1 10 CLK0 11 VEE 12 15 OR 14 EOC 13 VSS VREF VAG VDD NC VX Q3 4 3 2 1 28 27 26 25 Q1 24 Q 0 23 DS R1 5 R1/C1 6 C1 7 NC 8 CO1 9 CO2 10 DU 11 12 13 14 15 16 17 18 Q2 1 TC14433AELI TC14433ELI (PLCC) 22 NC 21 DS 2 20 DS 19 DS4 6 7 3 CLK1 VEE VSS CLK0 EOC OR NC 8 TELCOM SEMICONDUCTOR, INC. 3-129 3-1/2 DIGIT A/D CONVERTERS TC14433 TC14433A PIN DESCRIPTIONS Pin No. Pin No. 24-Pin 24-Pin PDIP/CerDip SOIC 1 1 Pin No. 28-Pin PLCC 2 Symbol VAG Description This is the analog ground; it has a high input impedance — This pin determines the reference level for the unknown input voltage (VX) and the reference voltage (VREF). Reference voltage — Full-scale output is equal to the voltage applied to VREF. Therefore, full-scale voltage of 1.999V requires 2V reference and 199.9 mV full-scale requires a 200 mV reference. VREF functions as system reset also. When switched to VEE, the system is reset to the beginning of the conversion cycle. The unknown input voltage (VX) is measured as a ratio of the reference voltage (VREF) in a ratiometric A/D conversion. These pins are for external components used for the integration function in the dual slope conversion. Typical values are 0.1 µF (mylar) capacitor for C1. R1 = 470 kW (resistor) for 2V full-scale. R1 = 27 kW (resistor) for 200 mV full-scale. Clock frequency of 66 kHz gives 250 msec conversion time. See equation below for calculation of integrator component values. These pins are used for connecting the offset correction capacitor. The recommended value is 0.1 µF. Display update input pin — When DU is connected to the EOC output every conversion is displayed. New data will be strobed into the output latches during the conversion cycle if a positive edge is received on DU prior to the ramp-down cycle. When this pin is driven from an external source, the voltage should be referenced to VSS. Clock input pins — The TC14433 has its own oscillator system clock. Connecting a single resistor between CLK1 and CLK0 sets the clock frequency. A crystal or OC circuit may be inserted in lieu of a resistor for improved CLK1, the clock input, can be driven from an external clock source, which need only have standard CMOS output drive. This pin is referenced to VEE for external clock inputs. A 300 kW resistor yields a clock frequency of about 66 kHz. (See typical characteristic curves; see Figure 9 for alternate circuits.) Negative power current — Connection pin for the most negative supply. Please note the current for the output drive circuit is returned through VSS. Typical supply current is 0.8 mA. Negative power supply for output circuitry — This pin sets the low voltage level for the output pins (BCD, Digit Selects, EOC, OR). When connected to analog ground, the output voltage is from analog ground to VDD. If connected to VEE, the output swing is from VEE to VDD. The recommended operating range for VSS is between the VDD –3 volts and VEE. End of conversion output generates a pulse at the end of each conversion cycle. This generated pulse width is equal to one-half the period of the system clock. Overrange pin — Normally this pin is set high. When VX exceeds VREF the OR pin is low. 2 2 3 VREF 3 4 5 6 3 4 5 6 4 5 6 7 VX R1 R1/C1 C1 7 8 9 7 8 9 9 10 11 CO1 CO2 DU 10 11 10 11 12 13 CLK1 CLK0 12 12 14 VEE 13 13 16 VSS 14 14 17 EOC 15 15 18 OR 3-130 TELCOM SEMICONDUCTOR, INC. 3-1/2 DIGIT A/D CONVERTERS TC14433 TC14433A PIN DESCRIPTIONS (Cont.) Pin No. Pin No. 24-Pin 24-Pin PDIP/CerDip SOIC 16 17 18 19 20 21 22 23 24 16 17 18 19 20 21 22 23 24 1 Pin No. 28-Pin PLCC 19 20 21 23 24 25 26 28 28 8,15, 22 2 Symbol DS4 DS3 DS2 DS1 Q0 Q1 Q2 Q3 VDD NC Description Digit select pins — The digit select output goes high when the respective digit is selected. The MSD (1/2 digit) turns on immediately after an EOC pulse. The remaining digits turn on in sequence from MSD to LSD. To ensure that the BCD data has settled, an inter-digit blanking time of two clock periods is included. Clock frequency divided by 80 equals multiplex rate. For example, a system clock of 60 kHz gives a multiplex rate of 0.8 kHz. See Figure 12 for digit select timing diagram. BCD data output pins — Multiplexed BCD outputs contain three full digits of information during digit select DS2, DS3, DS4. During DS1, the 1/2 digit, overrange, underrange and polarity information is available. Refer to truth table. Positive power supply — This is the most positive power supply pin. Not Used. 3 4 5 6 7 CIRCUIT DESCRIPTION The TC14433 CMOS IC becomes a modified dualslope A/D with a minimum of external components. This IC has the customary CMOS digital logic circuitry, as well as CMOS analog circuitry. It provides the user with digital functions (such as counters, latches, multiplexers) and analog functions (such as operational amplifiers and comparators) on a single chip. Features of this system include auto-zero, high input impedances and auto-polarity. Low power consumption and a wide range of power supply voltages are also advantages of this CMOS device. The system's auto-zero function compensates for the offset voltage of the internal amplifiers and comparators. In this "ratiometric system," the output reading is the ratio of the unknown voltage to the reference voltage, where a ratio of 1 is equal to the maximum count of 1999. It takes approximately 16,000 clock periods to complete one conversion cycle. Each conversion cycle may be divided into 6 segments. Figure 7 shows the conversion cycle in 6 segments for both positive and negative inputs. Segment 1 — The offset capacitor (CO), which compensates for the input offset voltages of the buffer and integrator amplifiers, is charged during this period. However, the integrator capacitor is shorted. This segment requires 4000 clock periods. Segment 2 — During this segment, the integrator output decreases to the comparator threshold voltage. At this time, a number of counts equivalent to the input offset TELCOM SEMICONDUCTOR, INC. voltage of the comparator is stored in the offset latches for later use in the auto-zero process. The time for this segment is variable and less than 800 clock periods. START TIME SEGMENT NUMBER 1 2 3 4 5 6 VX TYPICAL POSITIVE INPUT VOLTAGE VX TYPICAL NEGATIVE INPUT VOLTAGE END Figure 7. Integrator Waveforms at Pin 6 C1 BUFFER – VX R1 INTEGRATOR + – + COMPARATOR + – Figure 8. Equivalent Circuit Diagrams of the Analog Section During Segment 4 of the Timing Cycle 3-131 8 3-1/2 DIGIT A/D CONVERTERS TC14433 TC14433A (A) Crystal Oscillator Circuit 10 CLK1 L C (B) LC Oscillator Circuit 10 CLK1 C 1 18M TC14433 11 CLK 0 11 C f= 1 2 2/LC TC14433 CLK 0 47k C2 10 pF < C1 AND C2 < 200 pF FOR L = 5 mH AND C = 0.01 µF, f ≅ 32 kHz Figure 9. Alternate Oscillator Circuits Segment 3 — This segment of the conversion cycle is the same as Segment 1. Segment 4 — Segment 4 is an up-going ramp cycle with the unknown input voltage (VX) as the input to the integrator. Figure 8 shows the equivalent configuration of the analog section of the TC14433. The actual configuration of the analog section is dependent upon the polarity of the input voltage during the previous conversion cycle. Segment 5 — This segment is a down-going ramp TC04 +5V 0.1 µF 1 3 2 period with the reference voltage as the input to the integrator. Segment 5 of the conversion cycle has a time equal to the number of counts stored in the offset storage latches during Segment 2. As a result, the system zeros automatically. Segment 6 — This is an extension of Segment 5. The time period for this portion is 4000 clock periods. The results of the A/D conversion cycle are determined in this portion of the conversion cycle. 20K –5V +5V 0.1 µF 300k RC 11 10 2 12 24 23 22 21 4 20 5 TC14433 6 13 3 1 7 8 9 14 15 19 18 17 16 0.1 0.1 µF 1 4 2 3 5 +5V +5V SEGMENT RESISTORS 150 Ω (7) 7 6 5 4 3 2 1 –5V –5V 10 11 12 13 14 15 16 MINUS SIGN 200Ω MPS-A12 PLUS SIGN 110Ω COMMON ANODE LED DISPLAY 0.1 µF MPS-A12 (4) –5V Vx * R1 16 –5V 0.1 µF** 0.1 µF –5V 9 10 11 12 13 4543B 14 15 867 1413 fgedcba 14013B –5V 6 5 1 S DQ 3 2 CRQ 4 8 9 D S Q 13 11 C Q 12 R 7 10 14 +5V –5V 51k +5V 50 µF DS 4 *R 1 = 470kΩ FOR 2V RANGE R 1 = 27k Ω FOR 200mV RANGE **MYLAR CAPACITOR DS 3 DS 2 DS 1 –5V Figure 10. 3-1/2 Digit Voltmeter Common-Anode Displays, Flashing Overrange 3-132 TELCOM SEMICONDUCTOR, INC. 3-1/2 DIGIT A/D CONVERTERS TC14433 TC14433A 0.1 µF 470k 0.1 µF –V C 14024B R 1 +V 27k TC04 20k R 1/C 1C 1 DS 4 DS 3 VAG DS 2 DS 1 Q0 TC14433 Q1 Q2 VREF Q3 RC V DD V SS V EE EOC DU R C C0 2 +V –V 300k 14070B 1/4 +V C0 1 Vx R1 2 3 4 14013B D CR Q Q 1/4 14070B 1/2 DIGIT R 14013B D CR Q RQ PLUS SIGN –V 1/4 14070B MINUS SIGN BI D C B A Ph LD +V 14543B –V gfedcba BI D C B A Ph LD 14543B gfedcba +V +V –V BI D C B A Ph LD 14543B gfedcba +V –V +V 5 Figure 11. 3-1/2 Digit Voltmeter with LCD Display 6 ≈ 16,400 CLOCK CYCLES BETWEEN EOC PULSES EOC 1/2 CLOCK CYCLE DS 1 1/2 DIGIT (MSD) 2 CLOCK CYCLES 18 CLOCK CYCLES 7 DS2 DS3 DS 4 (LSD) Figure 12. Digit Select Timing Diagram 8 3-133 TELCOM SEMICONDUCTOR, INC. 3-1/2 DIGIT A/D CONVERTERS TC14433 TC14433A APPLICATIONS INFORMATION Figure 10 is an example of a 3-1/2 digit voltmeter using the TC14433 with common-anode displays. This system requires a 2.5V reference. Full-scale may be adjusted to 1.999V or 199.9 mV. Input overrange is indicated by flashing a display. This display uses LEDs with common anode digit lines. Power supply for this system is shown as a dual ±5V supply; however, the TC14433 will operate over a wide voltage range (see recommended operating conditions, page 2). The circuit in Figure 11 shows a 3-1/2 digit LCD voltmeter. The 14024B provides the low frequency square wave signal drive to the LCD backplane. Dual power supplies are shown here; however, one supply may be used when VSS is connected to VEE. In this case, VAG must be at least 2.8V above VEE. When only segments b and c of the decoder are connected to the 1/2 digit of the display, 4, 0, 7 and 3 appear as 1. The overrange indication (Q3 = 0 and Q0 = 1) occurs when the count is greater than 1999; e.g., 1.999V for a reference of 2V. The underrange indication, useful for autoranging circuits, occurs when the count is less than 180; e.g., 0.180V for a reference of 2V. Figure 14 is an example of a 3-1/2 digit LED voltmeter with a minimum of external components (only 11 additional components). In this circuit, the 14511B provides the segment drive and the 75492 or 1413 provides sink for digit current. Display is blanked during the overrange condition. TRUTH TABLE Coded Condition of MSD +0 –0 +0 UR –0 UR +1 –1 +1 OR –0 OR BCD to 7-Segment Q3 Q2 Q1 Q0 1 1 1 1 0 0 0 0 1 0 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Decoding Blank Blank Blank Blank Hook up only segments b and c to MSD 4–1 0–1 7–1 3–1 CAUTION If the most significant digit is connected to a display other than a "1" only, such as a full digit display, segments other than b and c must be disconnected. The BCD to 7-segment decoder must blank on BCD inputs 1010 to 1111. NOTES: Q3 — 1/2 digit, low for "1", high for "0" Q2 — Polarity: "1" = positive, "0" = negative Q0 — Out of range condition exists if Q0 = 1. When used in conjunction with Q3, the type of out of range condition is indicated; i.e., Q3 = 0 → OR or Q3 = 1 → UR. DS 1 DS 2 MULTIPLEXED BCD DS 1 DS 2 DS 3 DS 4 D0 D1 D2 D3 VDD POL 14042B C C D0 D1 D2 D3 14042B POL Q0 Q1 Q2 Q3 D0 D1 D2 D3 C VDD POL 14175B Q0 Q1 Q2 Q3 C VDD D0 D1 D2 D3 POL 14042B Q0 Q1 Q2 Q3 D0 D1 D2 D3 VDD POL 14175B Q0 Q1 Q2 Q3 C VDD C C D0 D1 D2 D3 14042B POL Q0 Q1 Q2 Q3 D0 D1 D2 D3 POL 14175B Q0 Q1 Q2 Q3 C VDD Q0 Q1 Q2 Q3 D0 D1 D2 D3 VDD R 14175B Q0 Q1 Q2 Q3 EOC Figure 13. Demultiplexing for TC14433 BCD Data 3-134 TELCOM SEMICONDUCTOR, INC. 3-1/2 DIGIT A/D CONVERTERS TC14433 TC14433A 470k 0.1µF 0.1µF 1 +5V V X 27kΩ TC04 INPUT 100kΩ R1 R1/C 1 C1 C01 C02 VX CLK1 V CLK0 AG DU OR Q0 EOC Q1 TC14433 VREF Q2 VSS VDD VEE DS 4 DS3 DS 2 DS 1 300k RESISTOR NETWORK OR INDIVIDUAL RESISTOR* A B1 a b B c C D I4511B d e LT f LE VSS VDDg RDP RM R 2 3 COMMON CATHODE LED DISPLAY +5V For VREF = 2000V V : 1.999V full scale For VREF = 200 mV V : 199.9 mV full scale (change 470k to R = 27k and decimal point position) Peak digit current for an eight displayed is 7 times the segment current. *To increase segment current capability add two 75491 ICs between 14511B and Resistor Network. The use of the 1413 as digit driver increases digit current capability over the 75492. **V can range between –2.8 and –11V. VEE** (MINUS) +5V MINUS CONTROL 75492 OR 1413* DIGIT DRIVERS 4 5 6 7 ALTERNATE OVERRANGE CIRCUIT WITH SEPARATED LED RR 1/6 75492 OR +5V OR 1/7 1413 Figure 14. 3-1/2 Digit Voltmeter with Low Component Count Using Common Cathode Displays 8 TELCOM SEMICONDUCTOR, INC. 3-135 3-1/2 DIGIT A/D CONVERTERS TC14433 TC14433A TYPICAL CHARACTERISTICS ROLLOVER ERROR (IN LSD) AT FULL-SCALE (PLUS COUNT LESS MINUS COUNT) I Q— QUIESCENT CURRENT (mA) 4 3 2 1 0 –1 –2 –3 –4 2 3 –3 –2 –1 0 1 (IV DD I–IV EE I) — SUPPLY VOLTAGE SKEW (V) 4 NOTE: ROLLOVER ERROR IS THE DIFFERENCE IN OUTPUT READING FOR THE SAME ANALOG INPUT SWITCHED FROM POSITIVE TO NEGATIVE. 4 3 VEE = –8V VDD = +8V 2 1 VEE = –5V VDD = +5V –40 –20 0 20 40 60 T A — TEMPERATURE (°C) 80 100 0 5 4 3 2 1 0 0 1 2 3 4 5 V DS — DRAIN TO SOURCE VOLTAGE (Vdc) –40°C +25°C +85°C ID — SINK CURRENT (mA) ID — SINK CURRENT (mA) –3 –40°C –2 –25°C –85°C –1 0 0 –1 –2 –3 –4 –5 V DS — DRAIN TO SOURCE VOLTAGE (Vdc) ICLK — CLOCK FREQUENCY (% CHANGE) ICLK — CLOCK FREQUENCY (Hz) 4 3 2 1 0 –1 –2 –3 –4 –40 ±5V SUPPLY 1M NOTE: ±5% TYPICAL VARIATION OVER SUPPLY VOLTAGES RANGE OF ±4.5V TO ±8V. ±8V SUPPLY 100k NORMALIZED AT 25°C 10k 10 k Ω 100 k Ω 1 MΩ R C — CLOCK FREQUENCY RESISTOR –20 0 20 40 60 T A — TEMPERATURE (°C) 80 CONVERSION RATE = CLOCK FREQUENCY ±1.5% 16,400 CLOCK FREQUENCY 80 MULTIPLEX RATE = 3-136 TELCOM SEMICONDUCTOR, INC.