TC7136CLW

1 TC7136 TC7136A LOW POWER, 3-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTERS FEATURES s s Fast Overrange Recovery, Guaranteed First Reading Accuracy Low Temperature Drift Internal Reference TC7136 ....................................... 70 ppm/°C Typ TC7136A ..................................... 35 ppm/°C Typ Guaranteed Zero Reading With Zero Input Low Noise .................................................... 15 µVP-P High Resolution .............................................. 0.05% Low Input Leakage Current ...................... 1 pA Typ 10 pA Max Precision Null Detectors With True Polarity at Zero High-Impedance Differential Input Convenient 9V Battery Operation With Low Power Dissipation ........................ 500 µW Typ 900 µW Max Thermometry Bridge Readouts: Strain Gauges, Load Cells, Null Detectors Digital Meters: Voltage/Current/Ohms/Power, pH Digital Scales, Process Monitors Portable Instrumentation GENERAL DESCRIPTION The TC7136 and TC7136A are low-power, 3-1/2 digit with liquid crystal display (LCD) drivers with analog-todigital converters. These devices incorporate an "integrator output zero" phase which guarantees overrange recovery. The performance of existing TC7126, TC7126A and ICL7126-based systems may be upgraded with minor changes to external, passive components. The TC7136A has an improved internal zener reference voltage circuit which maintains the analog common temperature drift to 35 ppm/°C (typical) and 75 ppm/°C (maximum). This represents an improvement of two to four times over similar 3-1/2 digit converters. The costly, spaceconsuming external reference source may be removed. The TC7136/A limits linearity error to less than 1 count on 200 mV or 2V full-scale ranges. Roll-over error — the difference in readings for equal magnitude but opposite polarity input signals — is below ±1 count. High-impedance differential inputs offer 1 pA leakage currents and a 1012Ω input impedance. The differential reference input allows ratiometric measurements for ohms or bridge transducer measurements. The 15 µVP-P noise performance guarantees a "rock solid" reading. The auto-zero cycle guarantees a zero display readout for a 0V input. TYPICAL OPERATING CIRCUIT 0.1 µF 34 C+ 31 33 – C REF 9–19 SEGMENT 22–25 DRIVE POL BP V+ 20 21 1 240 kΩ 36 10 k Ω + 9V MINUS SIGN BACKPLANE LCD 2 3 4 5 6 7 s s s s s s s TYPICAL APPLICATIONS s s s s s ORDERING INFORMATION PART CODE TC7136X X XXX A or blank* R (reversed pins) or blank (CPL pkg only) * "A" parts have an improved reference TC Package Code (see below): Package Code Package CKW CLW CPL 44-Pin PQFP 44-Pin PLCC 40-Pin PDIP 1 MΩ + ANALOG INPUT – 0.01 µF REF + V IN – 30 V IN 32 ANALOG COMMON 28 VBUFF Pin Layout Formed Leads — Normal Temperature Range 0°C to +70°C 0°C to +70°C 0°C to +70°C 180 kΩ 0.47 µF 29 TC7136 TC7136A + VREF – CAZ AVAILABLE PACKAGES 0.15 µF V REF 35 27 26 VINT V– OSC2 OSC3 OSC1 39 38 COSC 40 ROSC 50 pF 1 CONVERSION/SEC TO ANALOG COMMON (PIN 32) 40-Pin Plastic DIP 44-Pin Plastic Quad Flat Package Formed Leads 44-Pin Plastic Chip Carrier PLCC 560 kΩ 8 TC7136-6 10/18/96 TELCOM SEMICONDUCTOR, INC. 3-247 LOW POWER, 3-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTERS TC7136 TC7136A ABSOLUTE MAXIMUM RATINGS* Supply Voltage (V+ to V –)............................................ 15V Analog Input Voltage (Either Input) (Note 1) ........ V+ to V – Reference Input Voltage (Either Input) ................. V+ to V – Clock Input ...................................................... TEST to V+ Package Power Dissipation (TA ≤ 70°C) (Note 2) Plastic DIP ........................................................1.23W Plastic Quad Flat Package ...............................1.00W PLCC ................................................................1.23W Operating Temperature Range C Devices .............................................. 0°C to +70°C I Devices ............................................ –25°C to +85°C Storage Temperature Range ................. –65°C to +150°C Lead Temperature (Soldering, 10 sec) ................. +300°C *Static-sensitive device. Unused devices must be stored in conductive material. Protect devices from static discharge and static fields. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to Absolute Maximum Rating Conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS: VS = 9V, fCLK = 16 kHz, and TA = +25°C, unless otherwise noted. Symbol Input Zero Input Reading Zero Reading Drift Ratiometric Reading NL Nonlinearity Error VIN = 0V Full Scale = 200 mV VIN = 0V, 0°C ≤ TA ≤ +70°C VIN = VREF, VREF = 100 mV Full Scale = 200 mV or 2V Max Deviation From Best Straight Line –VIN = +VIN ≈ 200 mV VIN = 0V, Full Scale = 200 mV VIN = 0V VCM = ±1V, VIN = 0V, Full Scale = 200 mV VIN = 199 mV, 0°C ≤ TA ≤ +70°C Ext Ref Temp Coeff = 0 ppm/°C 250 kΩ Between Common and V + 0°C ≤ TA ≤ +70°C TC7136A "C" Commercial Temp TC7136 Range Devices TC7136A – 25°C ≤ TA ≤ +85°C "I" Industrial Temp TC7136 Range Devices 250 kW Between Common and V+ V + to V – = 9V V+ to V– = 9V VIN = 0V, V + to V – = 9V (Note 6) – 000.0 — 999 –1 ±000.0 0.2 999/1000 ±0.2 +000.0 1 1000 1 Digital Reading µV/°C Digital Reading Count Parameter Test Conditions Min Typ Max Unit eN IL CMRR Roll-Over Error Noise Input Leakage Current Common-Mode Rejection Ratio Scale Factor Temperature Coefficient — — — — –1 15 1 50 1 ±0.2 — 10 — 5 1 Count µVP-P pA µV/V ppm/°C Analog Common VCTC Analog Common Temperature Coefficient — — — — 2.7 4 4 — 35 70 35 70 3.05 5 5 70 75 150 100 150 3.35 6 6 100 ppm/°C ppm/°C ppm/°C ppm/°C V VP-P VP-P µA VC LCD Drive VSD VBD Analog Common Voltage LCD Segment Drive Voltage LCD Backplane Drive Voltage Power Supply IS Power Supply Current NOTES: 1. 2. 3. 4. Input voltages may exceed supply voltages when input current is limited to 100 µA. Dissipation rating assumes device is mounted with all leads soldered to PC board. Refer to "Differential Input" discussion. Backplane drive is in-phase with segment drive for "OFF" segment and 180° out-of-phase for "ON" segment. Frequency is 20 times conversion rate. Average DC component is less than 50 mV. 5. See "Typical Operating Circuit". 6. A 48 kHz oscillator increases current by 20 µA (typical). Common current not included. 3-248 TELCOM SEMICONDUCTOR, INC. LOW POWER, 3-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTERS TC7136 TC7136A PIN CONFIGURATIONS REF LO + C REF C– REF REF HI REF HI OSC 1 OSC 2 OSC 3 IN LO IN HI BUFF TEST COM 1 2 35 6 5 4 3 2 1 44 43 42 41 40 44 43 42 41 40 39 38 37 36 INT V– 34 NC V+ A1 B1 C1 D1 AZ F1 7 G1 8 E1 9 D2 10 39 REF LO 38 C REF NC 1 NC 2 TEST 3 OSC 3 4 33 NC 32 G + 2 – 37 C REF 36 COMMON 35 IN HI 31 C 3 30 A 3 29 G 3 3 4 5 C2 11 NC 5 OSC 2 6 OSC 1 7 NC 12 B2 13 A 2 14 F 2 15 E 2 16 TC7136CLW TC7136ACLW (PLCC) 34 NC 33 IN LO 32 AZ 31 BUFF 30 INT 29 V – V+ 8 D1 9 C 1 10 B 1 11 12 13 14 TC7136CKW TC7136ACKW (PQFP) 28 BP 27 POL 26 AB 4 25 E3 24 F3 23 B3 D 3 17 18 19 20 21 22 23 24 25 26 27 28 15 16 17 18 19 20 21 22 AB4 B3 F3 E3 G3 A3 C3 POL BP G2 NC D2 C2 B2 A2 A1 G1 V+ D1 C1 B1 1's A1 F1 G1 E1 D2 1 2 3 4 5 6 7 8 9 40 OSC 1 NORMAL PIN CONFIGURATION 39 OSC 2 38 OSC 3 37 TEST + 36 V REF 35 V – REF + 34 CREF – 33 CREF 32 ANALOG COMMON + 31 V IN 30 V – IN 29 CAZ 28 VBUFF 27 V INT 26 V – 25 G 2 24 C 3 23 A 3 22 G 3 OSC 1 OSC 2 OSC 3 1 2 3 40 V + REVERSE PIN CONFIGURATION 39 D1 38 C1 37 B1 36 A1 35 F1 C2 10 10's B2 11 A2 12 F2 13 E 2 14 D3 15 100's B3 16 F3 17 E 3 18 1000's AB 4 19 POL 20 (MINUS SIGN) TC7136CPL TC7136ACPL (PDIP) TEST 4 + V REF 5 – VREF 6 + CREF 7 – CREF 8 ANALOG 9 COMMON + V IN 10 V – 11 IN CAZ 12 VBUFF 13 V INT 14 V – 15 G 2 16 E1 E2 1's 34 G1 33 E 1 32 D2 31 C2 TC7136RCPL TC7136ARCPL (Reversed) PDIP 30 B2 29 A2 28 F2 10's D3 F1 F2 6 7 100's 1000's 27 E 2 26 D3 25 B3 24 F3 100's 100's C 3 17 A 3 18 G 3 19 23 E 3 22 AB4 21 POL (MINUS SIGN) 21 BP (BACKPLANE) BP 20 (BACKPLANE) NC = NO INTERNAL CONNECTION 8 3-249 TELCOM SEMICONDUCTOR, INC. LOW POWER, 3-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTERS TC7136 TC7136A TC7136/A PIN DESCRIPTION Pin No. 40-Pin PDIP Normal 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 (Reverse) (40) (39) (38) (37) (36) (35) (34) (33) (32) (31) (30) (29) (28) (27) (26) (25) (24) (23) (22) (21) (20) (19) (18) (17) (16) (15) (14) Name V+ D1 C1 B1 A1 F1 G1 E1 D2 C2 B2 A2 F2 E2 D3 B3 F3 E3 AB4 POL BP G3 A3 C3 G2 V– VINT Description Positive supply voltage. Activates the D section of the units display. Activates the C section of the units display. Activates the B section of the units display. Activates the A section of the units display. Activates the F section of the units display. Activates the G section of the units display. Activates the E section of the units display. Activates the D section of the tens display. Activates the C section of the tens display. Activates the B section of the tens display. Activates the A section of the tens display Activates the F section of the tens display. Activates the E section of the tens display. Activates the D section of the hundreds display. Activates the B section of the hundreds display. Activates the F section of the hundreds display. Activates the E section of the hundreds display. Activates both halves of the 1 in the thousands display. Activates the negative polarity display. Backplane drive output. Activates the G section of the hundreds display. Activates the A section of the hundreds display. Activates the C section of the hundreds display. Activates the G section of the tens display. Negative power supply voltage. The integrating capacitor should be selected to give the maximum voltage swing that ensures component tolerance build-up will not allow the integrator output to saturate. When analog common is used as a reference and the conversion rate is 3 readings per second, a 0.047 µF capacitor may be used. The capacitor must have a low dielectric constant to prevent roll-over errors. See Integrating Capacitor section for additional details. Integration resistor connection. Use a 180 kΩ for a 200 mV full-scale range and a 1.8 MΩ for 2V full-scale range. The size of the auto-zero capacitor influences the system noise. Use a 0.47 µF capacitor for a 200 mV full scale, and a 0.1 µF capacitor for a 2V full scale. See paragraph on Auto-Zero Capacitor for more details. The low input signal is connected to this pin. The high input signal is connected to this pin. This pin is primarily used to set the analog common-mode voltage for battery operation or in systems where the input signal is referenced to the power supply. See paragraph on Analog Common for more details. It also acts as a reference voltage source. 28 29 (13) (12) VBUFF CAZ 30 31 32 (11) (10) (9) – VIN + VIN ANALOG COMMON 3-250 TELCOM SEMICONDUCTOR, INC. LOW POWER, 3-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTERS TC7136 TC7136A TC7136/A PIN DESCRIPTION (Cont.) Pin No. 40-Pin PDIP Normal 33 34 1 2 (Reverse) (8) (7) Name C– REF C+ REF Description See pin 34. A 0.1 µF capacitor is used in most applications. If a large common-mode voltage exists (for example, the VIN– pin is not at analog common), and a 200 mV scale is used, a 1 µF capacitor is recommended and will hold the roll-over error to 0.5 count. See pin 36. The analog input required to generate a full-scale output (1999 counts). Place 100 mV between pins 35 and 36 for 199.9 mV full scale. Place 1V between pins 35 and 36 for 2V full scale. See paragraph on Reference Voltage. Lamp test. When pulled HIGH (to V+) all segments will be turned ON and the display should read –1888. It may also be used as a negative supply for externally-generated decimal points. See paragraph under Test for additional information. See pin 40. See pin 40. Pins 40, 39 and 38 make up the oscillator section. For a 48 kHz clock (3 readings per second) connect pin 40 to the junction of a 180 kΩ resistor and a 50 pF capacitor. The 180 kΩ resistor is tied to pin 39 and the 50 pF capacitor is tied to pin 38. CINT ANALOG INPUT SIGNAL INTEGRATOR – 35 (6) (5) V– REF V– REF 3 4 5 36 (4) TEST 37 38 39 (3) (2) (1) OSC3 OSC2 OSC1 The TC7136/A is a dual-slope, integrating analog-todigital converter. An understanding of the dual-slope conversion technique will aid in following detailed TC7136/A operational theory. The conventional dual-slope converter measurement cycle has two distinct phases: (1) Input signal integration (2) Reference voltage integration (deintegration) The input signal being converted is integrated for a fixed time period (tSI), measured by counting clock pulses. An opposite polarity constant reference voltage is then integrated until the integrator output voltage returns to zero. The reference integration time is directly proportional to the input signal (tRI). In a simple dual-slope converter, a complete conversion requires the integrator output to "ramp-up" and "rampdown." A simple mathematical equation relates the input signal, reference voltage, and integration time: 1 RC SWITCH DRIVER REF VOLTAGE PHASE CONTROL CONTROL LOGIC POLARITY CONTROL INTEGRATOR OUTPUT DISPLAY VIN VIN VARIABLE REFERENCE INTEGRATE TIME VFULL SCALE 1.2 VFULL SCALE FIXED SIGNAL INTEGRATE TIME Figure 1. Basic Dual-Slope Converter where: VR = Reference voltage tSI = Signal integration time (fixed) tRI = Reference voltage integration time (variable). For a constant VIN: VIN = VR ∫0 tSI VIN(t) dt = VR tRI , RC [] 3-251 tRI tSI . TELCOM SEMICONDUCTOR, INC. + – CLOCK GENERAL THEORY OF OPERATION (All Pin designations refer to 40-Pin Dip) Dual-Slope Conversion Principles COMPARATOR + 6 7 COUNTER 8 LOW POWER, 3-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTERS TC7136 TC7136A 30 NORMAL MODE REJECTION (dB) Auto-Zero Phase During the auto-zero phase, the differential input signal is disconnected from the circuit by opening internal analog gates. The internal nodes are shorted to analog common (ground) to establish a zero input condition. Additional analog gates close a feedback loop around the integrator and comparator. This loop permits comparator offset voltage error compensation. The voltage level established on CAZ compensates for device offset voltages. The auto-zero phase residual is typically 10 µV to 15 µV. The auto-zero duration is from 910 to 2900 counts for non-overrange conversions and from 300 to 910 counts for overrange conversions. 20 10 t = MEASUREMENT PERIOD 0 0.1/t 1/t INPUT FREQUENCY 10/t Figure 2. Normal-Mode Rejection of Dual-Slope Converter The dual-slope converter accuracy is unrelated to the integrating resistor and capacitor values, as long as they are stable during a measurement cycle. Noise immunity is an inherent benefit. Noise spikes are integrated, or averaged, to zero during integration periods. Integrating ADCs are immune to the large conversion errors that plague successive approximation converters in high-noise environments. Interfering signals with frequency components at multiples of the averaging period will be attenuated. Integrating ADCs commonly operate with the signal integration period set to a multiple of the 50 Hz/60 Hz power line period. Signal Integration Phase The auto-zero loop is entered and the internal differen+ tial inputs connect to VIN and V– . The differential input signal IN is integrated for a fixed time period. The TC7136/A signal integration period is 1000 clock periods or counts. The externally-set clock frequency is divided by four before clocking the internal counters. The integration time period is: tSI = 4 fOSC 1000, ANALOG SECTION In addition to the basic integrate and deintegrate dualslope cycles discussed above, the TC7136/A designs incorporate an "integrator output-zero cycle" and an "auto-zero cycle." These additional cycles ensure the integrator starts at 0V (even after a severe overrange conversion) and that all offset voltage errors (buffer amplifier, integrator and comparator) are removed from the conversion. A true digital zero reading is assured without any external adjustments. A complete conversion consists of four distinct phases: (1) (2) (3) (4) Integrator output-zero phase Auto-zero phase Signal integrate phase Reference deintegrate phase where fOSC = external clock frequency. The differential input voltage must be within the device common-mode range when the converter and measured system share the same power supply common (ground). If the converter and measured system do not share the same power supply common, V– should be tied to analog comIN mon. Polarity is determined at the end of signal integrate phase. The sign bit is a true polarity indication, in that signals less than 1 LSB are correctly determined. This allows precision null detection limited only by device noise and auto-zero residual offsets. Reference Integrate Phase – The third phase is reference integrate or deintegrate. VIN + is internally connected to analog common and VIN is connected across the previously-charged reference capacitor. Circuitry within the chip ensures that the capacitor will be connected with the correct polarity to cause the integrator output to return to zero. The time required for the output to return to zero is proportional to the input signal and is between 0 and 2000 internal clock periods. The digital reading displayed is: Integrator Output-Zero Phase This phase guarantees the integrator output is at 0V before the system-zero phase is entered. This ensures that true system offset voltages will be compensated for even after an overrange conversion. The count for this phase is a function of the number of counts required by the deintegrate phase. The count lasts from 11 to 140 counts for non-overrange conversions and from 31 to 640 counts for overrange conversions. 3-252 1000 VIN VREF TELCOM SEMICONDUCTOR, INC. TYPICAL SEGMENT OUTPUT + V 0.5 mA SEGMENT OUTPUT LCD 2 mA TC7136/A INTERNAL DIGITAL GROUND BP 21 RINT – C REF V BUFF V 28 1 INTEGRATOR 7 SEGMENT DECODE – + – ZI COMPARATOR THOUSANDS LOW POWER, 3-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTERS TELCOM SEMICONDUCTOR, INC. CAZ CINT VINT 29 27 7 SEGMENT DECODE 7 SEGMENT DECODE LCD SEGMENT DRIVERS + – VREF 35 33 + C REF + VREF CREF 34 36 ÷ 200 – + AZ HUNDREDS ZI & AZ + 10 µA ZI & AZ TO DIGITAL SECTION DATA LATCH + V IN 31 TENS UNITS INT – + V+– 2.8V CLOCK LOW TEMPCO VREF DE (–) TO SWITCH DRIVERS FROM COMPARATOR OUTPUT fOSC DE (+) Figure 3. TC7136A Block Diagram ÷4 26 – V 40 OSC 1 39 OSC 2 ROSC 38 OSC 3 COSC INTERNAL DIGITAL GOUND 1 6.2V CONTROL LOGIC 37 ANALOG COMMON 32 DE (+) DE (–) V+ – V IN AZ & DE (±) INT TEST VTH = 1V 500W 26 V– TC7136 TC7136A 3-253 1 7 2 6 5 4 3 8 LOW POWER, 3-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTERS TC7136 TC7136A System Timing 1000 INT 1–2000 11–140 ZI AZ 910–2900 4000 1000's 100's 10's 1's The oscillator frequency is divided by 4 prior to clocking the internal decade counters. The four-phase measurement cycle takes a total of 4000 counts, or 16,000 clock DISPLAY FONT DENT Figure 4. Conversion Timing During Normal Operation Figure 6. Display FONT and Segment Assignment INT 1000 DEINT 2001–2090 31–640 pulses. The 4000-count cycle is independent of input signal magnitude. Each phase of the measurement cycle has the following length: (1) Auto-zero phase: 3000 to 2900 counts (1200 to 11,600 clock pulses) (2) Signal integrate: 1000 counts (4000 clock pulses) This time period is fixed. The integration period is: ZI AZ 300–910 4000 Figure 5. Conversion Timing During Overrange Operation tSI = 4000 1 , fOSC DIGITAL SECTION The TC7136/A contains all the segment drivers necessary to directly drive a 3-1/2 digit LCD. An LCD backplane driver is included. The backplane frequency is the external clock frequency divided by 800. For three conversions per second the backplane frequency is 60 Hz with a 5V nominal amplitude. When a segment driver is in-phase with the backplane signal, the segment is OFF. An out-of-phase segment drive signal causes the segment to be ON, or visible. This AC drive configuration results in negligible DC voltage across each LCD segment, ensuring long LCD life. The polarity segment driver is ON for negative analog inputs. + – If VIN and VIN are reversed, this indicator would reverse. On the TC7136/A, when the TEST pin is pulled to V+, all segments are turned ON. The display reads –1888. During this mode the LCD segments have a constant DC voltage impressed. DO NOT LEAVE THE DISPLAY IN THIS MODE FOR MORE THAN SEVERAL MINUTES. LCDS MAY BE DESTROYED IF OPERATED WITH DC LEVELS FOR EXTENDED PERIODS. The display font and segment drive assignment are shown in Figure 6. 3-254 where fOSC is the externally-set clock frequency. (3) Reference integrate: 0 to 2000 counts (4) Zero integrator: 11 to 640 counts The TC7136 is a drop-in replacement for the TC7126 and ICL7126. The TC7136A offers a greatly-improved internal reference temperature coefficient. Minor component value changes are required to upgrade existing designs and improve the noise performance. COMPONENT VALUE SELECTION Auto-Zero Capacitor (CAZ) The CAZ capacitor size has some influence on system noise. A 0.47 µF capacitor is recommended for 200 mV fullscale applications where 1 LSB is 100 µV. A 0.1 µF capacitor is adequate for 2V full-scale applications. A Mylar-type dielectric capacitor is adequate. Reference Voltage Capacitor (CREF) The reference voltage, used to ramp the integrator TELCOM SEMICONDUCTOR, INC. LOW POWER, 3-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTERS TC7136 TC7136A output voltage back to zero during the reference integrate phase, is stored on CREF. A 0.1 µF capacitor is acceptable – when VREF is tied to analog common. If a large common– mode voltage exists (VREF ≠ analog common) and the application requires a 200 mV full scale, increase CREF to 1 µF. Roll-over error will be held to less than 0.5 count. A Mylar-type dielectric capacitor is adequate. 1 Oscillator Components COSC should be 50 pF. ROSC is selected from the equation: fOSC = 0.45 . RC Note that fOSC is 4 to generate the TC7136A's internal clock. The backplane drive signal is derived by dividing fOSC by 800. To achieve maximum rejection of 60Hz noise pickup, the signal integrate period should be a multiple of 60Hz. Oscillator frequencies of 240kHz, 120kHz, 80kHz, 60kHz, 40kHz, etc. should be selected. For 50 Hz rejection, oscillator frequencies of 200kHz, 100kHz, 66-2/3 kHz, 50kHz, 40kHz, etc. would be suitable. Note that 40kHz (2.5 readings per second) will reject both 50Hz and 60Hz. 2 3 4 5 6 7 Integrating Capacitor (CINT) CINT should be selected to maximize integrator output voltage swing without causing output saturation. Analog common will normally supply the differential voltage reference this case, a ±2V full-scale integrator output swing is satisfactory. For 3 readings per second (fOSC = 48 kHz) a 0.047 µF value is suggested. For one reading per second, 0.15 µF is recommended. If a different oscillator frequency is used, CINT must be changed in inverse proportion to maintain the nominal ±2V integrator swing. An exact expression for CINT is: (4000) CINT = where: fOSC VFS RINT VINT Reference Voltage Selection A full-scale reading (2000 counts) requires the input signal be twice the reference voltage. Required Full-Scale Voltage* 200 mV 2V *VFS = 2 VREF. ( )( ) 1 fOSC VFS RINT VINT , VREF 100 mV 1V = Clock frequency at pin 38 = Full-scale input voltage = Integrating resistor = Desired full-scale integrator output swing. CINT must have low dielectric absorption to minimize roll-over error. A polypropylene capacitor is recommended. Integrating Resistor (RINT) The input buffer amplifier and integrator are designed with Class A output stages. The output stage idling current is 6 µA. The integrator and buffer can supply 1 µA drive currents with negligible linearity errors. RINT is chosen to remain in the output stage linear drive region, but not so large that PC board leakage currents induce errors. For a 200 mV full scale, RINT is 180 kΩ. A 2V full scale requires 1.8 MΩ. Component Value In some applications, a scale factor other than unity may exist between a transducer output voltage and the required digital reading. Assume, for example, a pressure transducer output for 2000 lb/in.2 is 400 mV. Rather than dividing the input voltage by two, the reference voltage should be set to 200 mV. This permits the transducer input to be used directly. The differential reference can also be used when a digital zero reading is required when VIN is not equal to zero. This is common in temperature measuring instrumentation. A compensating offset voltage can be applied between – analog common and VIN The transducer output is connected + between V IN and analog common. DEVICE PIN FUNCTIONAL DESCRIPTION Differential Signal Inputs + – VIN (Pin 31), VIN (Pin 30) The TC7136/A is designed with true differential inputs and accepts input signals within the input stage commonmode voltage range (VCM). The typical range is V+ –1V to V– +1V. Common-mode voltages are removed from the system when the TC7136A operates from a battery or floating power – source (isolated from measured system), and VIN is connected to analog common (VCOM). (See Figure 7.) Nominal Full-Scale Voltage 200mV 2V 0.1 µF 1.8 MΩ 0.047 µF 0.47 µF 180 kΩ 0.047 µF CAZ RINT CINT NOTE:fOSC = 48 kHz (3 readings per sec). ROSC = 180kΩ, COSC = 50 8 TELCOM SEMICONDUCTOR, INC. 3-255 LOW POWER, 3-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTERS TC7136 TC7136A SEGMENT DRIVE LCD MEASURED SYSTEM V V V + V – + – GND VBUF V+ V – CAZ VINT POL BP OSC1 OSC3 OSC2 V– TC7136 TC7136A ANALOG – + + COMMON VREF VREF V GND POWER SOURCE + 9V Figure 7. Common-Mode Voltage Removed in Battery Operation With VIN = Analog Common In systems where common-mode voltages exist, the 86 dB common-mode rejection ratio minimizes error. Common-mode voltages do, however, affect the integrator output level. A worst-case condition exists if a large positive VCM exists in conjunction with a full-scale negative differential signal. The negative signal drives the integrator output positive along with VCM (see Figure 8.) For such applications, the integrator output swing can be reduced below the recommended 2V full-scale swing. The integrator output will swing within 0.3V of V+ or V– without increased linearity error. The TC7136/A offers a significantly improved analog common temperature coefficient. This potential provides a very stable voltage, suitable for use as a voltage reference. The temperature coefficient of analog common is typically 35 ppm/°C. ANALOG COMMON (Pin 32) The analog common pin is set at a voltage potential approximately 3V below V+. The potential is guaranteed to be between 2.7V and 3.35V below V+. Analog common is tied internally to an N-channel FET capable of sinking 100µA. This FET will hold the common line at 3V below V+ if an external load attempts to pull the common line toward V+. Analog common source current is limited to 1 µA. Analog common is therefore easily pulled to a more negative voltage (i.e., below V+ – 3V). – + The TC7136/A connects the internal VIN and VIN inputs to analog common during the auto-zero phase. During – the reference-integrate phase, VIN is connected to analog – common. If VIN is not externally connected to analog common, a common-mode voltage exists, but is rejected by the converter's 86 dB common-mode rejection ratio. In battery – operation, analog common and VIN are usually connected, removing common-mode voltage concerns. In systems where – VIN is connected to the power supply ground or to a given – voltage, analog common should be connected to VIN The analog common pin serves to set the analog section reference, or common point. The TC7136A is specifically designed to operate from a battery or in any measurement system where input signals are not referenced (float) with respect to the TC7136A power source. The analog common potential of V+ –3V gives a 7V end of battery life voltage. The common potential has a 0.001%/% voltage coefficient. With sufficiently high total supply voltage (V+–V– >7V), TELCOM SEMICONDUCTOR, INC. Differential Reference – VREF (Pin 36), VREF (Pin 35) The reference voltage can be generated anywhere within the V+ to V– power supply range. To prevent roll-over type errors being induced by large common-mode voltages, CREF should be large compared to stray node capacitance. + INPUT BUFFER + VIN – VCM + – CI RI – + VI INTEGRATOR TI VI = V CM – VIN RI CI Where: 4000 T I = Integration time = f OSC C I = Integration capacitor R I = Integration resistor [ [ Figure 8. Common-Mode Voltage Reduces Available Integrator Swing (VCOM ≠ VIN) 3-256 LOW POWER, 3-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTERS TC7136 TC7136A analog common is a very stable potential with excellent temperature stability (typically 35 ppm/°c). for TC7136A This potential can be used to generate the TC7136A's reference voltage. An external voltage reference will be unnecessary in most cases because of the 35 ppm/°C temperature coefficient. See TC7136A Internal Voltage Reference discussion. TEST (Pin 37) The TEST pin potential is 5V less than V+. TEST may be used as the negative power supply connection for external CMOS logic. The TEST pin is tied to the internally-generated negative logic supply through a 500Ω resistor. The TEST pin load should not be more than 1 mA. See the Applications Section for additional information on using TEST as a negative digital logic supply. If TEST is pulled high (to V+), all segments plus the minus sign will be activated. DO NOT OPERATE IN THIS MODE FOR MORE THAN SEVERAL MINUTES. With TEST = V+, the LCD segments are impressed with a DC voltage which will destroy the LCD. 9V + 1 2 1 V+ 240 kΩ 36 VREF 10 kΩ 26 V– TC7136 TC7136A + VREF 35 – VREF ANALOG 32 COMMON SET VREF = 1/2 VFULL SCALE Figure 10. TC7136A Internal Voltage Reference Connection 3 4 5 6 7 APPLICATIONS INFORMATION Liquid Crystal Display Sources Several manufacturers supply standard LCDs to interface with the TC7136A 3-1/2 digit analog-to-digital converter. Representative Part Numbers* C5335, H5535, T5135, SX440 FE 0201, 0501 FE 0203, 0701 FE 2201 I1048, I1126 TC7136A Internal Voltage Reference The TC7136 analog common voltage temperature stability has been significantly improved (Figure 9). The "A" version of the industry-standard TC7136 device allows users to upgrade old systems and design new systems without external voltage references. External R and C values do not need to be changed; however, noise performance will be improved by increasing CAZ. (See Auto-Zero Capacitor section.) Figure 10 shows analog common supplying the necessary voltage reference for the TC7136/A. 200 Manufacturer Crystaloid Electronics AND Address/Phone 5282 Hudson Dr. Hudson, OH 44236 216-655-2429 720 Palomar Ave. Sunnyvale, CA 94086 408-523-8200 1800 Vernon St. Ste. 2 Roseville, CA 95678 916-783-7878 612 E. Lake St. Lake Mills, WI 53551 414-648-2361 VGI, Inc. GUARANTEED MAXIMUM NO MAXIMUM SPECIFIED TYPICAL *NOTE: ANALOG COMMON TEMPERATURE COEFFICIENT (ppm/°C) 180 160 140 120 100 80 60 40 20 TC7136A 0 Figure 9. Analog Common Temperature Coefficient Hamlin, Inc. 3902, 3933, 3903 Contact LCD manufacturer for full product listing/specifications. GUARANTEED MAXIMUM TYPICAL Decimal Point and Annunciator Drive The TEST pin is connected to the internally-generated digital logic supply ground through a 500Ω resistor. The TEST pin may be used as the negative supply for external CMOS gate segment drivers. LCD annunciators for decimal points, low battery indication, or function indication may be added without adding an additional supply. No more than 1 mA should be supplied by the TEST pin: its potential is approximately 5V below V+. 3-257 TYPICAL TC7136 ICL7136 8 TELCOM SEMICONDUCTOR, INC. LOW POWER, 3-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTERS TC7136 TC7136A Ratiometric Resistance Measurements The TC7136A's true differential input and differential reference make ratiometric readings possible. In ratiometric operation, an unknown resistance is measured with respect to a known standard resistance. No accurately-defined reference voltage is needed. The unknown resistance is put in series with a known standard and a current passed through the pair. The voltage developed across the unknown is applied to the input and the voltage across the known resistor applied to the reference input. If the unknown equals the standard, the display will read 1000. The displayed reading can be determined from the following expression: Displayed reading = RUNKNOWN × 1000. RSTANDARD 160 kΩ 300 kΩ 300 kΩ R STANDARD + + VREF V V– REF + V IN R UNKNOWN – V IN ANALOG COMMON TC7136 TC7136A LCD Figure 12. Low Parts Count Ratiometric Resistance Measurement + 9V The display will overrange for RUNKNOWN ≥ 2 ×RSTANDARD. Simple Inverter for Fixed Decimal Point or Display Annunciator V+ V+ V+ – VIN + VIN + VREF – VREF V– 1N4148 SENSOR R2 50 kΩ R1 50 kΩ TC7136 TC7136A 4049 TC7136 TC7136A BP 21 TO LCD DECIMAL POINT GND TO LCD BLACK PLANE COMMON TEST 37 Figure 13. Temperature Sensor Multiple Decimal Point or Annunciator Driver 5.6 kΩ V+ V+ BP + 160 kΩ R1 20 kΩ V+ – VIN + VIN 9V V– 1N4148 TC7136 TC7136A DECIMAL POINT SELECT TO LCD DECIMAL POINTS TC7136 TC7136A 0.7%/°C PTC R3 R2 20 kΩ + VREF – VREF TEST 4030 GND COMMON Figure 11. Decimal Point and Annunciator Drives 3-258 Figure 14. Positive Temperature Coefficient Resistor Temperature Sensor TELCOM SEMICONDUCTOR, INC.