TSC51C2XXX12IBD

TSC8051C2 8-Bit Microcontroller for Digital Computer Monitors 1. Introduction In addition, the TSC8051C2 has 2 software selectable modes of reduced activity for further reduction in power consumption. In the idle mode the CPU is frozen while the RAM, the timers, the serial ports, and the interrupt The TSC8051C2 includes the fully static 8–bit “80C51” system continue to function. In the power down mode the CPU core with 256 bytes of RAM; 4 Kbytes of ROM; two RAM is saved and all other functions are inoperative. 16–bit timers; 12 PWM Channels; a 5 sources and 2–level The TSC8051C2 enables the users reducing a lot of interrupt controller; a full duplex serial port; a watchdog external discrete components while bringing the maximum of flexibility. timer; power voltage monitor and on–chip oscillator. The TSC8051C2 is a stand–alone high performance CMOS 8–bit embedded microcontroller and is designed for use in CRT monitors. It is also suitable for automotive and industrial applications. 2. Features D Boolean processor D Fully static design D 4K bytes of ROM D 256 bytes of RAM D 2 x 16–bit timer/counter D Programmable serial port D 5 interrupt sources: D External interrupts (2) D Timers interrupt (2) D Serial port interrupt D Watchdog reset D Power Fail reset D On chip oscillator for crystal or ceramic resonator D 2 power saving control modes: D Idle mode D Power–down mode D SYNC Processor D Controlled HSYNC & VSYNC outputs D Controlled HSYNC & VSYNC inputs D Clamp pulse output D Up to 12 programmable PWM channels with 8–bit resolution D Up to 32 programmable I/O lines depending on the package D 40 pins DIP, 44 pins PQFP, 44 and 52 pins PLCC packages D Commercial and industrial temperature ranges D Operating Frequency: 12 MHz to 16 MHz MATRA MHS Rev. A (10 Jan. 97) 1 Preview TSC8051C2 3. Block Diagram T1 3 INT1 VCC 3 VSS T0 INT0 3 3 CPO 1 XTAL1 XTAL2 EA ALE PSEN 3 WR 3 RD T0 TWO 16–BIT TIMER/EVENT COUNTER INT0 CPU PROGRAM MEMORY 4k x 8 ROM DATA MEMORY 256 x 8 RAM SPECIAL EXTERNAL INPUTS CLAMP PULSE 80C51 CORE EXCLUDING ROM/RAM 8–BIT INTERNAL BUS 0 AD0–7 2 A8–15 RST PARALLEL I/O PORTS AND EXTERNAL BUS SERIAL UART PORT WATCHDOG TIMER POWER VOLTAGE MONITOR 12 x 8–bit PWM CHANNELS CONTROLLED HSYNC & VSYNC OUTPUTS 3 P0 P1 P2 P3 TxD RxD 3 PWM0 – PWM7 1 PWM8 – PWM11 3 3 3 3 VSYNC HSYNC VOUT HOUT 0 ALTERNATE FUNCTION OF PORT0 1 ALTERNATE FUNCTION OF PORT1 2 ALTERNATE FUNCTION OF PORT2 3 ALTERNATE FUNCTION OF PORT3 Figure 1. TSC8051C2 block diagram. 2 MATRA MHS Rev. A (10 Jan. 97) Preview TSC8051C2 4. Pin Configurations P1.0/PWM8 P1.1/PWM9 P1.2/PWM10 P1.3/PWM11 P1.4/CPO P1.5 P1.6 P1.7 RST P3.0/RXD P3.1/TXD P3.2/INT0/VSYNC P3.3/INT1/VOUT P3.4/TO/HSYNC P3.5/T1/HOUT P3.6/WR P3.7/RD XTAL2 XTAL1 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA ALE PSEN PWM7 * PWM6 * PWM5 * PWM4 * PWM3 * PWM2 * PWM1 * PWM0 * INDEX CORNER P1.5 P1.6 P1.7 RST P3.0/RXD NC P3.1/TXD P3.2/INT0/VSYNC PWM7* PWM6* PWM5* 7 8 9 10 11 12 13 14 15 16 17 6 P1.3/PWM11 P1.2/PWM10 P1.1/PWM9 P1.0/PWM8 NC VCC P0.0 P0.1 P0.2 P0.3 5 4 3 2 1 44 43 42 41 40 39 38 37 36 35 PLCC 44 34 33 32 31 30 29 P0.4 P0.5 P0.6 P0.7 EA NC ALE PSEN PWM7* PWM6* PWM5* P0.5 P0.6 P0.7 EA ALE PSEN P2.7 PWM7 P2.6 PWM6 P2.5 PWM5 PWM4 DIL 40 P3.6/WR P3.7/RD XTAL2 XTAL1 VSS P1.2/PWM10 P1.1/PWM9 P1.0/PWM8 VCC P0.0 P0.1 P0.2 4 3 2 1 52 51 50 49 48 47 46 45 44 43 42 PLCC 52 41 40 39 38 37 36 35 34 P1.4/CPO 18 19 20 21 22 23 24 26 26 27 28 *PWMx or P2.x depending on option (see ordering information) P1.3/PWM11 NC P1.4/CPO 7 NC P1.5 P1.6 P1.7 RST P3.0/RXD P3.1/TXD P3.2/INT0/VSYNC P3.3/INT1/VOUT P3.4/T0/HSYNC P3.5/T1/HOUT NC P3.6/WR 8 9 10 11 12 13 14 15 16 17 18 19 20 6 5 21 22 23 24 25 26 27 28 29 30 31 32 33 P3.7/RD XTAL2 XTAL1 VSS PWM0 P2.1 NC INDEX CORNER PWM1 P2.2 PWM2 P2.3 Figure 2. TSC8051C2 pin configurations. PWM3 P2.4 P2.0 P0.3 P0.4 NC PWM0* PWM1* PWM2* PWM3* PWM4* MATRA MHS Rev. A (10 Jan. 97) 3 Preview TSC8051C2 5. Pin Description VSS Circuit ground. PORT 2 (P2.0–P2.7) Port 2 is an 8–bit bidirectional I/O port with internal pullups. Port 2 pins that have 1’s written to them are pulled high by the internal pullups, and in that state can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL on the data–sheet) because of the internal pullups. Port 2 emits the high–order 8–bit address during fetches from external Program Memory and during accesses to external Data Memory that use 16–bit addresses. In this application it uses strong internal pull–up when emitting 1’s. Port 2 can sink and source 3 LS TTL loads. VCC Power supply voltage. RST A high level on this pin for two machine cycles while the oscillator is running resets the device. An internal pulldown resistor permits power–on reset using only a capacitor connected to VCC. PORT 0 (P0.0–P0.7) Port 0 is an 8–bit open–drain bidirectional I/O port. Port 0 pins that have 1’s written to them float, and in that state can be used as high–impedance inputs. Port 0 is also the multiplexed low–order address and data bus during access to external Program and Data memory. In this application it uses strong internal pull–up when emitting 1’s. Port 0 can sink and source 8 LS TTL loads. PORT 3 (P3.0–P3.7) Port 3 is an 8–bit bidirectional I/O port with internal pullups. Port 3 pins that have 1’s written to them are pulled high by the internal pullups, and in that state can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL on the data–sheet) because of the internal pullups. Each line on this port has 2 or 3 functions either a general I/O or special control signal, as listed below: Port Pin P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 PORT 1 (P1.0–P1.7) Port 1 is an 8–bit bidirectional I/O port with internal pullups. Port 1 pins that have 1’s written to them are pulled high by the internal pullups, and in that state can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL on the data–sheet) because of the internal pullups. Port 1 also serves 4 programmable PWM open drain outputs and programmable open drain CPO, as listed below: Port Pin P1.0 P1.1 P1.2 P1.3 P1.4 Alternate Function RXD: serial input port. TXD: serial output port. INT0: external interrupt 0. VSYNC: vertical synchro input. INT1: external interrupt 1. VOUT: buffered V-SYNC output. T0: Timer 0 external input. HSYNC: horizontal synchro input. T1: Timer 1 external input. HOUT: buffered H–SYNC output. WR: external data memory write strobe. RD: external data memory read strobe. Alternate Function PWM8: Pulse Width Modulation output 8. PWM9: Pulse Width Modulation output 9. PWM10: Pulse Width Modulation output 10. PWM11: Pulse Width Modulation output 11. CPO: Clamp Pulse Output. Port 3 can sink and source 3 LS TTL loads. PWM0–7 These eight Pulse Width Modulation outputs are true open drain outputs and are floating after reset. Port 1 can sink and source 3 LS TTL loads. 4 MATRA MHS Rev. A (10 Jan. 97) Preview TSC8051C2 ALE The Address Latch Enable output signal occurs twice each machine cycle except during external data memory access. The negative edge of ALE strobes the address into external data memory or program memory. ALE can sink and source 8 LS TTL loads. If desired, ALE operation can be disabled by setting bit 0 of SFR location AFh (MSCON). With the bit set, ALE is active only during MOVX instruction and external fetches. Otherwise the pin is pulled low. PSEN The Program Store Enable output signal remains high during internal program memory. An active low output occurs during an external program memory fetch. PSEN can sink and source 8 LS TTL loads. XTAL1 Input to the inverting oscillator amplifier and input to the external clock generator circuits. EA When the External Access input is held high, the CPU executes out of internal program memory (unless the Program Counter exceeds 1FFFh). When EA is held low the CPU executes only out of external program memory. must not be left floating. XTAL2 Output from the inverting oscillator amplifier. This pin should be non–connected when external clock is used. MATRA MHS Rev. A (10 Jan. 97) 5 Preview TSC8051C2 6. Basic Functional Description 6.1. Idle And Power Down Operation Figure 3 shows the internal Idle and Power Down clock configuration. As illustrated, Power Down operation stops the oscillator. Idle mode operation allows the interrupt, serial port, and timer blocks to continue to operate while the clock to the CPU is gated off. These special modes are activated by software via the Special Function Register, its hardware address is 87h. PCON is not bit addressable. XTAL1 INTERRUPT SERIAL PORT TIMER BLOCKS CPU PD IDL XTAL2 OSC CLOCK GEN. Figure 3. Idle and Power Down Hardware. PCON: Power Control Register MSB SMOD – – PFRE SFR 87h GF1 GF0 PD LSB IDL Symbol IDL PD GF0 GF1 PFRE – – SMOD Position PCON.0 PCON.1 PCON.2 PCON.3 PCON.4 PCON.5 PCON.6 PCON.7 Name and Function Idle mode bit. Setting this bit activates idle mode operation. Power Down bit. Setting this bit activates power down operation. General–purpose flag bit. General–purpose flag bit. Power Fail Reset Enable bit. Setting this bit enables the power voltage monitor. The only way to clear this bit is to apply an external reset. (Reserved). (Reserved). Double Baud rate bit. Setting this bit causes the baud rate to double when the serial port is being used in either modes 1, 2 or 3. If 1’s are written to PD and IDL at the same time, PD takes precedence. The reset value of PCON is 0XX0 0000b. 6.1.1. Idle Mode The instruction that sets PCON.0 is the last instruction executed before the Idle mode is activated. Once in the Idle mode the CPU status is preserved in its entirety: the Stack Pointer, Program Counter, Program Status Word, Accumulator, RAM, and all other register maintain their data during Idle Table 1 describes the status of the external pins during Idle mode. There are two ways to terminate the Idle mode. Activation of any enabled interrupt will cause PCON.0 to be cleared by hardware terminating Idle mode. The interrupt is serviced, and following RETI, the next instruction to be executed will be the one following the instruction that wrote 1 to PCON.0. The flag bits GF0 and GF1 may be used to determine whether the interrupt was received during normal execution or during the Idle mode. For example, the instruction that writes to PCON.0 can also set or clear one or both flag bits. When Idle mode is terminated by an enabled interrupt, the service routine can examine the status of the flag bits. The second way of hardware reset. Since hardware reset needs cycles (24 oscillator operation. terminating the Idle is with a the oscillator is still running, the to be active for only 2 machine periods) to complete the reset 6 MATRA MHS Rev. A (10 Jan. 97) Preview TSC8051C2 6.1.2. Power Down Mode The instruction that sets PCON.1 is the last executed prior to entering power down. Once in power down, the oscillator is stopped. The contents of the onchip RAM and the Special Function Register are saved during power down mode. A hardware reset is the only way of exiting the power down mode. The hardware reset initiates the Special Function Register. In the Power Down mode, VCC may be lowered to minimize circuit power consumption. Care must be taken to ensure the voltage is not reduced until the power down mode is entered, and that the voltage is restored before the hardware reset is applied which frees the oscillator. Reset should not be released until the oscillator has restarted and stabilized. Table 1 describes the status of the external pins while in the power down mode. It should be noted that if the power down mode is activated while in external program memory, the port data that is held in the Special Function Register P2 is restored to Port 2. If the data is a 1, the port pin is held high during the power down mode by the strong pullup transistor. Table 1. Status of the external pins during Idle and Power Down modes. Mode Idle Idle Power Down Power Down Program Memory Internal External Internal External ALE 1 1 0 0 PSEN 1 1 0 0 Port 0 Port Data Floating Port Data Floating Port 1 Port Data Port Data Port Data Port Data Port 2 Port Data Address Port Data Port Data Port 3 Port Data Port Data Port Data Port Data PWMx Floating Floating Floating Floating 6.2. Stop Clock Mode Due to static design, the TSC8051C2 clock speed can be reduced down to 0 MHz without any data loss in memory or register. This mode allows step by step code execution, and permits to reduce system power consumption by bringing the clock frequency down to any value. When the clock is stopped, the power consumption is the same as in the Power Down Mode. 6.4. I/O Configurations Figure 4. shows a functional diagram of the generic bit latch and I/O buffer in each of the four ports. The bit latch, (one bit in the port SFR) is represented as a D type flip–flop. A ‘write to latch’ signal from the CPU latches a bit from the internal bus and a ‘read latch’ signal from the CPU places the Q output of the flip–flop on the internal bus. A ‘read pin’ signal from the CPU places the actual pin logical level on the internal bus. Some instructions that read a port read the actual pin, and other instructions read the latch (SFR). 6.3. I/O Ports Structure The TSC8051C2 has four 8–bit ports. Each port consist of a latch (special function register P0 to P3), an input buffer and an output driver. These ports are the same as in 80C51, with the exception of the additional functions of port 1 and port 3 (see Pin Description section). MATRA MHS Rev. A (10 Jan. 97) 7 Preview TSC8051C2 READ LATCH ADDR/DATA CONTROL VCC READ LATCH P0.X PIN D Q P0.X LATCH Q LE PWMX CONTROL VCC INTERNAL PULL–UP* P1.X PIN D Q P1.X LATCH LE Q INT. BUS WRITE TO LATCH INT. BUS WRITE TO LATCH MUX MUX READ PIN PORT 0 BIT READ PIN PORT 1 BIT * Internal pull–up not present on P1.0 to P1.4 when PWM8 to PWM11 and CPO are enabled ADDR CONTROL VCC INTERNAL PULL–UP P2.X PIN D Q P2.X LATCH LE Q READ LATCH ALTERNATE OUTPUT FUNCTION VCC INTERNAL PULL–UP P3.X PIN D Q P3.X LATCH LE Q READ LATCH INT. BUS WRITE TO LATCH INT. BUS WRITE TO LATCH MUX READ PIN PORT 2 BIT READ PIN ALTERNATE INPUT FUNCTION PORT 3 BIT Figure 4. Port Bit Latches and I/O buffers 6.5. Reset Circuitry The reset circuitry for the TSC8051C2 is connected to the reset pin RST. A Schmitt trigger is used at the input for noise rejection (see Figure 5. ). A reset is accomplished by holding the RST pin high for at least two machine cycles (24 oscillator periods) while the oscillator is running. The CPU responds by executing an internal reset. It also configures the ALE and PSEN pins as inputs (they are quasi–bidirectional). A Watchdog timer underflow or a power Fail condition if enabled, will force a reset condition to the TSC8051C2 by an internal connection. The internal reset is executed during the second cycle in which reset is high and is repeated every cycle until RST goes low. It leaves the internal registers as follows: Register ACC B DPTR EICON HWDR IE IP MSCON MXCR0–1 P0–P3 PC PCON PSW PWM0–11 PWMCON SBUF Content 00h 00h 0000h 00h 00h 0XX0 0000b XXX0 0000b XXXX XXX0b 00h FFh 0000h 0XX0 0000b 00h 00h XXXX XXX0b 00h 8 MATRA MHS Rev. A (10 Jan. 97) Preview TSC8051C2 Register SCON SOCR SP TCON TH0, TH1 TL0, TL1 TMOD Content 00h 00h 07h 00h 00h 00h 00h 6.6. Oscillator Characteristics XTAL1 and XTAL2 are respectively the input and output of an inverting amplifier which is configured for use as an on–chip oscillator. As shown in Figure 7. , either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL1 should be driven while XTAL2 is left unconnected as shown in Figure 8. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide–by–two flip–flop. The minimum high and low times specified on the data sheet must be observed however. XTAL2 The internal RAM is not affected by reset. At power–on reset, the RAM content is indeterminate. RST On–chip resistor R RST Schmitt Trigger Reset Circuitry XTAL1 VSS Watchdog Reset Power Fail Reset Figure 7. Crystal Oscillator NC EXTERNAL OSCILLATOR SIGNAL XTAL2 XTAL1 VSS Figure 5. On–Chip Reset Configuration. An automatic reset can be obtained when VCC is turned on by connecting the RST pin to VCC through a 1µF capacitor providing the VCC setting time does not exceed 1ms and the oscillator start–up time does not exceed 10ms. This power–on reset circuit is shown in Figure 6. When power comes on, the current drawn by RST starts to charge the capacitor. The voltage at RST is the difference between VCC and the capacitor voltage, and decreases from VCC as the capacitor charges. VRST must remain above the lower threshold of the Schmitt trigger long enough to effect a complete reset. The time required is the oscillator start–up time, plus 2 machine cycles. VCC 1mF + RST VRST VSS R RST VCC TSC8051C2 Figure 8. External Drive Configuration 6.7. Memory organization The memory organisation of the TSC8051C2 is the same as in the 80C51, with the exception that the TSC8051C2 has 4k bytes ROM, 256 bytes RAM, and additional SFRs. Details of the differences are given in the following paragraphs. In the TSC8051C2, the lowest 4k of the 64k program memory address space is filled by internal ROM. Depending on the package used, external access is available or not. By tying the EA pin high, the processor fetches instructions from internal program ROM. Bus expansion for accessing program memory from 4k upward is automatic since external instruction fetches occur automatically when the program counter exceeds 1FFFh. If the EA pin is tied low, all program memory fetches are from external memory. The execution speed is the same regardless of whether fetches are from external or internal program memory. If all storage is on–chip, then byte location 0FFFh should be left vacant to prevent an undesired pre–fetch from external program memory address 1000h. Figure 6. Power–on Reset Circuit MATRA MHS Rev. A (10 Jan. 97) 9 Preview TSC8051C2 Certain locations in program memory are reserved for specific purposes. Locations 0000h to 0002h are reserved for the initialisation program. Following reset, the CPU always begins execution at location 0000h. Locations 0003h to 002Ah are reserved for the five interrupt request service routines. The internal data memory space is divided into a 256–bytes internal RAM address space and a 128 bytes special function register address space. The internal data RAM address space is 0 to FFh. Four 8–bit register banks occupy locations 0 to 1Fh. 128 bit locations of the internal data RAM are accessible through direct addressing. These bits reside in 16 bytes of internal RAM at location 20h to 2Fh. The stack can be located anywhere in the internal data RAM address space by loading the 8–bit stack pointer (SP SFR). Table 2. Mapping of Special Function Register 0/8 F8 F0 E8 E0 D8 D0 C8 C0 B8 B0 A8 A0 98 90 88 80 IP P3 IE P2 SCON P1 TCON P0 TMOD SP TL0 DPL TL1 DPH TH0 TH1 PCON SBUF MSCON PSW ACC B The SFR address space is 100h to 1FFh. All registers except the program counter and the four 8–bit register banks reside in this address space. Memory mapping of the SFRs allows them to be accessed as easily as internal RAM, and as such, they can be operated on by most instructions.The mapping in the SFR address space of the 40 SFRs is shown in Table 2. The SFR names in italic are TSC8051C2 new SFRs and are described in Peripherals Functional Description section. The SFR names in bold are bit addressable. 1/9 2/A 3/B 4/C PWM8 PWM4 PWM0 EICON 5/D PWM9 PWM5 PWM1 SOCR 6/E PWM10 PWM6 PWM2 HWDR 7/F PWM11 PWM7 PWM3 MXCR0 PWMCON MXCR1 6.8. Interrupts The TSC8051C2 has five interrupt sources, each of which can be assigned one of two priority levels. These five interrupt sources are common to the 80C51 and are the external interrupts (INT0 and INT1), the timer 0 and timer 1 interrupts (IT0 and IT1), and the serial I/O interrupt (RI or TI). 10 MATRA MHS Rev. A (10 Jan. 97) Preview TSC8051C2 6.8.1. Interrupt Enable Register: Each interrupt source can be individually enabled or disabled by setting or clearing a bit in the interrupt enable register (IE SFR). All interrupts sources can also be globally enabled or disabled by setting or clearing the EA bit in IE register. IE: Interrupt Enable Register MSB EA – – ES SFR A8h ET1 EX1 ET0 LSB EX0 Symbol EX0 ET0 EX1 ET1 ES – – EA Position IE.0 Enable external interrupt 0. Enable timer 0 interrupt. Enable external interrupt 1. Enable timer 1 interrupt. Enable UART interrupt. (Reserved). (Reserved). Enable all interrupts. Name and Function IE.1 IE.2 IE.3 IE.4 IE.5 IE.6 IE.7 6.8.2. Interrupt Priority Structure: Each interrupt source can be assigned one of two priority levels. Interrupt priority levels are defined by the interrupt priority register (IP SFR). Setting a bit in the interrupt priority register selects a high priority interrupt, clearing it selects a low priority interrupt. IP: Interrupt Priority Register MSB – – – PS SFR B8h PT1 PX1 PT0 LSB PX0 Symbol PX0 PT0 PX1 PT1 PS – – – Position IP.0 IP.1 IP.2 IP.3 IP.4 IP.5 IP.6 IP.7 Name and Function External interrupt 0 priority level. Timer 0 interrupt priority level. External interrupt 1 priority level. Timer 1 interrupt priority level. UART interrupt priority level. (Reserved). (Reserved). (Unused). MATRA MHS Rev. A (10 Jan. 97) 11 Preview TSC8051C2 A low priority interrupt service routine may be interrupted by a high priority interrupt. A high priority interrupt service routine cannot be interrupted by any other interrupt source. If two requests of different priority levels occur simultaneously, the high priority level request is serviced. If requests of same priority are received simultaneously, an internal polling sequence determines which request is serviced. Thus, within each priority level, there is a second priority structure determined by the polling sequence, as follows: Priority Within Level (highest) ↑ Order 1 2 3 4 5 Source INT0 Timer 0 INT1 Timer 1 UART ↓ (lowest) 6.8.3. Interrupt Handling: The interrupt flags are sampled at S5P2 of every machine cycle. The samples are polled during the following machine cycle. If one of the flags was in a set condition at S5P2 of the previous machine cycle, the polling cycle will find it and the interrupt system will generate a LCALL to the appropriate service routine, provided this hardware–generated LCALL is not blocked by any of the following conditions: 1. An interrupt of higher or equal priority is already in progress. 2. The current (polling) cycle is not the final cycle in the execution of the instruction in progress. 3. The instruction in progress is RETI or any access to the IE or IP SFR. Any of these three conditions will block the generation of the LCALL to the interrupt service routine. Note that if an interrupt is active but not being responded to for one of the above conditions, if the flag is not still active when the blocking condition is removed, the denied interrupt will not be serviced. In other words, the facts that the interrupt flag was once active but not serviced is not memorized. Every polling cycle is new. The processor acknowledges an interrupt request by executing a hardware–generated LCALL to the appropriate service routine. In some cases it also clears the flag that generated the interrupt, and in other case it does not. It clears the timer 0, timer 1, and external interrupt flags. An external interrupt flag (IE0 or IE1) is cleared only if it was transition–activated. All other interrupt flags are not cleared by hardware and must be cleared by the software. The LCALL pushes the contents of the program counter onto the stack (but it does not save the PSW) and reloads the PC with an address that depends on the source of the interrupt being vectored to, as listed below: Source IE0 TF0 IE1 TF1 RI + TI Vector Address 0003h 000Bh 0013h 001Bh 0023h Execution proceeds from the vector address until the RETI instruction is encountered. The RETI instruction clears the ‘priority level active’ flip–flop that was set when this interrupt was acknowledged. It then pops two bytes from the the top of the stack and reloads the program counter with them. Execution of the interrupted program continues from where it was interrupted. 12 MATRA MHS Rev. A (10 Jan. 97) Preview TSC8051C2 7. Peripherals Functional Description For detailed functionnal description of standard 80C51 peripherals, please refer to C51 Family, Hardware Description and Programmer’s Guides. The 4–bit timer is decremented every ‘t’ seconds, where: t = 12 x 131072 x 1/fosc. (131.072ms at fosc = 12MHz). Thus, the interval may vary from 131.072ms to 2097.152ms in 16 possible steps (see Table 3. ). The watchdog timer has to be reloaded (write to HWDR SFR) within periods that are shorter than the programmed watchdog interval, otherwise the watchdog timer will underflow and a system reset will be generated which will reset the TSC8051C2. 7.1. Watchdog Timer The watchdog timer consists of a 4–bit timer with a 17–bit prescaler as shown in Figure 9. The prescaler is fed with a signal whose frequency is 1/12 the oscillator frequency (1MHz with a 12MHz oscillator). HWDR: Hardware WatchDog Register MSB WTE – – – SFR E6h WT3 WT2 WT1 LSB WT0 Symbol WT0 WT1 WT2 WT3 – – – WTE Position HWDR.0 HWDR.1 HWDR.2 HWDR.3 HWDR.4 HWDR.5 HWDR.6 HWDR.7 Watchdog Timer Interval bit 0. Watchdog Timer Interval bit 1. Watchdog Timer Interval bit 2. Watchdog Timer Interval bit 3. Name and Function Reserved for test purpose, must remain to 0 for normal operation. (Reserved). (Reserved). Watchdog Timer Enable bit. Setting this bit activates watchdog operation. Table 3. Watchdog timer interval value format. WT3 0 0 0 : : 1 WT2 0 0 0 : : 1 WT1 0 0 1 : : 1 WT0 0 1 0 : : 1 Interval t x 16 tx1 tx2 : : t x 15 Once the watchdog timer enabled setting WTE bit, it cannot be disabled anymore, except by a system reset. The watchdog timer is frozen during idle or power down mode. HWDR is a write only register. Its value after reset is 00h which disables the watchdog operation. HWDR is using TSC8051C2 Special Function Register address, E6h. MATRA MHS Rev. A (10 Jan. 97) 13 Preview TSC8051C2 fosc/12 Prescaler (17–bit) Clear Q Set WTE Write HWDR Internal bus Timer (4–bit) Underflow Internal reset Load The PFR must be enabled by setting PFRE bit in PCON register bit location 4 (see Idle and Power Donwn Operation section). The PFR is disable during Idle and power down modes. Since it is enabled, PFR can no longer be disabled by software. Writing 0 to PFRE bit has no effect, the only way to clear the PFRE bit is to apply an external reset. To avoid period during which PFR is disabled, internal reset sources do not disable PFR. VCC Figure 9. Watchdog timer block diagram 7.2. Power Fail Reset The TSC8051C2 implements a programmable power fail reset mechanism that avoids the microcontroller running while VCC is under working voltage (see Figure 10. ). This system generates an internal reset when VCC falls: during VCC failure or power supply switch off. When VCC falls below VLOW (see DC Electricals Characteristics), reset is asserted and maintained until power supply is completely off. If VCC rises above VLOW, reset is maintained during at least 2 machine cycles to be well detected by the CPU core. To avoid spurious reset, power glitches of pulses width less than 2 to 3 fOSC periods are filtered out (see Figure 11. ). Vcc (V) 5 VLOW + – VLOW Digital Filter Internal reset f OSC PFRE Figure 10. Power–Fail Reset block diagram 0 Internal RST Less than 2 to 3 TOSC 2 to 3 TOSC t More than 2 to 3 TOSC 2 to 3 TOSC > 2 machine cycles t Figure 11. Power Fail Reset timing diagram 7.3. Pulse Width Modulated Outputs The TSC8051C2 contains twelve pulse width modulated output channels (see Figure 10. ). These channels generate pulses of programmable duty cycle with an 8–bit resolution. 14 MATRA MHS Rev. A (10 Jan. 97) Preview TSC8051C2 The 8–bit counter counts modulo 256 by default i.e., from 0 to 255 inclusive but can count modulo 254 i.e., from 0 to 253 inclusive by programming the bit 0 of the PWMCON register. The counter clock is supplied by the oscillator frequency. Thus, the repetition frequency fpwm is constant and equals to the oscillator frequency divided by 256 or 254 (fpwm=46.875KHz or 47.244KHz with a 12MHz oscillator). The 8–bit counter is common to all PWM channels, its value is compared to the contents of the twelve registers: PWM0 to PWM11. Provided the content of each of these registers is greater than the counter value, the corresponding output is set low. If the contents of these registers are equal to, or less than the counter value the output will be high. PWMx: Pulse Width Modulator x Register MSB D7 D6 D5 D4 D3 D2 D1 The pulse–width ratio is therefore defined by the contents of these registers, and is in the range of 0 (all ‘0’ written to PWM register) to 255/256 or 1 (all ‘1’ written to PWM register) and may be programmed in increments of 1/256 or 1/254. When the 8–bit counter counts modulo 254, it can never reach the value of the PWM registers when they are loaded with FEh or FFh. LSB D0 When a compare register (PWM0 to PWM11) is loaded with a new value, the associated output is updated immediately. It does not have to wait until the end of the current counter period. All the PWM outputs are open–drain outputs with standard current drive and standard maximum voltage capability. When they are disabled, eight of them (PWM0 to PWM7) are in high impedance while the other four (PWM8 to PWM11) are standard Port outputs with internal pullups. PWM0 to PWM11 are write only registers. Their value after reset is 00h. PWM0 to PWM11 are using TSC8051C2 Special Function Registers addresses as detailed in Table 4. Table 4. PWM SFR register addresses Channel PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 PWM8 PWM9 PWM10 PWM11 Two 8–bit control registers: MXCR0 and MXCR1 are used to enable or disable PWM outputs. MXCR0 is used for PWM0 to PWM7. MXCR1 is used for PWM8 to PWM11, these PWMs are multiplexed with PORT 1 (see Table 5. ) SFR address ECh EDh EEh EFh F4h F5h F6h F7h FCh FDh FEh FFh MATRA MHS Rev. A (10 Jan. 97) 15 Preview TSC8051C2 MXCR0: PWM Multiplexed Control Register 0 MSB PE7 PE6 PE5 PE4 SFR E7h PE3 PE2 PE1 LSB PE0 Symbol PEx Position MXCR0.x Name and Function PWMX Enable bit. Setting this bit enables PWMx output. Clearing this bit disables PWMx output. MXCR1: PWM Multiplexed Control Register 1 MSB – – – – SFR D7h PE11 PE10 PE9 LSB PE8 Symbol PEx Position MXCR1.x Name and Function PWMX+8 Enable bit. Setting this bit enables PWMx output. Clearing this bit disables PWMx output and activates the I/O pin (see Table 5). MXCR0 and MXCR1 are read/write registers. Their value after reset is 00h which corresponds to all PWM disabled. PWM will not operate in idle and power down modes (frozen counter). When idle or power down mode is entered, the PWM0 to PWM7 output pins are floating and PWM8 to PWM11 pins are set to general purpose P1 port with the value of P1 SFR. MXCR0 and MXCR1 are using TSC8051C2 Special Function Register addresses, E7h and D7h respectively. PWMCON: PWM Control Register MSB – – – – Table 5. PWM alternate pin. Channel PWM8 PWM9 PWM10 PWM11 Pin assignment P1.0 P1.1 P1.2 P1.3 PWMCON is used to control the PWM counter. SFR DFh – – – LSB CMOD Symbol CMOD Position PWMCON.0 Name and Function Counter modulo. Setting this bit sets the modulo to 254. Clearing this bit sets the modulo to 256. PWMCON is a write only register. Its value after reset is 00h which sets the PWM counter modulo to 256. PWMCON is using TSC8051C2 Special Function Register address, DFh. 16 MATRA MHS Rev. A (10 Jan. 97) Preview TSC8051C2 Internal bus PWMX register PEX bit ABh PWMX 100h Figure 13. shows a PWM programming example with PWM register content 55h and counter modulo 256. 55h 8–bit comparator X Output buffer X fosc 8–bit counter CMOD bit Figure 13. PWM programming example. Note: when packaging P2.X is selected, PWM0 to PWM7 are not available. Please refer to ordering information. Figure 12. Pulse width modulated outputs block diagram 7.4. SYNC Processor 7.4.1. HSYNC and VSYNC Outputs SOCR is used to configure P3.3 and P3.5 pins as buffered HSYNC and VSYNC outputs or as general purpose I/Os. When either HSYNC or VSYNC is selected, the output level can be respectively programmed as P3.4 or P3.2 input level (inverted or not), or as a low level if not enabled. Figure 14. shows the programmable HSYNC and VSYNC output block diagram. SOCR: Synchronisation Output Control Register. MSB – – VOS HOS SFR E5h VOP VOE HOP LSB HOE Symbol HOE HOP VOE VOP HOS VOS CPE CPP Position SOCR.0 SOCR.1 SOCR.2 SOCR.3 SOCR.4 SOCR.5 SOCR.6 SOCR.7 Name and Function HSYNC Output Enable bit. Setting this bit enables the HSYNC signal. HSYNC Output Polarity bit. Setting this bit inverts the HSYNC output. VSYNC Output Enable bit. Setting this bit enables the VSYNC signal. VSYNC Output Polarity bit. Setting this bit inverts the VSYNC output. HSYNC Output Selection bit. Setting this bit selects the VSYNC output, clearing it selects P3.5 SFR bit. VSYNC Output Selection bit. Setting this bit selects the VSYNC output, clearing it selects P3.3 SFR bit. Clamp Pulse Enable bit. Setting this bit enables the CPO output. Clamp Pulse Polarity bit. Setting this bit selects positive clamp pulses, clearing it selects negative clamp pulses. SOCR is a write only register. Its value after reset is 00h which enables P3.3 and P3.5 general purpose I/O pins. SOCR is using TSC8051C2 Special Function Register address, E5h. MATRA MHS Rev. A (10 Jan. 97) 17 Preview TSC8051C2 8051 CORE P3.5 P3.4/T0/HSYNC PIN MUX P3.5/HOUT PIN HOP HOE HOS 8051 CORE P3.3 P3.2/INT0/HSYNC PIN MUX P3.3/VOUT PIN VOP VOE VOS Figure 14. Buffered HSYNC and VSYNC block diagram EICON: External Input Control Register MSB – – – – 7.4.2. HSYNC and VSYNC Inputs EICON is used to control INT0VSYNC input. Thus, an interrupt on either falling or rising edge and on either high or low level can be requested. Figure 15. shows the programmable INT0/VSYNC input block diagram. EICON is also used to control T0/HSYNC input as short pulses input capture to be able to count them with timer 0. Pulse duration shorter than 1 clock period is rejected; depending on the position of the sampling point in the pulse, pulse duration longer than 1 clock period and shorter than 1.5 clock period may be rejected or accepted; and pulse duration longer than 1.5 clock period is accepted. Moreover selection of negative or positive pulses can be programmed. Accepted pulse is lengthened up to 1 cycle period to be sampled by the 8051 core (one time per machine cycle: 12 clock periods), this implies that the maximum pulse frequency is unchanged and equal to fOSC/24. Figure 16. shows the programmable T0/HSYNC input block diagram. The Digital Timer Delay samples T0/HSYNC pulses and rejects or lengthens them. SFR E4h – T0L T0S LSB I0L Symbol I0L T0S T0L Position EICON.0 EICON.1 EICON.2 Name and Function INT0/VSYNC input Level bit. Setting this bit inverts INT0/VSYNC input signal. Clearing it allows standard use of INT0/VSYNC input. T0/HSYNC input Selection bit. Setting this bit allows short pulse capture. Clearing it allows standard use of T0/HSYNC input. T0/HSYNC input Level bit. Setting this bit allows positive pulse capture. Clearing it allows negative pulse capture. EICON is a write only register. Its value after reset is 00h which allows standard INT0 and T0 inputs feature. EICON is using TSC8051C2 Special Function Register address, E4h. MUX P3.4/T0/HSYNC PIN T0L Digital Time Delay T0S fOSC T0 MUX INT0 P3.2/INT0/VSYNC PIN I0L Figure 16. T0/HSYNC input block diagram Figure 15. INT0/VSYNC input block diagram 18 MATRA MHS Rev. A (10 Jan. 97) Preview TSC8051C2 7.4.3. Clamp Pulse Output The TSC8051C2 provides fully programmable clamp pulse output to pre–amplifier IC. User can program a pulse with positive or negative polarity at either the falling or rising edge of the HSYNC signal depending on its polarity. Figure 17. shows the CPO block diagram. CPE bit in SOCR is used to configure P1.4 pin as general purpose I/O or as open drain clamp pulse output, so enables the CPO. CPP bit in SOCR is used to select the clamp pulse signal polarity. Depending on the HSYNC polarity selected by the T0L bit, Clamp pulse is generated on the falling edge (negative polarity) or on the rising edge (positive polarity) as shown in Figure 18. The clamp pulse duration depends on the oscillator frequency by the following formula: 7.5 " 1 f OSC 2 T CPO + 1 f OSC (542ns " 42ns at f OSC + 12 MHz) F OSC 8051 CORE P1.4 HSYNC Clamp Pulse Generator CPO/P1.4 PIN T0L CPP CPE Figure 17. Clamp Pulse Output block diagram HSYNC T0L bit=1 CPO CPP bit=1 CPO CPP bit=0 T CPO HSYNC T0L bit=0 CPO CPP bit=1 CPO CPP bit=0 Figure 18. Clamp Pulse Output waveform MATRA MHS Rev. A (10 Jan. 97) 19 Preview TSC8051C2 8. Electrical Characteristics Absolute Maximum Ratings(1) Operating Temperature: Voltage on VCC to VSS . . . . . . . . . . . . . . –0.5V to +7V Commercial . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Voltage on Any Pin to VSS . . . . –0.5V to VCC + 0.5V Industrial . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . 1W(2) Storage Temperature . . . . . . . . . . . . . –65ºC to +150ºC Notice: 1. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. This value is based on the maximum allowable die temperate and the thermal resistance of the package. 8.1. DC Characteristics TA = 0°C to +70°C; VSS = 0V; VCC = 5V ± 10%; F = 0 to 16MHz. TA = –40°C to +85°C; VSS = 0V; VCC = 5V ± 10%; F = 0 to 16MHz. Symbol Inputs VIL VIH VIH1 IIL ILI ITL VLOW Input Low Voltage Input High Voltage except XTAL1, RST Input High Voltage, XTAL1, RST Logical 0 Input Current ports 1, 2 and 3 Input Leakage Current Logical 1 to 0 Transition Current, ports 1, 2, 3 Power Fail Reset Low Voltage TBD 3.5(5) –0.5 0.2 Vcc + 0.9 0.7 Vcc 0.2 Vcc – 0.1 Vcc + 0.5 Vcc + 0.5 –50 ±10 –650 TBD V V V µA µA µA V Vin = 0.45V 0.45 < Vin < Vcc Vin = 2.0V Parameter Min Typ Max Unit Test Conditions Outputs VOL Output Low Voltage, ports 1, 2, 3, PWM0–7 (6) Output Low Voltage, port 0, ALE, PSEN (6) 0.3 0.45 1.0 0.3 0.45 1.0 Vcc – 0.3 Vcc – 0.7 Vcc – 1.5 V V V V V V V V V IOL = 100µA(4) IOL = 1.6mA(4) IOL = 3.5mA(4) IOL = 200µA(4) IOL = 3.2mA(4) IOL = 7.0mA(4) IOH = –10µA IOH = –30µA IOH = –60µA Vcc = 5V ± 10% IOH =–200µA IOH = –3.2mA IOH = –7.0mA Vcc = 5V ± 10% VOL1 VOH Output High Voltage, ports 1, 2, 3 VOH1 Output High Voltage, port 0, ALE, PSEN Vcc – 0.3 Vcc – 0.7 Vcc – 1.5 90 (5) V V V kΩ pF RRST CIO RST Pulldown Resistor Capacitance of I/O Buffer 50 200 10 fc = 1MHz, TA = 25°C 20 MATRA MHS Rev. A (10 Jan. 97) Preview TSC8051C2 Symbol ICC Parameter Power Supply Current Active Mode 12MHz Idle Mode 12MHz Power Down Current (7) Min Typ TBD TBD 5 (5) Max TBD TBD 30 Unit mA mA µA Test Conditions Vcc = 5.5V(1) Vcc = 5.5V(2) Vcc = 2.0V to 5.5V(3) IPD Notes for DC Electrical Characteristics 1. ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns (see Figure 20. ), VIL = VSS + 0.5V, VIH = VCC – 0.5V; XTAL2 N.C.; EA = RST = Port 0 = VCC. ICC would be slightly higher if a crystal oscillator used (see Figure 19. ). 2. Idle ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5ns, VIL = VSS + 0.5V, VIH = VCC–0.5V; XTAL2 N.C; Port 0 = VCC; EA = RST = VSS (see Figure 20. ). 3. Power Down ICC is measured with all output pins disconnected; EA = PORT 0 = VCC; XTAL2 NC.; RST = VSS (see Figure 21. ). 4. Capacitance loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLs of ALE and Ports 1 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to 0 transitions during bus operation. In the worst cases (capacitive loading 100pF), the noise pulse on the ALE line may exceed 0.45V with maxi VOL peak 0.6V. A Schmitt Trigger use is not necessary. 5. Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature and 5V. 6. Under steady state (non–transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: 10 mA Maximum IOL per 8–bit port: Port 0: 26 mA Ports 1, 2 and 3: 15 mA Maximum total IOL for all output pins: 71 mA If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 7. For other values, please contact your sales office. VCC ICC VCC P0 VCC RST (NC) CLOCK SIGNAL XTAL2 XTAL1 VSS All other pins are disconnected. EA VCC VCC ICC VCC P0 RST (NC) CLOCK SIGNAL XTAL2 XTAL1 VSS All other pins are disconnected. EA VCC Figure 20. ICC Test Condition, Idle Mode. VCC ICC VCC P0 RST (NC) XTAL2 XTAL1 VSS All other pins are disconnected. EA VCC Figure 21. ICC Test Condition, Power Down Mode. Figure 19. ICC Test Condition, Active Mode. MATRA MHS Rev. A (10 Jan. 97) 21 Preview TSC8051C2 Vcc–0.5V 0.7Vcc 0.2Vcc–0.1 0.45V TCHCL TCLCH TCLCH = TCHCL = 5ns. Figure 22. Clock Signal Waveform for ICC Tests in Active and Idle Modes. 8.2. Explanation Of The AC Symbol Each timing symbol has 5 characters. The first character is always a “T” (stands for time). The other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. The following is a list of all the characters and what they stand for. A: Address. C: Clock. D: Input data. H: Logic level HIGH. I: Instruction (Program memory contents). L: Logic level LOW, or ALE. P: PSEN. Example: TAVLL = Time for Address Valid to ALE low. TLLPL = Time for ALE low to PSEN low. Q: Output data. R: READ signal. T: Time. V: Valid. W: WRITE signal. X: No longer a valid logic level. Z: Float. 8.3. AC Parameters TA = 0 to +70_C; VSS = 0V VCC = 5V±10%; 0 to 12MHz TA = –40°C to +85°C; VSS = 0V; VCC = 5V ± 10%; F = 0 to 12MHz. (Load Capacitance for PORT 0, ALE and PSEN = 100pf; Load Capacitance for all other outputs = 80 pF.) 8.4. External Program Memory Characteristics 0 to 12MHz Symbol Symbol TLHLL TAVLL TLLAX TLLIV TLLPL TPLPH TPLIV ALE pulse width Address Valid to ALE Address Hold After ALE ALE to Valid Instruction In ALE to PSEN PSEN Pulse Width PSEN to Valid Instruction In TCLCL – 30 3TCLCL – 45 3TCLCL – 105 Parameter Parameter Min 2TCLCL – 40 TCLCL – 40 TCLCL – 30 4TCLCL – 100 Units Units Max ns ns ns ns ns ns ns 22 MATRA MHS Rev. A (10 Jan. 97) Preview TSC8051C2 0 to 12MHz Symbol TPXIX TPXIZ TPXAV TAVIV TPLAZ Parameter Min Input Instruction Hold After PSEN Input Instruction Float After PSEN PSEN to Address Valid Address to Valid Instruction In PSEN Low to Address Float TCLCL – 8 5TCLCL – 105 10 0 TCLCL – 25 Units Max ns ns ns ns ns 8.5. External Program Memory Read Cycle 12 TCLCL TLHLL ALE TLLIV TLLPL TPLPH PSEN TLLAX TAVLL PORT 0 INSTR IN A0–A7 TAVIV PORT 2 ADDRESS OR SFR–P2 ADDRESS A8–A15 ADDRESS A8–A15 TPLIV TPLAZ TPXIX INSTR IN A0–A7 INSTR IN TPXAV TPXIZ 8.6. External Data Memory Characteristics 0 to 12MHz Symbol Symbol TRLRH TWLWH TRLDV TRHDX TRHDZ TLLDV TAVDV TLLWL TAVWL TQVWX TQVWH TWHQX TRLAZ TWHLH RD Pulse Width WR Pulse Width RD to Valid Data In Data Hold After RD Data Float After RD ALE to Valid Data In Address to Valid Data In ALE to WR or RD Address to WR or RD Data Valid to WR Transition Data set–up to WR High Data Hold After WR RD Low to Address Float RD or WR High to ALE high TCLCL–40 3TCLCL–50 4TCLCL–130 TCLCL–50 7TCLCL–150 TCLCL–50 0 TCLCL+40 0 2TCLCL–60 8TCLCL–150 9TCLCL–165 3TCLCL+50 Parameter Parameter Min 6TCLCL–100 6TCLCL–100 5TCLCL–165 Units Units Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns MATRA MHS Rev. A (10 Jan. 97) 23 Preview TSC8051C2 8.7. External Data Memory Write Cycle TWHLH ALE PSEN TLLWL TWLWH WR TQVWX TLLAX PORT 0 A0–A7 TAVWL PORT 2 ADDRESS OR SFR–P2 ADDRESS A8–A15 OR SFR P2 TQVWH DATA OUT TWHQX 8.8. External Data Memory Read Cycle TWHLH ALE TLLDV PSEN TLLWL TRLRH RD TAVDV TLLAX PORT 0 A0–A7 TAVWL PORT 2 ADDRESS OR SFR–P2 TRLAZ ADDRESS A8–A15 OR SFR P2 TRHDX DATA IN TRHDZ 8.9. Serial Port Timing–Shift Register Mode 0 to 12MHz Symbol Symbol TXLXL TQVHX TXHQX TXHDX TXHDV Parameter Parameter Min Serial port clock cycle time Output data set–up to clock rising edge Output data hold after clock rising edge Input data hold after clock rising edge Clock rising edge to input data valid 12TCLCL 10TCLCL–133 2TCLCL–117 0 10TCLCL–133 Units Units Max ns ns ns ns ns 24 MATRA MHS Rev. A (10 Jan. 97) Preview TSC8051C2 8.10. Shift Register Timing Waveforms INSTRUCTION ALE TXLXL CLOCK TQVXH OUTPUT DATA WRITE to SBUF INPUT DATA CLEAR RI 0 TXHDV VALID VALID 0 1 2 3 4 5 6 7 8 TXHQX 1 2 TXHDX VALID VALID VALID VALID VALID 3 4 5 6 7 SET TI VALID SET RI 8.11. External Clock Drive Characteristics (XTAL1) Symbol TCLCL TCHCX TCLCX TCLCH TCHCL Oscillator Period High Time Low Time Rise Time Fall Time Parameter Min 83.3 5 5 Max Units ns ns ns 5 5 ns ns 8.12. External Clock Drive Waveforms Vcc–0.5V 0.45V 0.7Vcc 0.2Vcc–0.1 TCHCL TCLCX TCLCL TCHCX TCLCH 8.13. AC Testing Input/Output Waveforms Vcc –0.5 V INPUT/OUTPUT 0.45 V 0.2 Vcc + 0.9 0.2 Vcc – 0.1 AC inputs during testing are driven at Vcc – 0.5 for a logic “1” and 0.45V for a logic “0”. Timing measurement are made at VIH min for a logic “1” and VIL max for a logic “0”. MATRA MHS Rev. A (10 Jan. 97) 25 Preview TSC8051C2 8.14. Float Waveforms FLOAT VOH – 0.1 V VOL + 0.1 V FLOAT VLOAD VLOAD + 0.1 V VLOAD – 0.1 V For timing purposes as port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded VOH/VOL level occurs. IOL/IOH ≥ ± 20mA. 8.15. Clock Waveform This diagram indicates when signals are clocked internally. The time it takes the signals to propagate to the pins, however, ranges from 25 to 125ns. This propagation delay is dependent on variables such as temperature and pin loading. Propagation also varies from output to output and component. Typically though (TA=25_C fully loaded) RD and WR propagation delays are approximately 50ns. The other signals are typically 85ns. Propagation delays are incorporated in the AC specifications. 26 MATRA MHS Rev. A (10 Jan. 97) Preview TSC8051C2 INTERNAL CLOCK XTAL2 ALE THESE SIGNALS ARE NOT ACTIVATED DURING THE EXECUTION OF A MOVX INSTRUCTION STATE4 P1 P2 STATE5 P1 P2 STATE6 P1 P2 STATE1 P1 P2 STATE2 P1 P2 STATE3 P1 P2 STATE4 P1 P2 STATE5 P1 P2 EXTERNAL PROGRAM MEMORY FETCH PSEN P0 DATA SAMPLED FLOAT P2 (EXT) PCL OUT DATA SAMPLED FLOAT INDICATES ADDRESS TRANSITIONS PCL OUT DATA SAMPLED FLOAT PCL OUT READ CYCLE RD 00H IS EMITTED DURING THIS PERIOD DPL OR Rt OUT PCL OUT (IF PROGRAM MEMORY IS EXTERNAL) DATA SAMPLED FLOAT P0 P2 INDICATES DPH OR P2 SFR TO PCH TRANSITION WRITE CYCLE WR PCL OUT (EVEN IF PROGRAM MEMORY IS INTERNAL) DPL OR Rt OUT DATA OUT P2 INDICATES DPH OR P2 SFR TO PCH TRANSITION PCL OUT (IF PROGRAM MEMORY IS EXTERNAL) P0 PORT OPERATION MOV PORT SRC OLD DATA P0 PINS SAMPLED MOV DEST P0 MOV DEST PORT (P1. P2. P3) (INCLUDES INTO. INT1. TO T1) SERIAL PORT SHIFT CLOCK TXD (MODE 0) P1, P2, P3 PINS SAMPLED P1, P2, P3 PINS SAMPLED NEW DATA P0 PINS SAMPLED RXD SAMPLED RXD SAMPLED MATRA MHS Rev. A (10 Jan. 97) 27 Preview TSC8051C2 9. Ordering Information 12 16 TSC 51C2 XXX –A C B R Part Number 8051C2: Romless version 51C2: 4Kx8 Mask ROM –12 : 12 MHz version –16 : 16 MHz version Bounding Option –none : 12 PWM –A : 4 PWM & P2x Customer Rom Code TEMIC Semiconductor Microcontroller Product Line Packaging A : PDIL 40 B : PLCC 44 C : PQFP 44 D : SSOP 44 E : PLCC 52 G : CDIL 40 H : LCC 44 I : CQPJ 44 Conditioning R : Tape & Reel D : Dry Pack B : Tape & Reel and Dry Pack Temperature Range C : Commercial 0° to 70°C I : Industrial –40° to 85°C Examples Part Number TSC51C2XXX–12CA TSC8051C2–16CER Description Mask ROM XXX, 12 MHz, PDIL 40, 0 to 70°C ROMless, 16 MHz, PLCC 52, 0 to 70°C, Tape and Reel Development Tools Reference ANM059 IM–80C51–RB–400–40 PC–TSC8051C1–RB–16 Description Application Note: “How to recognize video mode and generate free running synchronization signals using TSC8051C1/C2 Microcontroller” Emulator Base Probe card for TSC8051C1. These products are released by Metalink. Please consult the local tools distributor or your sales office. Product Marking : TEMIC Customer P/N Temic P/N © Intel 80, 82 YYWW Lot Number 28 MATRA MHS Rev. A (10 Jan. 97) Preview