U2733B-C

U2733B-C Fractional-N Frequency Synthesizer for DAB Tuner Description The U2733B-C is a monolithically integrated fractional-N frequency synthesizer circuit fabricated in TEMIC’s advanced UHF5S technology. Designed for applications in DAB receivers, it controls a VCO to synthesize frequencies in the range of 70 to 500 MHz in a 16 kHz raster; four different reference divide factors can be selected. The lock status of the phase detector is indicated at a special output pin, six switching outputs can be addressed. An internal frequency doubler provides an output signal having twice the frequency of the reference oscillator. All functions of this IC are controlled by I2C bus. Features D Microprocessor controlled via I2C bus D 4 addresses selectable D Four reference divide factors selectable: 1024, 1120, 1152, 1536 D Superior phase noise performance D Deactivation of tuning output programmable D 6 switching outputs (open collector) D Reference frequency doubler (open collector output) D Lock status indication (open collector) D Fully compatible to U2753B-C D SSO20 package D Effectively D Programmable 15-bit counter 1:2048 to 1:32767 effectively D Three state phase detector with programmable charge pump Block Diagram FDO 10 Frequency doubler x2 Lock detector REF NREF 4 5 Reference counter Three State Phase Detector Fractional N control 2 Prog. charge pump VD 1 PD NFDO 9 3 PLCK 18 RF NRF 17 Prog. 13 Bit counter N/N=1 4 Bit latch 7 Bit latch 2 Bit latch 5 Bit latch MUX MUX I2C Bus – Interface / Control Switches 19 20 6 ADR 7 8 11 12 13 14 15 16 GND VS SCL SDA SWC SWD SWE SWF SWG SWH 12476 Figure 1. Block diagram TELEFUNKEN Semiconductors Rev. A1, 21-Aug-96 1 (14) Preliminary Information U2733B-C Pin Description PD VD PLCK REF NREF ADR SCL SDA NFDO FDO 1 2 3 4 5 6 7 8 9 10 12484 20 VS 19 GND 18 RF 17 NRF 16 SWH 15 SWG 14 SWF 13 SWE 12 SWD 11 SWC Figure 2. Pinning Functional Description The U2733B-C is a low power fractional-N frequency synthesizer designed for applications in DAB receivers. Its RF operation range reaches from 70 MHz up to 500 MHz. The device includes input buffers for reference and RF dividers, a reference divider, a programmable RF divider using fractional-N technique, a tri-state phase detector, a programmable charge pump, six switching outputs, a frequency doubler for the reference input signal and a control unit. The control unit has to be accessed by a micro controller via I2C bus. The programming information is stored in a set of internal registers. The basic difference of this circuit from the U2753B-C is the use of a special phase noise shaping technique based on the fractional-N principle which concentrates the 2 (14) Preliminary Information Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ Á 4 5 6 7 8 9 REF NREF ADR SCL SDA NFDO FDO 10 11 SWC 12 13 14 15 16 17 18 19 20 SWD SWE SWF SWG SWH NRF RF GND VS phase detector’s phase noise contribution to the spectrum of the controlled VCO at frequency positions where it doesn’t damage the quality of the received DAB signal. In critical locations of the VCO’s frequency spectrum the phase detectors phase noise contribution is reduced by roughly 12 dB. A special property of the transmission technique which is used in DAB is that the phase noise weighting function which measures the influence of the LO’s phase noise to the phase information of the coded signal in a DAB receiver has zeros, i.e., if phase noise is concentrated in the position of such zeros as discrete lines the DAB signal is not disturbed as long as these lines don’t exceed a certain limit. TELEFUNKEN Semiconductors Rev. A1, 21-Aug-96 Pin 1 2 3 Symbol PD VD PLCK Function Three-state charge pump output Active filter output Lock indicating output (open collector) Reference input Reference input (inverted) Address selection Clock (I2C) Data (I2C) Frequency doubler output (inverted, open collector) Frequency doubler output (open collector) Switching output (opencollector) Switching output (open collector) Switching output (open collector) Switching output (open collector) Switching output (open collector) Switching output (open collector) RF input (inverted) RF input Ground Supply voltage U2733B-C For DAB mode I this phase noise weighting function is shown in the following figure: 1,80 1,60 1,40 1,20 PNWF 1,00 0,80 0,60 0,40 0,20 0,00 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 df / Hz 12477 division ratio is either N or N+1 according to the control of a special control unit. On average the scaling factors SF = N+k/ 4 can be selected where k = 0, 1, 2, 3. In this way VCO frequencies fVCO = 4 (N+k/4) fref/(4 SFref) can be synthesized starting from a reference frequency fref.. If we define SFeff = 4 N+k and SFref, eff = 4 SFref we end up with fVCO = SFeff fref/SFref,eff, Figure 3. It is important to realize that this function shows zeros in all distances from the center line which are multiples of the carrier spacing. The technique of concentrating the phase noise in the positions of such zeros is protected by a patent. In this circuit the phase detector is operated at a frequency which is four times the desired frequency raster spacing (e.g., 16 kHz in case of DAB) and the well known fractional-N technique is used to synthesize the raster. As a result of this technique in the VCO’s frequency spectrum spurious occur not only in multiples of the phase detectors input comparison frequency (64 kHz) but also in multiples of the raster frequency (16 kHz). As described above for all DAB modes these spurious are placed in spectral positions where the phase noise weighting function is zero. Therefore no measures are necessary to suppress these lines. where SFeff is defined by 15 bits. In the following this circuit is described in terms of SFeff and SFref,eff. SFeff has to be programmed via the I2C bus interface. An effective scaling factor from 2048 up to 32767 can be selected. By setting of the I2C bus bit ‘T’ a test signal representing the divided input signal can be monitored at the switching output SWF. When the supply voltage is switched on both the reference divider and the programmable divider are kept in RESET state till a complete scaling factor is written onto the chip. Changes in the setting of the programmable divider become active when the corresponding I2C bus transmission is completed. By an internal synchronization procedure is ensured that such changes don’t become active while the charge pump is sourcing or sinking current at its output pin. This behavior allows a smooth tuning of the output frequency without disturbing the controlled VCO’s frequency spectrum. Reference Divider Four different scaling factors SFref of the reference divider can be selected by means of the bits ‘RD1’ and ‘RD2’ in the I2C bus instruction code: 256, 280, 288, and 384. Starting from a reference oscillator frequency of 16.384 MHz/ 17.92 MHz/ 18.432 MHz/ 24.576 MHz these scaling factors provide a frequency raster of 64 kHz. By changing the division ratio of the main divider from N to N+1 in an appropriate way (fractional-N technique) this frequency raster is interpolated to deliver a frequency spacing of 16 kHz according to the DAB specification. So effectively the reference divide factors 1024, 1120, 1152 and 1536 can be selected. By setting of the I2C bus bit ‘T’ a test signal representing the divided input signal can be monitored at the switching output SWC. Phase Comparator and Charge Pump The tri-state phase detector causes the charge pump to source or to sink current at the output pin PD depending on the phase relation of its input signals which are provided by the reference and the main divider respectively. Four different values of this current can be selected by means of the I2C bus bits ‘I50’ and ‘I100’. By use of this option for example changes of the loop characteristics due to the variation of the VCO gain as a function of the tuning voltage can be reduced. The charge pump current can be switched off using the I2C bus bit ‘TRI’. A change in the setting of the charge pump current becomes active when the corresponding I2C bus transmission is completed. As described for the setting of the scaling factor of the programmable divider an internal synchronization procedure ensures that such changes don’t become active while the charge pump is sourcing or sinking current at its output pin. This behavior allows a change in the charge pump current without disturbing the controlled VCO’s frequency spectrum. Main Divider The main divider consists of a fully programmable 13-bit divider which defines a division ratio N. The applied TELEFUNKEN Semiconductors Rev. A1, 21-Aug-96 3 (14) Preliminary Information U2733B-C A high gain amplifier (output pin: VD) which is implemented in order to construct a loop filter as shown in the application circuit can be switched off by means of the I2C bus bit ‘OS’. An internal lock detector checks if the phase difference of the input signals of the phase detector is smaller than approximately 250 ns in seven subsequent comparisons. If phase lock is detected the open collector output pin PLCK is set ‘H’ (logical value!). It should be noted that the output current of this pin must be limited by external circuitry as it is not limited internally. If the I2C bus bit ‘TRI’ is set ‘H’ the lock detector function is deactivated and the logical value of the PLCK output is undefined. Frequency Doubler An internal frequency doubler provides a signal at twice the frequency of the reference signal appearing at the input pins REF and NREF. If the I2C bus bit ‘OFD’ = ‘H’ the current of its open collector outputs FDO and NFDO is doubled. By means of the I2C bus bit ‘OFD’ the frequency doubler function can be switched off. As shown on page 15 (Integration in TEMIC DAB Receiver Concept) the output signal of the frequency doubler can be used in order to construct the LO signal of the IF circuit (U2759B). I2C Bus Interface Via its I2C bus interface various functions can be controlled by a microprocessor. These functions are overviewed in the following sections ‘I2C bus instruction codes’ and ‘I2C bus functions’. By means of the ADR pin four different I2C bus addresses can be selected as described in the section ‘Electrical characteristics’. Switching Outputs Six switching outputs controlled by the bus bits ‘SWC’, ‘SWD’, ‘SWE’, ‘SWF’, ‘SWG’, ‘SWH’ can be used for any switching task on the front end board. The currents of these outputs are not limited internally. They have to be limited by external circuitry. I2C 4 (14) Preliminary Information TELEFUNKEN Semiconductors Rev. A1, 21-Aug-96 U2733B-C I2C Bus Instruction Codes ÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁ Á Á Á Á Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁ Á Á Á Á Á Á Á ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ Á Á Á Á Á Á ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ 1 RD1 X X X 2IFD 0 0 RD2 n11 n5 0 SWC 0 0 X n10 n4 OS SWD 0 0 X n9 n3 T SWE 0 AS1 n14 n8 n2 TRI SWF 0 AS2 n13 n7 n1 I100 SWG 0 Description Address byte Divider byte 1 Divider byte 2 Divider byte 3 Control byte 1 Control byte 2 Control byte 3 MSB 1 0 X X 1 OFD X LSB 0 n12 n6 n0 I50 SWH 0 I2C Bus Functions AS1, AS2 RD1, RD2 RD1 I2C Bus Data Transfer Format define the I2C bus address define the effective scaling factor of the reference divider: RD2 Effective Scaling Factor 1120 1152 1024 1536 START – ADR – ACK – – STOP The consists of a sequence of divider bytes and control bytes each followed by ACK. Divider byte i must be followed by divider byte i+1 (control byte 1 if i = 3) or the instruction set must be finished. Control bytes have to be handled accordingly. Examples START – ADR – ACK – DB1 – ACK – DB2 – ACK – DB3 – ACK – CB1 – ACK – CB2 –ACK – CB3 – ACK – STOP START – ADR – ACK – CB1 – ACK – CB2 – ACK – STOP However START – ADR – ACK – DB1 – ACK – CB1 –ACK – STOP is not allowed. Description START STOP ACK ADR DBi CBi start condition stop condition acknoledge address byte divider byte i (i = 1, 2, 3) control byte i (i = 1, 2, 3) Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ Á ÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ 0 1 0 1 0 0 1 1 ni effective scaling factor (SFeff) of the main divider SFeff = SUM(ni 2i) OS = ‘H’ switches off tuning output OS T for T = ‘H’ reference signals describing the output frequencies of reference reference divider and programmable divider are monitored at SWF (prog. div.) and SWC (ref. div.) TRI = ‘H’ switches off charge pump define the charge pump current: I100 ’L’ ’L’ ’H’ ’H’ TRI I50, I100 I50 ’L’ ’H’ ’L’ ’H’ Charge Pumup Current (nominal)/A 50 102 151 203 OFD OFD = ‘H’ switches off frequency doubler 2IFD SWa 2IFD = ‘H’ doubles the frequency doubler output current SWa = ‘H’ switches on output current TELEFUNKEN Semiconductors Rev. A1, 21-Aug-96 5 (14) Preliminary Information U2733B-C I2C Bus Timing The values of the drawn periods are specified in the section ‘Electrical Characteristics’. More detailed informations can be taken from ‘Application Note 1.0 (I2C Bus Description)’. Please note: due to the I2C bus specification the MSB of a byte is transmitted first, the LSB last. SDA t buf tr tr t hdstat SCL t hdsta STOP START t low t t hddat t high t sudat t susta START t sustp STOP 12478 Figure 4. Typical Pulse Diagram START SDA SCL Address byte ACK Divider byte ACK Divider byte 2 ACK Divider byte 3 SDA SCL ACK Control byte 1 ACK Control byte 2 ACK STOP 12479 Figure 5. 6 (14) Preliminary Information TELEFUNKEN Semiconductors Rev. A1, 21-Aug-96 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Operating Range Parameter Supply voltage Ambient temperature range Junction temperature Storage temperature Pin Vs Tamb Conditions 125 –40 to 125 Value 4.5 to 5.5 –30 to+85 Unit V °C °C °C ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á ÁÁ ÁÁ ÁÁÁÁ Á Á ÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Absolute Maximum Ratings I2C bus input/ output voltage SDA output current Address select voltage Switch output current Switch output voltage PLCK output current PLCK output voltage Frequency doubler output Parameter Supply voltage RF input voltage (AC) Reference input voltage (AC) Pin VS RF, NRF REF, NREF SCL, SDA SDA ADR SWa SWa PLCK PLCK FDO, NFDO Tj Tstg Open collector Open collector Open collector Open collector Open collector Conditions –0.3 to VS 5 –0.3 to VS 4 –0.3 to 5.5 0.5 –0.3 to 5.5 VS –1 to 5.5 Value –0.3 to 5.5 1 1 TELEFUNKEN Semiconductors Rev. A1, 21-Aug-96 Thermal Resistance Parameter Junction ambient Preliminary Information Pin RthJA Conditions SSO20 U2733B-C Value 140 Unit K/W 7 (14) Unit V Vpp Vpp V mA V mA V mA V V ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ Á Á Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ Á Á Á Á Á ÁÁ Á Á ÁÁ ÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ Á Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ Á Á Á Á Á ÁÁ Á Á ÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ Á Á Á Á Á ÁÁ Á Á ÁÁ ÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁ Á Á Á ÁÁ Á Á ÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ Á Á Á Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ Á Á Á Á Á ÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ Á Á Á Á Á ÁÁ Á Á ÁÁ Á ÁÁ ÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ Á Á Á ÁÁ Á Á ÁÁ Á Á ÁÁ Á ÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ Á Á Á Á Á ÁÁ Á ÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁ Á Á ÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁ Á Á Á Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ Á Á Á Á Á ÁÁ Á ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ Á Á ÁÁ Á ÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁ ÁÁÁ ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ Á Á ÁÁ ÁÁÁ ÁÁÁÁ Á Á Á Á Á ÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ Test conditions: VS = 5 V, Tamb = 27°C, unless otherwise specified Electrical Characteristics U2733B-C 8 (14) Effective phase noise *) Lock indication Phase detector Charge pump current Input sensitivity Max. input signal Input impedance Input frequency range REF input Input sensitivity Max. input signal Input impedance VSWR RF input Input frequency range Tuning step Effective scaling factor of programmable divider Effective scaling factor of reference divider Characteristics Supply current RF, NRF REF, NREF PLCK Pin Vs PD Preliminary Information Vrfs Vrfmax Zrf VSWRrf IPD4 ± IPD3 ± IPD2 ± IPD1 ± IPD,tri Symbol Is SFref,eff Vrefs Vrefmax Zref ± SFeff LPD frast fref Iso frf Conditions SWa=‘L’,TRI=‘L’, PLCK=‘L’,OS=‘L’, I50=‘H’, I100=‘H’, OFD=‘L’,2IFD=‘L’ SWa=‘L’,TRI=‘L’, PLCK=‘L’,OS=‘L’, I50=‘H’, I100=‘H’, OFD=‘H’,2IFD=‘L’ RD1=‘L’,RD2=‘L’ RD1=‘H’,RD2=‘L’ RD1=‘L’,RD2=‘H’ RD1=‘H’,RD2=‘H’ 17.920 MHz/ 18.432 MHz/ 16.384 MHz/ 24.576 MHz ref. frequency I100=’H’, I50=’H’ I100=’L’, I50=’H’ I100=’H’, I50=’L’ I100=’L’, I50=’L’ Single ended VS = 4.5 V, Tamb = 20°C VS = 4.5 V, Tamb = 20°C Differential IPD=203A TRI = ’H’ ± 120 ± 160 2048 Min. 13.2 ± 40 ± 80 70 5 TELEFUNKEN Semiconductors Rev. A1, 21-Aug-96 17.92 18.432 10 ± 102 ± 151 ± 203 1120 1152 1024 1536 16 –163 ± 50 Typ. 16.5 14.6 ø 200 2 2.7 2.5 10 32767 ± 100 ± 120 ± 180 ± 240 Max 19.8 ± 60 300 20 300 500 30 dBc/Hz mVrms mVrms k pF mVrms mVrms MHz MHz Unit mA kHz mA nA A A A A ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á Á Á ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ Á Á Á Á Á ÁÁ Á Á ÁÁ ÁÁ Á ÁÁ Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁ Á Á Á Á Á ÁÁ Á Á Á ÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁ Á Á ÁÁ Á ÁÁ Á ÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁ Á Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁ ÁÁÁÁ Á Á Á Á Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ Á Á ÁÁ Á Á ÁÁ Á ÁÁ Á ÁÁ Á ÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁ Á ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ Á Á ÁÁ Á Á ÁÁ Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁ Á ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á Á ÁÁ ÁÁ Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁ ÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁÁÁ Á Á Á ÁÁ Á ÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ Á ÁÁ Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ Á ÁÁ *) Set up time DATA Hold time DATA Set up time STOP Set up time START Hold time START SCL ‘L’ period Fall time (SCL; SDA) Time before new transmission can start SCL ‘H’ period SCL clock frequency Rise time (SCL, SDA) Output voltage SDA (open collector) Saturation voltage Address selection AS1=0, AS2=0 AS1=0, AS2=1 AS1=1, AS2=0 AS1=1, AS2=1 I2C bus Input voltage SCL/SDA p g Minimum output voltage Switches Leakage current Output current Saturation voltage Frequency doubler Characteristics Leakage current The phase detectors phase noise contribution to the VCO’s frequency spectrum is refered to the operating frequency of the phase detector divided by 4 according to the fractional-N technique (regularly: 16 kHz). SCL, SDA FDO, NFDO ADR SWa Pin VPLCK,sat Symbol IPLCK,L IFDOH, INFDOH IFDOL, INFDOL VSW,sat VFDO, VNFDO ISW,L thddat tsudat thdsta tsustp tsusta fSCL tr thigh tlow tf tbuf VH VL IPLCK = 0.5 mA Conditions VPLCK = 5.5 V VSWa = 5.5 V VFDO = VS, VNFDO = VS, 2IFD = ’L’ VFDO = VS, VNFDO = VS, 2IFD = ’H’ VS = 5 V ISWa = 4 mA ‘High’ ‘Low’ ISDA = 2mA SDA = ‘L’ 0.4 VS 0.9 VS Min. 250 4.7 4.7 4.7 4.7 0.1 0.8 0.4 0 4 4 3 0 4 open Typ. 1.0 0.5 TELEFUNKEN Semiconductors Rev. A1, 21-Aug-96 Preliminary Information U2733B-C 0.6 VS VS 0.1 VS Max 10 300 100 1 5.5 1.5 0.4 0.5 1.2 0.6 0.5 10 mApp mApp Unit kHz 9 (14) ns ns A A V V V V V V s s s s s s s s U2733B-C Application Circuit + 8.5 V U2309B/ U2750B VCO signal VS 1n tuning voltage 20 19 18 17 16 15 14 13 12 11 1n Band switches Alternative load circuit: VS 600ENS-9272Y (TOKO) L1, L2: LL1608-F47NJ (TOKO) L1 L2 47nH (5%) 47nH (5%) for fres = 36MHz 180p (1%) 1 2 3 4 5 6 7 8 9 10 47k 1n 1n 1n 470p 4.7n 27p (1%) (18p) 1n U2759B VS 15p (5%) U2733B-C + 17 V 22K 1k 10n 1k 10n mC BC846B Address select voltage +5V 12480 22K Ref. OSC. Figure 6. Application circuit 10 (14) Preliminary Information TELEFUNKEN Semiconductors Rev. A1, 21-Aug-96 U2733B-C Phase Noise Performance (Example: SFeff = 16899, SFref,eff = 1120, fref = 17.92 MHz, IPD = 200 A, reference oscillator: MARCONI INSTRUMENTS signal generator 2042, 10.00 dB/DIV spectrum analysis: HP70000, above shown application circuit, band A oscillator of U2309B) 10.00 dB/DIV –70.5 dBc/Hz CENTER 270.384 MHz RB 100 Hz VB 100 Hz SPAN 10.00 kHz ST 3.050 sec 12481 CENTER 270.384 MHz RB 1.00 kHz VB 1.00 kHz SPAN 200.0 kHz ST 600.0 msec 12482 Figure 7. Figure 8. TELEFUNKEN Semiconductors Rev. A1, 21-Aug-96 11 (14) Preliminary Information U2733B-C Integration in TEMIC DAB Receiver Concept 12 (14) U2750B AGC U2309B AGC 79 ... 240 MHz U2759B IF2 (IF3) SAW 3.072 MHz VCO X190 ... 230 MHz 38.912 MHz 35.84 MHz PIN L-Band Down-converter FSYNCGENERATION Channel Decoder Figure 9. DAB Receiver Frontend U2733B-C PLL – 17.92 MHz DCXO Preliminary Information System controller AFC TELEFUNKEN Semiconductors Rev. A1, 21-Aug-96 12483 U2733B-C Package Dimensions SSO20 all dimensions in mm 0.15 +/– 0.05 4.40 +/– 0.1 6.45 +/– 0.1 6.5 +/– 0.1 1.375 +/– 0.125 0.05 min 0.25 +/– 0.05 0.65 Pin 1 TELEFUNKEN Semiconductors Rev. A1, 21-Aug-96 13 (14) Preliminary Information U2733B-C Ozone Depleting Substances Policy Statement It is the policy of TEMIC TELEFUNKEN microelectronic GmbH to 1. Meet all present and future national and international statutory requirements. 2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances ( ODSs). The Montreal Protocol ( 1987) and its London Amendments ( 1990) intend to severely restrict the use of ODSs and forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these substances. TEMIC TELEFUNKEN microelectronic GmbH semiconductor division has been able to use its policy of continuous improvements to eliminate the use of ODSs listed in the following documents. 1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively 2 . Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental Protection Agency ( EPA) in the USA 3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C ( transitional substances ) respectively. TEMIC can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances. We reserve the right to make changes to improve technical design and may do so without further notice. Parameters can vary in different applications. All operating parameters must be validated for each customer application by the customer. Should the buyer use TEMIC products for any unintended or unauthorized application, the buyer shall indemnify TEMIC against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. TEMIC TELEFUNKEN microelectronic GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany Telephone: 49 ( 0 ) 7131 67 2831, Fax number: 49 ( 0 ) 7131 67 2423 14 (14) Preliminary Information TELEFUNKEN Semiconductors Rev. A1, 21-Aug-96