CH0402-330RGNW

CH www.vishay.com Vishay Sfernice AEC-Q200 Qualified High Frequency 70 GHz Thin Film Chip Resistor FEATURES • • • • • • • • • • • • • • Operating frequency 70 GHz AEC-Q200 qualified (CH02016 flip chip only) Thin film microwave resistors Flip chip, wraparound or one face termination Small size, down to 20 mils by 16 mils Edged trimmed block resistors Pure alumina substrate (99.5 %) Ohmic range: 10R to 500R Design kits available Modelithics® library available Small internal reactance (LC down to 1 x 10-24) Tolerance 1 %, 2 %, 5 % TCR: 100 ppm/°C in (-55 °C, +155 °C) temperature range TCR: 50 ppm/°C available upon request for 10  to150  ohmic range • Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 LINKS TO ADDITIONAL RESOURCES 3D 3D 3D Models S-Parameters Simulation Tools Did You Know? Infographics Why It Matters Application Notes Capabilities and Custom Options Those miniaturized components are designed in such a way that their internal reactance is very small. When correctly mounted and utilized, they function as almost pure resistors on a very large range of frequency, up to 50 GHz, and 70 GHz for CH02016 from 50  to 100 . STANDARD ELECTRICAL SPECIFICATIONS MODEL SIZE CH02016 CH0402 CH0603 02016 0402 0603 RESISTANCE RANGE  10 to 500 10 to 500 10 to 500 RATED POWER Pn W 0.030 0.050 0.125 TEMPERATURE COEFFICIENT ± ppm/°C 100 (50 upon request) 100 (50 upon request) 100 (50 upon request) LIMITING ELEMENT TOLERANCE VOLTAGE ±% V 30 1, 2, 5 37 1, 2, 5 50 1, 2, 5 DIMENSIONS in millimeters (inches) CH02016 F / CH02016 P / CH0402 P / CH0603 P D A CH0402 F / CH0603 F CH0402 N / CH0402 G /CH0603 N / CH0603 G A D D D D C CASE SIZE  MODEL /  TERMINATION CH02016 F CH02016 P CH0402 F CH0402 N CH0402 G D C C G F A E E B B B DIMENSIONS D E when applicable MIN. MAX. 0.110 0.150 (0.004) (0.006) A ± 0.10 (± 0.004) B ± 0.10 (± 0.004) C ± 0.127 (± 0.005) F ± 0.050 (± 0.002) G ± 0.050 (± 0.002) 0.480 (0.020) 0.390 (0.016) 0.420 (0.016) (1) 0.260 (0.010) 0.300 (0.012) 1.000 (0.040) 0.600 (0.023) 0.500 (0.020) 0.150 (0.006) 0.350 (0.014) n/a n/a CH0402 P 1.200 (0.047) 0.600 (0.023) 0.500 (0.020) 0.110 (0.004) 0.150 (0.006) CH0603 F CH0603 N CH0603 G 0.320 (0.013) 0.880 (0.035) 1.520 (0.060) 0.750 (0.030) 0.500 (0.020) 0.250 (0.010) 0.510 (0.020) n/a n/a CH0603 P 1.720 (0.068) 0.750 (0.030) 0.500 (0.020) 0.235 (0.009) 0.275 (0.011) 0.660 (0.026) 1.355 (0.053) Note (1) ± 0.070 (± 0.003) Revision: 30-Sep-2021 Document Number: 53014 1 For technical questions, contact: sferthinfilm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 CH www.vishay.com Vishay Sfernice TOLERANCE VS. OHMIC VALUES Ohmic range 10   R < 50  50  R  500  5% 1 % for 50  and 100 , 2 %, 5 % 2 %, 5 % 1 %, 2 %, 5 % Tolerance CH02016 Tolerance CH0402 and CH0603 LAND PATTERN FOR F “FLIP CHIP” TERMINATIONS in millimeters (inches) Gmin. Xmax. Zmax. CHIP SIZE Zmax. Xmax. Gmin. 02016 0.53 (0.021) 0.44 (0.017) 0.15 (0.006) 0402 1.40 (0.055) 0.65 (0.026) 0.40 (0.016) 0603 1.71 (0.067) 0.90 (0.035) 0.76 (0.030) Note • Suggested land pattern: according to IPC-7351 LAND PATTERN FOR N AND G WRAPAROUND TERMINATIONS in millimeters (inches) X m ax . Gmin. Zmax. CHIP SIZE Zmax. Gmin. Xmax. 0402 1.55 (0.061) 0.15 (0.006) 0.73 (0.029) 0603 2.37 (0.093) 0.35 (0.014) 0.98 (0.039) Dimension and tolerance of land pattern shall be defined by PCB designer; PCB can be designed according to IPC-7351A “Generic Requirements for Surface Mount Design and Land Pattern Standard” PERFORMANCE (CH02016 F TERMINATION) TEST PROCEDURES AND REQUIREMENTS TEST PROCEDURE GLOBAL PERFORMANCES TYPICAL PERFORMANCES (25  TO 250 ) 3 High temperature exposure MIL-STD-202 method 108 1000 h at T = 125 °C, unpowered ± 2 % ± 0.05  ± 0.2 % ± 0.05  4 Temperature cycling JESD22 method JA-104 1000 cycles (-55 °C to +155 °C) ± 1.8 % ± 0.05  ± 1.5 % ± 0.05  7 Biased humidity MIL-STD-202 method 103 1000 h 85 °C / 85 % RH 10 % of operating power ± 2 % ± 0.05  ± 0.75 % ± 0.05  AEC-Q200 CLAUSE Revision: 30-Sep-2021 Document Number: 53014 2 For technical questions, contact: sferthinfilm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 CH www.vishay.com Vishay Sfernice TEST PROCEDURES AND REQUIREMENTS TEST PROCEDURE GLOBAL PERFORMANCES TYPICAL PERFORMANCES (25  TO 250 ) Operational life MIL-STD-202 method 108 Condition D steady state T = 125 °C at rated power 90' on / 30' off / 1000 h ± 2.5 % ± 0.05  ± 1 % ± 0.05  Mechanical shock MIL-STD-202 method 213 condition C 100 g/6 ms 3.75 m/s 3 shock/direction, 2 directions along 3 axes (18 shocks) ± 0.05 % ± 0.05  ± 0.015 % ± 0.05  Vibration MIL-STD-202 method 204 5 g for 20 min, 12 cycles each of 3 orientations Test from 10 Hz to 2000 Hz ± 0.1 % ± 0.05  ± 0.05 % ± 0.05  15 Resistance to soldering heat MIL-STD-202 method 210 condition D Flux used: alpha 611 Solder temp.: 260 °C ± 5 °C Total immersion during 10 s ± 2.5 % ± 0.05  ± 0.5 % ± 0.05  17 ESD AEC-Q200-002 Classification 1C 1000 VDC to 2000 VDC 18 Solderability J-STD-002 - Preconditioning 4 h dry heat aging and 235 °C SnPb 5 s - 215 °C SnPb 5 s - 260 °C SnAgCu 10 s Good tinning ( 95 % covered) No visible damage 20 Flammability UL 94 Class V-0 No burning 21 Board flex AEC-Q200-005 24 Flame retardance AEC-Q200-001 AEC-Q200 CLAUSE 8 13 14 ± 0.1 % ± 0.05  ± 0.05 % ± 0.05  No flame, no explosion, no temperature higher than 350 °C PREFERRED MODELS AND VALUES Vishay Sfernice highly recommend to use the smallest sizes and flip chip version to get the best performances. Recommended Values: 10R/18R/25R/50R/75R/100R/150R/180R/200R/250R/330R /500R Those values are available with a MOQ of 100 pieces. Other values can be ordered upon request, but higher MOQ will apply: 1000 pieces for CH02016, 500 pieces for CH0402, 250 pieces for CH0603. Recommended termination: F Recommended tolerance: 2% DESIGN KITS Design kits are available Ex Stock in CH02016 and CH0402 sizes. There are 20 pieces per recommended value. F termination. 5 % tolerance. Those kits are packaged in pieces of tape and delivered in ESD bags. Revision: 30-Sep-2021 Document Number: 53014 3 For technical questions, contact: sferthinfilm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 CH www.vishay.com Vishay Sfernice PACKAGING Standard packaging is plastic tape and reel for all sizes. Paper tape and reel is available for sizes 0402 and 0603. Waffle pack is available for all sizes. Depending on the type of terminations, parts will be packed differently: One face: • Gold terminations: (P termination option): Active face up. Please use M termination code for active face down in tape and reel. • Tin / silver terminations: (F termination option): Active face down in tape and reel. Active face up in waffle pack. Note • Please refer to Vishay Sfernice Application Note “Guidelines for Vishay Sfernice Resistive and Inductive Products” for soldering recommendation (document number 52029, 3. Guidelines for Surface Mounting Components (SMD), profile number 3 applies NUMBER OF PIECES PER PACKAGE SIZE MOQ 02016 0603 TAPE WIDTH MIN. MAX. 100 5000 484 See MOQ mentioned on preferred models and values 0402 TAPE AND REEL WAFFLE PACK 2" x 2" 100 8 mm 100 PACKAGING RULES Tape and Reel See Part Numbering information to get the quantity desired by tape. In regard to the CH02016 size only, up to 5 empty cavities can be found every 1000 parts in the reel. Nevertheless, the number of requested parts will be respected. Waffle Pack Can be filled up to maximum quantity indicated in the table here above, taking into account the minimum order quantity. When quantity ordered exceeds maximum quantity of a single waffle pack, the waffle packs are stacked up on the top of each other and closed by one single cover. To get “not stacked up” waffle pack in case of ordered quantity > maximum number of pieces per package: please consult Vishay Sfernice for specific ordering code. GLOBAL PART NUMBER INFORMATION New Global Part Numbering: CH0402-50RJF (preferred part number format) C H 0 4 0 2 - 5 0 R J F T 9 9 9 GLOBAL MODEL SIZE OHMIC VALUE TOLERANCE TERMINATION PACKAGING OPTION CH 02016 0402 0603 10R to 500R F=1% G=2% J=5% F (flip chip): SnAg over nickel barrier N (W/A): SnAg over nickel barrier (except 02016) P (one face): (1) gold bonding pads G (W/A): gold over nickel barrier (except 02016) For more information see Codification of Packaging table From 1 to 3 digits. Leave blank if no option. Historical Part Number example: CH02016-100RGFPT1K (tapes of 1K pieces) CH0402-50RJF (waffle pack) CHKIT Part Numbers (2): CHKIT-02016 CHKIT-0402 Notes • Historical part numbers are not recommended but can still be used for ordering (1) Gold termination for application in hermetic package. Can also be mounted on PCB with SnAg solder paste. Please use M termination code for active face down in tape and reel (2) CHKIT for 0603 size is not available Revision: 30-Sep-2021 Document Number: 53014 4 For technical questions, contact: sferthinfilm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 CH www.vishay.com Vishay Sfernice CODIFICATION OF PACKAGING WAFFLE PACK (available for all sizes) W 100 min., 1 mult. PLASTIC TAPE (standard packaging for all sizes) T 100 min., 1 mult. TA 100 min., 100 mult. TB 250 min., 250 mult. TC 500 min., 500 mult. TD 1000 min., 1000 mult. TF Full tape (quantity depending on size of chips) PAPER TAPE (available for 0402 and 0603) PT 100 min., 1 mult. PA 100 min., 100 mult. PB 250 min., 250 mult. PC 500 min., 500 mult. TYPICAL HIGH FREQUENCY PERFORMANCE ELECTRICAL MODEL Z C Z0 Z0 Cg Lc Cg Lc L R C Internal shunt capacitance L Internal inductance R Resistance Z Internal impedance (R, L, C) Lc External connection inductance Cg External capacitance to ground The complex impedance of the chip resistor is given by the following equations: 2 2 2 R + j  L – R C – L C  Z = ------------------------------------------------------------------------------------2 2 2 4 1 + C   R C – 2L  + L C  Z 1 -------- = ------------------------------------------------------------------------------------------ x 2 2 2 4 R 1 + C   R C – 2L  + L C  2 Notes • =2xxf • f: frequency 2 2 2   L – R C – L C  1 + -----------------------------------------------------------R 2 2 2 – 1   L – R C – L C   = tan -----------------------------------------------------------R R, L and C are relevant to the chip resistor itself. Lc and Cg also depend on the way the chip resistor is mounted. It is important to notice that after assembly the external reactance of Lc and Cg will be combined to internal reactance of L and C. This combination can upgrade or downgrade the HF behavior of the component. This is why we are displaying three sets of data: Z • -------- versus frequency curves which aim to show at a glance the intrinsic HF performance of a given chip resistor R  Z total  • ------------------- versus frequency curves which aim to show the behavior of the chip resistor when mounted R Revision: 30-Sep-2021 Document Number: 53014 5 For technical questions, contact: sferthinfilm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 CH www.vishay.com Vishay Sfernice These lines are terminated with adapted source and load impedance respectively Zs and Zl with Z0 = ZL = Zs (for others configurations please consult us). Equivalent circuit for S-parameters: Z total C ZS G Z0 Z0 Cg Lc Lc L Cg ZL R S-parameters are computed taking into account all the resistive, inductive and capacitive elements (Z total) and Z0 = ZL = Zs = R. For simulation purposes, those S-parameter data are available for download here: www.vishay.com/doc?53061 INTERNAL IMPEDANCE CURVES Axis Title 1.1 1.0 0.9 0.8 1000 150 Ω 0.7 1st line 2nd line 2nd line |Z|/R 10000 10 Ω 25 Ω 50 Ω 75 Ω 100 Ω 200 Ω 0.6 250 Ω 0.5 100 0.4 0.3 500 Ω 0.2 10 0.1 0.1 1 10 100 f (GHz) Internal impedance curve for 02016 size (F and P terminations) Axis Title 10 Ω 10000 25 Ω 1.0 50 Ω 0.9 75 Ω 0.8 100 Ω 0.7 1000 1st line 2nd line 2nd line |Z|/R 1.1 150 Ω 0.6 200 Ω 0.5 250 Ω 0.4 100 0.3 500 Ω 0.2 10 0.1 0.1 1 10 100 f (GHz) Internal impedance curve for 0402 size (F and P terminations) Revision: 30-Sep-2021 Document Number: 53014 6 For technical questions, contact: sferthinfilm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 CH www.vishay.com Vishay Sfernice INTERNAL IMPEDANCE CURVES Axis Title 1.1 10 Ω 25 Ω 50 Ω 10000 75 Ω 1.0 0.9 100 Ω 1000 0.7 1st line 2nd line 2nd line |Z|/R 0.8 0.6 0.5 150 Ω 0.4 200 Ω 0.3 250 Ω 100 0.2 500 Ω 10 0.1 0.1 1 10 100 f (GHz) Internal impedance curve for 0402 size (N and G terminations) Axis Title 10 Ω 25 Ω 1.1 10000 1.0 50 Ω 0.9 75 Ω 1000 0.7 1st line 2nd line 2nd line |Z|/R 0.8 100 Ω 0.6 0.5 150 Ω 0.4 100 200 Ω 250 Ω 0.3 0.2 500 Ω 10 0.1 0.1 1 10 100 f (GHz) Internal impedance curve for 0603 size (F and P terminations) Axis Title 10 Ω 1.1 25 Ω 50 Ω 1.0 10000 75 Ω 0.9 1000 0.7 100 Ω 1st line 2nd line 2nd line |Z|/R 0.8 0.6 0.5 150 Ω 0.4 100 200 Ω 250 Ω 0.3 0.2 500 Ω 10 0.1 0.1 1 10 100 f (GHz) Internal impedance curve for 0603 size (N and G terminations) Revision: 30-Sep-2021 Document Number: 53014 7 For technical questions, contact: sferthinfilm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 CH www.vishay.com Vishay Sfernice INTERNAL IMPEDANCE CURVES (|ZTOTAL| / R) Axis Title 10 Ω 1.1 25 Ω 0.9 0.8 0.7 1000 1st line 2nd line 2nd line |Ztotal|/R 10000 500 Ω 250 Ω 200 Ω 150 Ω 50 Ω 100 Ω 75 Ω 1.0 0.6 0.5 100 0.4 0.3 0.2 10 0.1 0.1 1 10 100 f (GHz) Internal impedance curve for 02016 size (F and P terminations) 10Axis Ω Title 1.1 25 Ω 50 Ω 1.0 0.9 0.8 1000 75 Ω 100 Ω 0.7 1st line 2nd line 2nd line |Ztotal|/R 10000 500 Ω 250 Ω 200 Ω 150 Ω 0.6 0.5 100 0.4 0.3 0.2 10 0.1 0.1 1 10 100 f (GHz) Internal impedance curve for 0402 size (F and P terminations) 10 Ω 1.1 Axis Title 25 Ω 50 Ω 1.0 500 Ω 250 Ω 200 Ω 150 Ω 75 Ω 100 Ω 0.8 0.7 1000 1st line 2nd line 0.9 2nd line |Ztotal|/R 10000 0.6 0.5 100 0.4 0.3 0.2 10 0.1 0.1 1 10 100 f (GHz) Internal impedance curve for 0402 size (N and G terminations) Revision: 30-Sep-2021 Document Number: 53014 8 For technical questions, contact: sferthinfilm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 CH www.vishay.com Vishay Sfernice INTERNAL IMPEDANCE CURVES (|ZTOTAL| / R) Axis Title 25 Ω 10 Ω 1.1 50 Ω 10000 1.0 500 Ω 250 Ω 200 Ω 150 Ω 75 Ω 2nd line |Ztotal|/R 0.8 0.7 1000 1st line 2nd line 0.9 100 Ω 0.6 0.5 100 0.4 0.3 0.2 10 0.1 0.1 1 10 100 f (GHz) Internal impedance curve for 0603 size (F and P terminations) 25Axis Ω Title 10 Ω 1.1 50 Ω 75 Ω 10000 1.0 100 Ω 0.9 1000 0.7 150 Ω 0.6 200 Ω 250 Ω 500 Ω 0.5 1st line 2nd line 2nd line |Ztotal|/R 0.8 100 0.4 0.3 0.2 10 0.1 0.1 1 10 100 f (GHz) Internal impedance curve for 0603 size (N and G terminations) S-PARAMETER CH02016 (F and P Terminations) Axis Title Axis Title 10000 -2 S21 -3 S21 -3 -4 1st line 2nd line -5 -6 -7 100 -8 1000 -5 1st line 2nd line 1000 2nd line Magnitude (dB) -4 2nd line Magnitude (dB) 10000 -2 -6 -7 100 -8 -9 -9 S11 10 -10 0.1 1 10 100 S11 10 -10 0.1 1 10 100 f (GHz) f (GHz) CH02016 flip chip (Z0 = ZI = Zs = R = 50 ) CH02016 flip chip (Z0 = ZI = Zs = R = 100 ) Revision: 30-Sep-2021 Document Number: 53014 9 For technical questions, contact: sferthinfilm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 CH www.vishay.com Vishay Sfernice S-PARAMETER CH0402 (F and P Terminations) Axis Title Axis Title 10000 -2 -3 -3 S21 S21 -4 1st line 2nd line -5 -6 -7 100 -8 1000 -5 1st line 2nd line 1000 2nd line Magnitude (dB) -4 2nd line Magnitude (dB) 10000 -2 -6 -7 100 -8 -9 -9 S11 10 -10 0.1 1 10 S11 10 -10 100 0.1 1 10 100 f (GHz) f (GHz) CH0402 flip chip (Z0 = ZI = Zs = R = 50 ) CH0402 flip chip (Z0 = ZI = Zs = R = 100 ) CH0402 (N and G Terminations) Axis Title Axis Title 10000 -2 -3 -3 S21 S21 -4 1st line 2nd line -5 -6 -7 100 -8 1000 -5 1st line 2nd line 1000 2nd line Magnitude (dB) -4 2nd line Magnitude (dB) 10000 -2 -6 -7 100 -8 -9 -9 S11 10 -10 0.1 1 10 S11 10 -10 100 0.1 1 10 100 f (GHz) f (GHz) CH0402 wraparound (Z0 = ZI = Zs = R = 50 ) CH0402 wraparound (Z0 = ZI = Zs = R = 100 ) CH0603 (F and P Terminations) Axis Title Axis Title 10000 -2 -3 -3 S21 S21 -4 1st line 2nd line -5 -6 -7 100 -8 1000 -5 1st line 2nd line 1000 2nd line Magnitude (dB) -4 2nd line Magnitude (dB) 10000 -2 -6 -7 100 -8 -9 -9 S11 10 -10 0.1 1 10 100 S11 10 -10 0.1 1 10 100 f (GHz) f (GHz) CH0603 flip chip (Z0 = ZI = Zs = R = 50 ) CH0603 flip chip (Z0 = ZI = Zs = R = 100 ) Revision: 30-Sep-2021 Document Number: 53014 10 For technical questions, contact: sferthinfilm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 CH www.vishay.com Vishay Sfernice S-PARAMETER CH0603 (N and G Terminations) Axis Title Axis Title 10000 -2 -3 -3 S21 S21 -4 1st line 2nd line -5 -6 -7 100 -8 1000 -5 1st line 2nd line 1000 2nd line Magnitude (dB) -4 2nd line Magnitude (dB) 10000 -2 -6 -7 100 -8 -9 -9 S11 10 -10 0.1 1 10 100 S11 10 -10 0.1 1 10 100 f (GHz) f (GHz) CH0603 wraparound (Z0 = ZI = Zs = R = 50 ) CH0603 wraparound (Z0 = ZI = Zs = R = 100 ) Revision: 30-Sep-2021 Document Number: 53014 11 For technical questions, contact: sferthinfilm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. 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Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the Vishay product could result in personal injury or death. Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners. © 2021 VISHAY INTERTECHNOLOGY, INC. ALL RIGHTS RESERVED Revision: 09-Jul-2021 1 Document Number: 91000