DG221BDY

DG221B Vishay Siliconix Quad SPST CMOS Analog Switch with Latches DESCRIPTION FEATURES The DG221B is a monolithic quad single-pole, single-throw analog switch designed for precision switching applications in communication, instrumentation and process control systems. Featuring independent onboard latches and a common WR pin, each DG221B can be memory mapped, and addressed as a single data byte for simultaneous switching. The DG221B combines low power and low on-resistance (60 typical) while handling continuous currents up to 20 mA. An epitaxial layer prevents latchup. The device features true bidirectional performance in the on condition. • Accepts 150 ns write pulse width • 5 V on-chip regulator Pb-free Available • Latches are transparent with WR low RoHS* • Low on-resistance: 60 W COMPLIANT BENEFITS • Compatible with most µP buses • Allows wide power supply tolerance without affecting TTL compatibility • Reduced power consumption • Allows flexibility of design APPLICATIONS • µP based systems • Automatic test equipment • Communication systems • Data acquisition systems • Medical instrumentation • Factory automation FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION Four latchable SPST switches per package Dual-In-Line and SOIC TRUTH TABLE IN1 1 D1 2 3 Input Latch S1 16 IN2 INX 15 D2 0 0 ON 1 0 OFF 14 S2 13 V+ 12 WR V- 4 GND 5 S4 6 11 S3 D4 7 10 D3 IN4 8 9 IN3 WR Control data latched-in, switches on or off as selected by last INX X X Switch 1 Maintains previous state Logic "0" ≤ 0.8 V Logic "1" ≥ 2.4 V Top View * Pb containing terminations are not RoHS compliant, exemptions may apply. Document Number: 71616 S-80263-Rev. B, 11-Feb-08 www.vishay.com 1 DG221B Vishay Siliconix ORDERING INFORMATION Temp. Range - 40 °C to 85 °C Package Standard Part Number Lead (Pb)-free Part Number 16-Pin Plastic DIP DG221BDJ DG221BDJ-E3 16-Pin Narrow SOIC DG221BDY DG221BDY-T1 DG221BDY-E3 DG221BDY-T1-E3 ABSOLUTE MAXIMUM RATINGS Parameter Limit Voltages Referenced V+ to VGND 25 (V-) - 2 to (V+) + 2 or 20 mA, whichever occurs first 30 a Digital Inputs , VS, VD Continuous Current (Any Terminal) Continuous Current, S or D 20 Peak Current, S or D (Pulsed at 1 ms, 10 % duty cycle max.) 70 Storage Temperature Power Dissipation (Package)b Unit 34 (DJ and DY Suffix) - 65 to 125 16-Pin Plastic DIPc 470 16-Pin SOICd 600 V mA °C mW Notes: a. Signals on SX, DX, or INX exceeding V+ or V- will be clamped by internal diodes. Limit forward diode current to maximum current ratings. b. All leads welded or soldered to PC board. c. Derate 6.5 mW/°C above 25 °C. d. Derate 7.7 mW/°C above 75 °C. SCHEMATIC DIAGRAM Typical Channel V+ 5V Reg S GND INX V- + Latch VV+ WR Level Shift/ Drive V+ + D V- Figure 1. www.vishay.com 2 Document Number: 71616 S-80263-Rev. B, 11-Feb-08 DG221B Vishay Siliconix SPECIFICATIONSa Parameter Test Conditions Unless Otherwise Specified V+ = 15 V, V- = - 15 V VIN = 2.4 V, 0.8 Vf, WR = 0 Temp.b Min.d VANALOG Full - 15 rDS(on) IS = - 10 mA, VD = ± 10 V Room Full Symbol Limits - 40 °C to 85 °C Typ.c Max.d Unit 15 V 60 90 135 Ω Analog Switch Analog Signal Rangee Drain-Source On-Resistance Source Off Leakage Current IS(off) VS = ± 14 V, VD = ± 14 V Room Full -5 - 100 ± 0.01 5 100 Room Full -5 - 100 ± 0.02 5 100 Drain Off Leakage Current ID(off) Drain On Leakage Current ID(on) VS = VD = ± 14 V Room Full -5 - 200 ± 0.01 5 200 IINL, IINH VIN = 0 V or = 2.4 V Room Full -1 - 10 - 0.0004 1 10 nA Digital Control Input Current µA Dynamic Characteristics Turn-On Time Turn-Off Time tON tOFF Turn-On Time Write tON, WR Turn-Off Time Write tOFF, WR Write Pulse Width tW Input Setup Time tS Input Hold Time tH Charge Injection Q Source-Off Capacitance CS(off) Drain-Off Capacitance CD(off) Channel On Capacitance CD(on) Off-Isolation OIRR Interchannel Crosstalk XTALK See Figure 2 See Figure 3 Room 550 Room 340 Room 550 Room 340 Room 150 120 See Figure 4 Room 180 130 Room 20 18 CL = 1000 pF, Vgen = 0 V, Rgen = 0 Ω Room 20 Room 8 f = 1 MHz, VS, VD = 0 V Room 9 Room 29 VS = 1 Vp-p, f = 100 kHz CL = 15 pF, RL = 1 kΩ Room 70 Room 90 All Channels On or Off VIN = 0 V or 2.4 V Room ns pC pF dB Power Supplies Positive Supply Current I+ Negative Supply Current I– Full 0.8 -1 1.5 - 0.4 mA Notes: a. Refer to PROCESS OPTION FLOWCHART. b. Room = 25 °C, Full = as determined by the operating temperature suffix. c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. e. Guaranteed by design, not subject to production test. f. VIN = input voltage to perform proper function. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Document Number: 71616 S-80263-Rev. B, 11-Feb-08 www.vishay.com 3 DG221B Vishay Siliconix TEST CIRCUITS + 15 V V+ 2V S D WR 50 % RL 1 kΩ V- Switch Input CL 35 pF tr < 10 ns tf < 10 ns 0V VO IN GND 3V Logic Input VS 90 % Switch Output VO tON - 15 V tOFF CL (includes fixture and stray capacitance) RL VO = V S RL + rDS(on) Figure 2. Switching Time + 15 V 3V 0V WR 2V WR 50 % 0V V+ S D 3V IN VO tr < 10 ns tf < 10 ns 0V IN GND RL 1 kΩ V- CL 35 pF VS VOUT 90 % VO - 15 V tON, WR tOFF , WR CL (includes fixture and stray capacitance) RL VO = V S RL + rDS(on) Figure 3. WR Switching Time 3V 50 % IN tS tH tS tH 3V 50 % WR tW tH = Hold Time tS = Setup Time tW = WR Pulse Width VOUT Figure 4. WR Setup Conditions www.vishay.com 4 Document Number: 71616 S-80263-Rev. B, 11-Feb-08 DG221B Vishay Siliconix TEST CIRCUITS + 15 V ΔVO V+ Rg S Vg VO D VO CL 1000 pF IN 3V OFF INX V- WR ON OFF ΔVO = measured voltage error due to charge injection The charge injection in coulombs is Q = CL x ΔV O - 15 V Figure 5. Charge Injection + 15 V C + 15 V V+ C Rg = 50 Ω V+ S VS D IN S2 NC V- D2 C GND WR - 15 V Off Isolation = 20 log VO RL IN2 0V WR 50 Ω 0V RL GND D1 IN1 VO Rg = 50 Ω 2.4 V S1 VS V- C - 15 V VS XTA LK Isolation = 20 log VO C = RF bypass VS VO C = RF bypass Figure 7. Channel-to-Channel Crosstalk Figure 6. Off Isolation APPLICATION HINTSa WR (V) VIN Logic Input Voltage VINH(min)/VINL(max) (V) VS or VD Analog Voltage Range (V) 0 2.4/0.8 2.4/0.8 - 15 to 15 0 2.4/0.8 2.4/0.8 - 10 to 10 0 2.4/0.8 2.4/0.8 - 5 to 10 V+ Positive Supply Voltage (V) VNegative Supply Voltage (V) GND (V) 15 - 15 10 - 10 10 -5 Notes: a. Application hints are for DESIGN AID ONLY, not guaranteed and not subject to production testing. Document Number: 71616 S-80263-Rev. B, 11-Feb-08 www.vishay.com 5 DG221B Vishay Siliconix APPLICATIONS VIN + 15 V V+ 9 MΩ S1 DG221B IN1 D C 900 kΩ Q D1 S2 IN2 D C 90 kΩ Q D2 Data Bus S3 IN3 D C Q 9 kΩ D3 S4 IN4 D C WR 1 kΩ Q D4 WR V- GND CS Address Decoder Address Bus + TL081 - - 15 V The TL081 is used as an output buffer while the voltage divider provides attenuation. VO Figure 7. µP-Controlled Analog Signal Attenuator TRUTH TABLE OUTPUT ATTENUATION FOR FIGURE 7 ON SWITCH WR IN1 IN2 IN3 IN4 0 All 0 0 1 1 1 0.1 0 None 0 1 0 1 1 0.01 1 0 1 0 1 1 0 1 0.001 1 0 2 0 1 1 1 0 0.0001 0 1 0 3 1 0 0 4 IN1 IN2 IN3 IN4 WRa 0 0 0 0 1 1 1 1 0 1 1 1 0 1 1 1 1 1 Gain Notes: a. WR may be held at "0" for temporary operation similar to DG201A/DG201B. With WR at “0” SW1 will remain on as long as IN1 is held at "0" V. Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see http://www.vishay.com/ppg?71616. www.vishay.com 6 Document Number: 71616 S-80263-Rev. B, 11-Feb-08 Package Information Vishay Siliconix SOIC (NARROW): 16ĆLEAD JEDEC Part Number: MS-012 MILLIMETERS 16 15 14 13 12 11 10 Dim A A1 B C D E e H L Ĭ 9 E 1 2 3 4 5 6 7 8 INCHES Min Max Min Max 1.35 1.75 0.053 0.069 0.10 0.20 0.004 0.008 0.38 0.51 0.015 0.020 0.18 0.23 0.007 0.009 9.80 10.00 0.385 0.393 3.80 4.00 0.149 0.157 1.27 BSC 0.050 BSC 5.80 6.20 0.228 0.244 0.50 0.93 0.020 0.037 0_ 8_ 0_ 8_ ECN: S-03946—Rev. F, 09-Jul-01 DWG: 5300 H D C All Leads e Document Number: 71194 02-Jul-01 B A1 L Ĭ 0.101 mm 0.004 IN www.vishay.com 1 Package Information Vishay Siliconix PDIP: 16ĆLEAD 16 15 14 13 12 11 10 9 E E1 1 2 3 4 5 6 7 8 D S Q1 A A1 L 15° MAX C B1 e1 Dim A A1 B B1 C D E E1 e1 eA L Q1 S B eA MILLIMETERS Min Max INCHES Min Max 3.81 5.08 0.150 0.200 0.38 1.27 0.015 0.050 0.38 0.51 0.015 0.020 0.89 1.65 0.035 0.065 0.20 0.30 0.008 0.012 18.93 21.33 0.745 0.840 7.62 8.26 0.300 0.325 5.59 7.11 0.220 0.280 2.29 2.79 0.090 0.110 7.37 7.87 0.290 0.310 2.79 3.81 0.110 0.150 1.27 2.03 0.050 0.080 0.38 1.52 .015 0.060 ECN: S-03946—Rev. D, 09-Jul-01 DWG: 5482 Document Number: 71261 06-Jul-01 www.vishay.com 1 Application Note 826 Vishay Siliconix RECOMMENDED MINIMUM PADS FOR SO-16 RECOMMENDED MINIMUM PADS FOR SO-16 0.372 (9.449) 0.152 0.022 0.050 0.028 (0.559) (1.270) (0.711) (3.861) 0.246 (6.248) 0.047 (1.194) Recommended Minimum Pads Dimensions in Inches/(mm) Return to Index APPLICATION NOTE Return to Index www.vishay.com 24 Document Number: 72608 Revision: 21-Jan-08 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer  ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. 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Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners. © 2017 VISHAY INTERTECHNOLOGY, INC. ALL RIGHTS RESERVED Revision: 08-Feb-17 1 Document Number: 91000