IRF730AS, SiHF730AS, IRF730AL, SiHF730AL
www.vishay.com
Vishay Siliconix
Power MOSFET
G
G
D
S
FEATURES
D
D2PAK (TO-263)
I2PAK (TO-262)
• Low gate charge Qg results in simple drive
requirement
Available
• Improved gate, avalanche and dynamic dV/dt
ruggedness
Available
• Fully
characterized
capacitance
and
avalanche voltage and current
• Effective Coss specified
• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
G
D
S
S
N-Channel MOSFET
Note
* This datasheet provides information about parts that are
RoHS-compliant and / or parts that are non RoHS-compliant. For
example, parts with lead (Pb) terminations are not RoHS-compliant.
Please see the information / tables in this datasheet for details
PRODUCT SUMMARY
VDS (V)
RDS(on) max. (Ω)
400
VGS = 10 V
1.0
Qg max. (nC)
22
Qgs (nC)
5.8
Qgd (nC)
APPLICATIONS
• Switch mode power supply (SMPS)
• Uninterruptible power supply
• High speed power switching
9.3
Configuration
Single
TYPICAL SMPS TOPOLOGIES
• Single transistor flyback Xfmr. reset
• Single transistor forward Xfmr. reset (both US line input
only)
ORDERING INFORMATION
Package
D2PAK (TO-263)
D2PAK (TO-263)
D2PAK (TO-263)
I2PAK (TO-262)
Lead (Pb)-free and halogen-free
SiHF730AS-GE3
SiHF730ASTRL-GE3 a
SiHF730ASTRR-GE3 a
SiHF730AL-GE3
IRF730ASPbF
IRF730ASTRLPbF a
-
-
Lead (Pb)-free
Note
a. See device orientation.
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
LIMIT
Drain-source voltage
VDS
400
Gate-source voltage
VGS
± 30
Continuous drain current
VGS at 10 V
TC = 25 °C
TC = 100 °C
Pulsed drain current a, e
ID
UNIT
V
5.5
3.5
A
IDM
22
0.6
W/°C
Single pulse avalanche energy b, e
EAS
290
mJ
Avalanche current a
IAR
5.5
A
Repetiitive avalanche energy a
EAR
7.4
mJ
Linear derating factor
Maximum power dissipation
TC = 25 °C
Peak diode recovery dV/dt c, e
Operating junction and storage temperature range
Soldering recommendations (peak temperature) d
for 10 s
PD
74
W
dV/dt
4.6
V/ns
TJ, Tstg
-55 to +150
300
°C
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11)
b. Starting TJ = 25 °C, L = 19 mH, Rg = 25 Ω, IAS = 5.5 A (see fig. 12)
c. ISD ≤ 5.5 A, dI/dt ≤ 90 A/μs, VDD ≤ VDS, TJ ≤ 150 °C
d. 1.6 mm from case
e. Uses IRF730A, SiHF730A data and test conditions
S21-0901-Rev. D, 30-Aug-2021
Document Number: 91046
1
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ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
TYP.
MAX.
Maximum junction-to-ambient
(PCB mounted, steady-state) a
RthJA
-
40
Maximum junction-to-case (drain)
RthJC
-
1.7
UNIT
°C/W
Note
a. When mounted on 1" square PCB (FR-4 or G-10 material)
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-source breakdown voltage
VDS temperature coefficient
Gate-source threshold voltage
VDS
VGS = 0, ID = 250 μA
400
-
-
V
ΔVDS/TJ
Reference to 25 °C, ID = 1 mA d
-
0.5
-
V/°C
VGS(th)
VDS = VGS, ID = 250 μA
2.0
-
4.5
V
Gate-Source Leakage
IGSS
VGS = ± 30 V
-
-
± 100
nA
Zero Gate Voltage Drain Current
IDSS
VDS = 400 V, VGS = 0 V
-
-
25
VDS = 320 V, VGS = 0 V, TJ = 125 °C
-
-
250
Drain-Source On-State Resistance
Forward Transconductance
μA
-
-
1.0
Ω
gfs
VDS = 50 V, ID = 3.3 A d
3.1
-
-
S
VGS = 0 V,
VDS = 25 V,
f = 1.0 MHz, see fig. 5d
-
600
-
-
103
-
-
4.0
-
RDS(on)
ID = 3.3 A b
VGS = 10 V
Dynamic
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
Output Capacitance
Coss
Effective Output Capacitance
Total Gate Charge
Coss eff.
Qg
Gate-Source Charge
Qgs
Gate-Drain Charge
Qgd
Turn-On Delay Time
td(on)
Rise Time
Turn-Off Delay Time
VGS = 0 V
tr
td(off)
Fall Time
tf
Gate Input Resistance
Rg
VGS = 10 V
VDS = 1.0 V, f = 1.0 MHz
-
890
VDS = 320 V, f = 1.0 MHz
-
30
-
VDS = 0 V to 320 V c, d
-
45
-
-
-
22
ID = 3.5 A, VDS = 320 V,
see fig. 6 and 13 b, d
-
-
5.8
-
-
9.3
-
10
-
VDD = 200 V, ID = 3.5 A,
Rg = 12 Ω, RD = 57 Ω, see fig. 10 b, d
-
22
-
-
20
-
-
16
-
f = 1 MHz, open drain
2.7
-
10.9
-
-
5.5
-
-
22
pF
nC
ns
Ω
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
IS
Pulsed Diode Forward Current a
ISM
Body Diode Voltage
VSD
Body Diode Reverse Recovery Time
trr
Body Diode Reverse Recovery Charge
Qrr
Forward Turn-On Time
ton
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
A
G
S
TJ = 25 °C, IS = 5.5 A, VGS = 0 V b
TJ = 25 °C, IF = 3.5 A, dI/dt = 100 A/μs b, d
-
-
1.6
V
-
370
550
ns
-
1.6
2.4
μC
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width ≤ 300 μs; duty cycle ≤ 2 %.
c. Coss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 % to 80 % VDS.
d. Uses IRF730A, SiHF730A data and test conditions.
S21-0901-Rev. D, 30-Aug-2021
Document Number: 91046
2
For technical questions, contact: hvm@vishay.com
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ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRF730AS, SiHF730AS, IRF730AL, SiHF730AL
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Vishay Siliconix
ID, Drain-to-Source Current (A)
102
VGS
15 V
10 V
8.0 V
10
7.0 V
6.0 V
5.5 V
5.0 V
Bottom 4.5 V
1
Top
0.1
4.5 V
20 µs Pulse Width
TC = 25 °C
10-2
0.1
1
102
10
VDS, Drain-to-Source Voltage (V)
91046_01
RDS(on), Drain-to-Source On Resistance
(Normalized)
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
C, Capacitance (pF)
ID, Drain-to-Source Current (A)
4.5 V
0.1
0.5
0.0
- 60 - 40 - 20 0
20 40 60 80 100 120 140 160
TJ, Junction Temperature (°C)
VGS = 0 V, f = 1 MHz
Ciss = Cgs + Cgd, Cds Shorted
Crss = Cgd
Coss = Cds + Cgd
104
103
Ciss
102
Coss
Crss
1
102
10
1
VDS, Drain-to-Source Voltage (V)
1
VDS, Drain-to-Source Voltage (V)
20
TJ = 25 °C
20 µs Pulse Width
VDS = 50 V
5.0
6.0
7.0
8.0
9.0
VGS, Gate-to-Source Voltage (V)
Fig. 3 - Typical Transfer Characteristics
S21-0901-Rev. D, 30-Aug-2021
VGS, Gate-to-Source Voltage (V)
TJ = 150 °C
0.1
103
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
102
1
102
10
91046_05
Fig. 2 - Typical Output Characteristics
ID, Drain-to-Source Current (A)
1.0
10
20 µs Pulse Width
TC = 150 °C
10-2
0.1
91046_03
1.5
105
VGS
Top
15 V
10 V
8.0 V
10
7.0 V
6.0 V
5.5 V
5.0 V
1
Bottom 4.5 V
4.0
2.0
Fig. 4 - Normalized On-Resistance vs. Temperature
102
10
ID = 5.5 A
VGS = 10 V
91046_04
Fig. 1 - Typical Output Characteristics
91046_02
2.5
ID = 5.5 A
VDS = 320 V
16
VDS = 200 V
VDS = 80 V
12
8
4
For test circuit
see figure 13
0
0
10.0
91046_06
5
10
15
20
25
QG, Total Gate Charge (nC)
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
Document Number: 91046
3
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRF730AS, SiHF730AS, IRF730AL, SiHF730AL
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Vishay Siliconix
6.0
5.0
ID, Drain Current (A)
ISD, Reverse Drain Current (A)
102
TJ = 150 °C
10
TJ = 25 °C
1
3.0
2.0
1.0
VGS = 0 V
0.1
0.4
0.6
0.8
0.0
25
1.2
1.0
VSD, Source-to-Drain Voltage (V)
91046_07
102
50
75
100
125
150
TC, Case Temperature (°C)
91046_09
Fig. 7 - Typical Source-Drain Diode Forward Voltage
ID, Drain Current (A)
4.0
Fig. 9 - Maximum Drain Current vs. Case Temperature
RD
VDS
Operation in this area limited
by RDS(on)
VGS
D.U.T.
Rg
10 µs
+
- VDD
10
100 µs
10 V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
1 ms
1
Fig. 10a - Switching Time Test Circuit
10 ms
TC = 25 °C
TJ = 150 °C
Single Pulse
0.1
VDS
102
10
90 %
103
VDS, Drain-to-Source Voltage (V)
91046_08
Fig. 8 - Maximum Safe Operating Area
10 %
VGS
td(on)
td(off) tf
tr
Fig. 10b - Switching Time Waveforms
Thermal Response (ZthJC)
10
1
D = 0.5
0.2
0.1
PDM
0.1
0.05
0.02
0.01
t1
t2
Notes:
1. Duty Factor, D = t1/t2
2. Peak Tj = PDM x ZthJC + TC
Single Pulse
(Thermal Response)
10-2
10-5
91046_11
S21-0901-Rev. D, 30-Aug-2021
10-4
10-3
10-2
0.1
1
t1, Rectangular Pulse Duration (s)
Document Number: 91046
4
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THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRF730AS, SiHF730AS, IRF730AL, SiHF730AL
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Vishay Siliconix
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
610
Driver
L
VDS
D.U.T
Rg
+
A
- VDD
IAS
20 V
VDSav, Avalanche Voltage (V)
15 V
0.01 Ω
tp
Fig. 12a - Unclamped Inductive Test Circuit
600
590
580
570
560
550
540
0.0
VDS
5.0
4.0
6.0
Fig. 12d - Typical Drain-to-Source Voltage vs.
Avalanche Current
QG
10 V
IAS
QGS
Fig. 12b - Unclamped Inductive Waveforms
EAS, Single Pulse Avalanche Energy (mJ)
3.0
IAV, Avalanche Current (A)
91046_12d
tp
2.0
1.0
QGD
VG
700
ID
Top
2.5 A
3.5 A
Bottom 5.5 A
600
500
Charge
Fig. 13a - Maximum Avalanche Energy vs. Drain Current
400
Current regulator
Same type as D.U.T.
300
200
50 kΩ
100
91046_12c
12 V
0.2 µF
0.3 µF
0
+
25
50
75
100
125
150
D.U.T.
-
VDS
Starting TJ, Junction Temperature (°C)
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
VGS
3 mA
IG
ID
Current sampling resistors
Fig. 13b - Gate Charge Test Circuit
S21-0901-Rev. D, 30-Aug-2021
Document Number: 91046
5
For technical questions, contact: hvm@vishay.com
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ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRF730AS, SiHF730AS, IRF730AL, SiHF730AL
www.vishay.com
Vishay Siliconix
Peak Diode Recovery dV/dt Test Circuit
+
D.U.T.
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
-
-
Rg
•
•
•
•
+
dV/dt controlled by Rg
Driver same type as D.U.T.
ISD controlled by duty factor “D”
D.U.T. - device under test
+
-
VDD
Driver gate drive
P.W.
Period
D=
P.W.
Period
VGS = 10 Va
D.U.T. lSD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
Inductor current
VDD
Body diode forward drop
Ripple ≤ 5 %
ISD
Note
a. VGS = 5 V for logic level devices
Fig. 14 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91046.
S21-0901-Rev. D, 30-Aug-2021
Document Number: 91046
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ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
Vishay Siliconix
TO-263AB (HIGH VOLTAGE)
A
(Datum A)
3
A
4
4
L1
B
A
E
c2
H
Gauge
plane
4
0° to 8°
5
D
B
Detail A
Seating plane
H
1
2
C
3
C
L
L3
L4
Detail “A”
Rotated 90° CW
scale 8:1
L2
B
A1
B
A
2 x b2
c
2xb
E
0.010 M A M B
± 0.004 M B
2xe
Plating
5
b1, b3
Base
metal
c1
(c)
D1
4
5
(b, b2)
Lead tip
MILLIMETERS
DIM.
MIN.
MAX.
View A - A
INCHES
MIN.
4
E1
Section B - B and C - C
Scale: none
MILLIMETERS
MAX.
DIM.
MIN.
INCHES
MAX.
MIN.
MAX.
A
4.06
4.83
0.160
0.190
D1
6.86
-
0.270
-
A1
0.00
0.25
0.000
0.010
E
9.65
10.67
0.380
0.420
6.22
-
0.245
-
b
0.51
0.99
0.020
0.039
E1
b1
0.51
0.89
0.020
0.035
e
b2
1.14
1.78
0.045
0.070
H
14.61
15.88
0.575
0.625
b3
1.14
1.73
0.045
0.068
L
1.78
2.79
0.070
0.110
2.54 BSC
0.100 BSC
c
0.38
0.74
0.015
0.029
L1
-
1.65
-
0.066
c1
0.38
0.58
0.015
0.023
L2
-
1.78
-
0.070
c2
1.14
1.65
0.045
0.065
L3
D
8.38
9.65
0.330
0.380
L4
0.25 BSC
4.78
5.28
0.010 BSC
0.188
0.208
ECN: S-82110-Rev. A, 15-Sep-08
DWG: 5970
Notes
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Dimensions are shown in millimeters (inches).
3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the
outmost extremes of the plastic body at datum A.
4. Thermal PAD contour optional within dimension E, L1, D1 and E1.
5. Dimension b1 and c1 apply to base metal only.
6. Datum A and B to be determined at datum plane H.
7. Outline conforms to JEDEC outline to TO-263AB.
Document Number: 91364
Revision: 15-Sep-08
www.vishay.com
1
Package Information
Vishay Siliconix
I2PAK (TO-262) (HIGH VOLTAGE)
A
(Datum A)
E
B
c2
A
E
A
L1
Seating
plane
D1
D
C
L2
C
B
B
L
A
c
3 x b2
E1
A1
3xb
Section A - A
Base
metal
2xe
b1, b3
Plating
0.010 M A M B
c1
c
(b, b2)
Lead tip
Section B - B and C - C
Scale: None
MILLIMETERS
INCHES
MILLIMETERS
INCHES
DIM.
MIN.
MAX.
MIN.
MAX.
DIM.
MIN.
MAX.
MIN.
MAX.
A
4.06
4.83
0.160
0.190
D
8.38
9.65
0.330
0.380
A1
2.03
3.02
0.080
0.119
D1
6.86
-
0.270
-
b
0.51
0.99
0.020
0.039
E
9.65
10.67
0.380
0.420
b1
0.51
0.89
0.020
0.035
E1
6.22
-
0.245
-
b2
1.14
1.78
0.045
0.070
e
b3
1.14
1.73
0.045
0.068
L
13.46
14.10
0.530
0.555
c
0.38
0.74
0.015
0.029
L1
-
1.65
-
0.065
c1
0.38
0.58
0.015
0.023
L2
3.56
3.71
0.140
0.146
c2
1.14
1.65
0.045
0.065
2.54 BSC
0.100 BSC
ECN: S-82442-Rev. A, 27-Oct-08
DWG: 5977
Notes
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm per side. These dimensions are measured at the outmost
extremes of the plastic body.
3. Thermal pad contour optional within dimension E, L1, D1, and E1.
4. Dimension b1 and c1 apply to base metal only.
Document Number: 91367
Revision: 27-Oct-08
www.vishay.com
1
AN826
Vishay Siliconix
RECOMMENDED MINIMUM PADS FOR D2PAK: 3-Lead
0.420
0.355
0.635
(16.129)
(9.017)
(10.668)
0.145
(3.683)
0.135
(3.429)
0.200
0.050
(5.080)
(1.257)
Recommended Minimum Pads
Dimensions in Inches/(mm)
Return to Index
Document Number: 73397
11-Apr-05
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1
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Revision: 01-Jan-2022
1
Document Number: 91000