IRF820

IRF820 www.vishay.com Vishay Siliconix Power MOSFET FEATURES D • Dynamic dV/dt rating TO-220AB • • • • • G G D S S Note * This datasheet provides information about parts that are RoHS-compliant and / or parts that are non RoHS-compliant. For example, parts with lead (Pb) terminations are not RoHS-compliant. Please see the information / tables in this datasheet for details N-Channel MOSFET PRODUCT SUMMARY VDS (V) DESCRIPTION 500 RDS(on) (Ω) VGS = 10 V 3.0 Qg max. (nC) 24 Qgs (nC) 3.3 Qgd (nC) Third generation power MOSFETs from Vishay provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness. 13 Configuration Repetitive avalanche rated Available Fast switching Ease of paralleling Simple drive requirements Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 The TO-220AB package is universally preferred for commercial-industrial applications at power dissipation levels to approximately 50 W. The low thermal resistance and low package cost of the TO-220AB contribute to its wide acceptance throughout the industry. Single ORDERING INFORMATION Package TO-220AB Lead (Pb)-free IRF820PbF Lead (Pb)-free and halogen-free IRF820PbF-BE3 ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted) PARAMETER SYMBOL LIMIT Drain-source voltage VDS 500 Gate-source voltage VGS ± 20 VGS at 10 V Continuous drain current TC = 25 °C TC = 100 °C Pulsed drain current a ID IDM Linear derating factor Single pulse avalanche energy b UNIT V 2.5 1.6 A 8.0 0.40 W/°C mJ EAS 210 Repetitive avalanche current a IAR 2.5 A Repetitive avalanche energy a EAR 5.0 mJ Maximum power dissipation TC = 25 °C Peak diode recovery dV/dt c Operating junction and storage temperature range Soldering recommendations (peak temperature) d Mounting torque For 10 s 6-32 or M3 screw PD 50 W dV/dt 3.5 V/ns TJ, Tstg -55 to +150 300 °C 10 lbf · in 1.1 N·m Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11) b. VDD = 50 V, starting TJ = 25 °C, L = 60 mH, Rg = 25 Ω, IAS = 2.5 A (see fig. 12) c. ISD ≤ 2.5 A, dI/dt ≤ 50 A/μs, VDD ≤ VDS, TJ ≤ 150 °C d. 1.6 mm from case S21-0852-Rev. D, 16-Aug-2021 Document Number: 91059 1 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRF820 www.vishay.com Vishay Siliconix THERMAL RESISTANCE RATINGS PARAMETER SYMBOL TYP. MAX. Maximum junction-to-ambient RthJA - 62 Case-to-sink, flat, greased surface RthCS 0.50 - Maximum junction-to-case (drain) RthJC - 2.5 UNIT °C/W SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static Drain-source breakdown voltage VDS temperature coefficient Gate-source threshold voltage VDS VGS = 0 V, ID = 250 μA 500 - - V ΔVDS/TJ Reference to 25 °C, ID = 1 mA - 0.59 - V/°C VGS(th) VDS = VGS, ID = 250 μA 2.0 - 4.0 V Gate-source leakage IGSS VGS = ± 20 V - - ± 100 nA Zero gate voltage drain current IDSS VDS = 500 V, VGS = 0 V - - 25 VDS = 400 V, VGS = 0 V, TJ = 125 °C - - 250 - - 3.0 Ω S Drain-source on-state resistance Forward transconductance RDS(on) ID = 1.5 A b VGS = 10 V gfs VDS = 50 V, ID = 1.5 A 1.5 - - VGS = 0 V, VDS = 25 V, f = 1.0 MHz, see fig. 5 - 360 - - 92 - - 37 - - - 24 - - 3.3 - - 13 - 8.0 - μA Dynamic Input capacitance Ciss Output capacitance Coss Reverse transfer capacitance Crss Total gate charge Qg Gate-source charge Qgs Gate-drain charge Qgd Turn-on delay time td(on) Rise time Turn-off delay time tr td(off) Fall time tf Gate input resistance Rg Internal drain inductance LD Internal source inductance LS VGS = 10 V ID = 2.1 A, VDS = 400 V, see fig. 6 and 13 b pF nC VDD = 250 V, ID = 2.1 A, Rg = 18 Ω, RD = 100 Ω, see fig. 10 b - 8.6 - - 33 - - 16 - f = 1 MHz, open drain 1.8 - 12.6 - 4.5 - - 7.5 - - - 2.5 - - 8.0 - - 1.6 - 260 520 ns - 0.7 1.4 nC Between lead, 6 mm (0.25") from package and center of die contact D ns Ω nH G S Drain-Source Body Diode Characteristics Continuous source-drain diode current IS Pulsed diode forward current a ISM Body diode voltage VSD Body diode reverse recovery time trr Body diode reverse recovery charge Qrr Forward turn-on time ton MOSFET symbol showing the integral reverse p - n junction diode D A G S TJ = 25 °C, IS = 2.5 A, VGS = 0 V b TJ = 25 °C, IF = 2.1 A, dI/dt = 100 A/μs V Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD) Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11) b. Pulse width ≤ 300 μs; duty cycle ≤ 2 % S21-0852-Rev. D, 16-Aug-2021 Document Number: 91059 2 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRF820 www.vishay.com Vishay Siliconix VGS 15 V 10 V 8.0 V 7.0 V 6.0 V 5.5 V 5.0 V Bottom 4.5 V ID, Drain Current (A) Top 100 4.5 V 20 µs Pulse Width TC = 25 °C 10-1 100 101 VDS, Drain-to-Source Voltage (V) 91059_01 RDS(on), Drain-to-Source On Resistance (Normalized) TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 3.0 ID = 2.1 A VGS = 10 V 2.5 2.0 1.5 1.0 0.5 0.0 - 60 - 40 - 20 0 91059_04 Fig. 1 - Typical Output Characteristics, TC = 25 °C 20 40 60 80 100 120 140 160 TJ, Junction Temperature (°C) Fig. 4 - Normalized On-Resistance vs. Temperature 800 VGS 15 V 10 V 8.0 V 7.0 V 6.0 V 5.5 V 5.0 V Bottom 4.5 V VGS = 0 V, f = 1 MHz Ciss = Cgs + Cgd, Cds Shorted Crss = Cgd Coss = Cds + Cgd 100 4.5 V 600 Capacitance (pF) ID, Drain Current (A) Top Ciss 400 Coss 200 20 µs Pulse Width TC = 150 °C 10-1 100 VDS, Drain-to-Source Voltage (V) 91059_02 Crss 0 100 101 VDS, Drain-to-Source Voltage (V) 91059_05 Fig. 2 - Typical Output Characteristics, TC = 150 °C Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage ID, Drain Current (A) 25 °C 100 10-1 20 µs Pulse Width VDS = 50 V VGS, Gate-to-Source Voltage (V) 20 150 °C 101 ID = 2.1 A VDS = 400 V 16 VDS = 250 V VDS = 100 V 12 8 4 For test circuit see figure 13 0 4 91059_03 5 6 7 8 9 10 VGS, Gate-to-Source Voltage (V) Fig. 3 - Typical Transfer Characteristics S21-0852-Rev. D, 16-Aug-2021 0 91059_06 4 8 12 16 20 24 QG, Total Gate Charge (nC) Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage Document Number: 91059 3 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRF820 www.vishay.com Vishay Siliconix 100 2.0 ID, Drain Current (A) ISD, Reverse Drain Current (A) 2.5 150 °C 25 °C 1.5 1.0 0.5 VGS = 0 V 0.4 0.6 0.8 0.0 1.2 1.0 25 VSD, Source-to-Drain Voltage (V) 91059_07 ID, Drain Current (A) 125 150 RD VDS VGS 2 10 100 Fig. 9 - Maximum Drain Current vs. Case Temperature Operation in this area limited by RDS(on) 5 75 TC, Case Temperature (°C) 91059_09 Fig. 7 - Typical Source-Drain Diode Forward Voltage 102 50 D.U.T. RG 10 µs + - VDD 5 100 µs 2 10 V 1 1 ms Pulse width ≤ 1 µs Duty factor ≤ 0.1 % 5 10 ms 2 0.1 Fig. 10a - Switching Time Test Circuit 5 TC = 25 °C TJ = 150 °C Single Pulse 2 10-2 0.1 2 5 1 2 5 10 2 5 102 VDS 2 5 103 2 5 90 % 104 VDS, Drain-to-Source Voltage (V) 91059_08 Fig. 8 - Maximum Safe Operating Area 10 % VGS td(on) td(off) tf tr Fig. 10b - Switching Time Waveforms Thermal Response (ZthJC) 10 1 D = 0.5 0.2 PDM 0.1 0.05 0.1 0.02 0.01 t1 Single Pulse (Thermal Response) t2 Notes: 1. Duty Factor, D = t1/t2 2. Peak Tj = PDM x ZthJC + TC 10-2 10-5 91059_11 10-4 10-3 10-2 0.1 1 10 t1, Rectangular Pulse Duration (s) Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case S21-0852-Rev. D, 16-Aug-2021 Document Number: 91059 4 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRF820 www.vishay.com Vishay Siliconix L Vary tp to obtain required IAS VDS QG 10 V D.U.T. Rg + - IAS QGS QGD V DD VG 10 V 0.01 Ω tp Charge Fig. 12a - Unclamped Inductive Test Circuit Fig. 13a - Basic Gate Charge Waveform VDS Current regulator Same type as D.U.T. tp VDD 50 kΩ 12 V 0.2 µF VDS 0.3 µF + D.U.T. IAS - VDS VGS Fig. 12b - Unclamped Inductive Waveforms 3 mA EAS, Single Pulse Energy (mJ) 500 ID 1.1 A 1.6 A Bottom 2.5 A Top 400 IG ID Current sampling resistors Fig. 13b - Gate Charge Test 300 200 100 0 VDD = 50 V 25 91059_12c 50 75 100 125 150 Starting TJ, Junction Temperature (°C) Fig. 12c - Maximum Avalanche Energy vs. Drain Current S21-0852-Rev. D, 16-Aug-2021 Document Number: 91059 5 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRF820 www.vishay.com Vishay Siliconix Peak Diode Recovery dv/dt Test Circuit + D.U.T. Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer 3 + 2 4 - - + 1 Rg • • • • 1 Driver gate drive Period P.W. + V - DD dv/dt controlled by Rg Driver same type as D.U.T. ISD controlled by duty factor “D” D.U.T. - device under test D= P.W. Period V GS = 10 V a 2 D.U.T. ISD waveform Reverse recovery current 3 D.U.T. VDS Body diode forward current di/dt waveform Diode recovery dv/dt Re-applied voltage V DD Body diode forward drop 4 Inductor current Ripple ≤ 5 % ISD Note a. VGS = 5 V for logic level devices Fig. 14 - For N-Channel Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91059. S21-0852-Rev. D, 16-Aug-2021 Document Number: 91059 6 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information www.vishay.com Vishay Siliconix TO-220-1 A E F D H(1) Q ØP 3 2 L(1) 1 M* L b(1) C b e J(1) e(1) MILLIMETERS DIM. INCHES MIN. MAX. MIN. MAX. A 4.24 4.65 0.167 0.183 b 0.69 1.02 0.027 0.040 b(1) 1.14 1.78 0.045 0.070 c 0.36 0.61 0.014 0.024 D 14.33 15.85 0.564 0.624 E 9.96 10.52 0.392 0.414 e 2.41 2.67 0.095 0.105 e(1) 4.88 5.28 0.192 0.208 F 1.14 1.40 0.045 0.055 H(1) 6.10 6.71 0.240 0.264 J(1) 2.41 2.92 0.095 0.115 L 13.36 14.40 0.526 0.567 L(1) 3.33 4.04 0.131 0.159 ØP 3.53 3.94 0.139 0.155 Q 2.54 3.00 0.100 0.118 ECN: E21-0621-Rev. D, 04-Nov-2021 DWG: 6031 Note • M* = 0.052 inches to 0.064 inches (dimension including protrusion), heatsink hole for HVM Document Number: 66542 1 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Revison: 04-Nov-2021 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. 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Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners. © 2022 VISHAY INTERTECHNOLOGY, INC. ALL RIGHTS RESERVED Revision: 01-Jan-2022 1 Document Number: 91000