IRF830AS, IRF830AL, SiHF830AS, SiHF830AL
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Vishay Siliconix
Power MOSFET
FEATURES
D
• Low gate charge Qg results in simple drive
requirement
• Improved gate, avalanche and dynamic dV/dt Available
ruggedness
• Fully characterized capacitance and avalanche
Available
voltage and current
• Effective Coss specified
• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
D2PAK (TO-2
I2PAK (TO-262)
G
G
G
D
S
D
S
S
Note
* This datasheet provides information about parts that are
RoHS-compliant and / or parts that are non RoHS-compliant. For
example, parts with lead (Pb) terminations are not RoHS-compliant.
Please see the information / tables in this datasheet for details
N-Channel MOSFET
PRODUCT SUMMARY
VDS (V)
RDS(on) max. (Ω)
500
VGS = 10 V
APPLICATIONS
1.40
Qg max. (nC)
24
• Switch mode power supply (SMPS)
Qgs (nC)
6.3
• Uninterruptible power supply
Qgd (nC)
11
• High speed power switching
Configuration
Single
TYPICAL SMPS TOPOLOGIES
• Two transistor forward
• Half bridge and full bridge
ORDERING INFORMATION
D2PAK (TO-263)
D2PAK (TO-263)
I2PAK (TO-262)
Lead (Pb)-free and Halogen-free
SiHF830AS-GE3
SiHF830ASTRL-GE3 a
SiHF830AL-GE3 a
Lead (Pb)-free
IRF830ASPbF
IRF830ASTRLPbF a
IRF830ALPbF
Package
Note
a. See device orientation
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
LIMIT
Drain-Source Voltage
VDS
500
Gate-Source Voltage
VGS
± 30
Continuous Drain Current
VGS at 10 V
TC = 25 °C
TC = 100 °C
Pulsed Drain Current a, e
ID
IDM
Linear Derating Factor
UNIT
V
5.0
3.2
A
20
0.59
W/°C
Single Pulse Avalanche Energy b, e
EAS
230
mJ
Avalanche Currenta
IAR
5.0
A
Repetiitive Avalanche Energy a
EAR
7.4
mJ
Maximum Power Dissipation
TA = 25 °C
TC = 25 °C
Peak Diode Recovery dV/dtc, e
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak temperature) d
for 10 s
PD
3.1
74
dV/dt
5.3
TJ, Tstg
-55 to +150
300
W
V/ns
°C
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11)
b. Starting TJ = 25 °C, L = 18 mH, Rg = 25 Ω, IAS = 5.0 A (see fig. 12)
c. ISD ≤ 5.0 A, dI/dt ≤ 370 A/μs, VDD ≤ VDS, TJ ≤ 150 °C
d. 1.6 mm from case
e. Uses SiHF830A data and test conditions
S21-0901-Rev. D, 30-Aug-2021
Document Number: 91062
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ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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Vishay Siliconix
THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
TYP.
MAX.
Maximum Junction-to-Ambient
(PCB mounted, steady-state) a
RthJA
-
40
Maximum Junction-to-Case (Drain)
RthJC
-
1.7
UNIT
°C/W
Note
a. When mounted on 1" square PCB (FR-4 or G-10 material)
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-Source Breakdown Voltage
VDS Temperature Coefficient
Gate-Source Threshold Voltage
VDS
VGS = 0, ID = 250 μA
500
-
-
V
ΔVDS/TJ
Reference to 25 °C, ID = 1 mA d
-
0.60
-
V/°C
VGS(th)
VDS = VGS, ID = 250 μA
2.0
-
4.5
V
Gate-Source Leakage
IGSS
VGS = ± 30 V
-
-
± 100
nA
Zero Gate Voltage Drain Current
IDSS
VDS = 500 V, VGS = 0 V
-
-
25
VDS = 400 V, VGS = 0 V, TJ = 125 °C
-
-
250
Drain-Source On-State Resistance
Forward Transconductance
μA
-
-
1.4
Ω
gfs
VDS = 50 V, ID = 3.0 A d
2.8
-
-
S
VGS = 0 V,
VDS = 25 V,
f = 1.0 MHz, see fig. 5 d
-
620
-
-
93
-
-
4.3
-
RDS(on)
ID = 3.0 A b
VGS = 10 V
Dynamic
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
Output Capacitance
Coss
Effective Output Capacitance
VGS = 0 V
Coss eff.
VDS = 1.0 V, f = 1.0 MHz
-
886
VDS = 400 V, f = 1.0 MHz
-
27
-
VDS = 0 V to 400 V c, d
-
39
-
-
-
24
-
-
6.3
pF
Total Gate Charge
Qg
Gate-Source Charge
Qgs
Gate-Drain Charge
Qgd
-
-
11
Turn-On Delay Time
td(on)
-
10
-
tr
VDD = 250 V, ID = 5.0 A,
Rg = 14 Ω, RD = 49 Ω, see fig. 10 b, d
-
21
-
-
21
-
-
15
-
f = 1 MHz, open drain
1.7
-
10.7
-
-
5.0
-
-
20
-
-
1.5
-
430
650
ns
-
2.0
3.0
μC
Rise Time
Turn-Off Delay Time
td(off)
Fall Time
tf
Gate Input Resistance
Rg
VGS = 10 V
ID = 5.0 A, VDS = 400 V,
see fig. 6 and 13 b, d
nC
ns
Ω
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
IS
Pulsed Diode Forward Current a
ISM
Body Diode Voltage
VSD
Body Diode Reverse Recovery Time
trr
Body Diode Reverse Recovery Charge
Qrr
Forward Turn-On Time
ton
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
A
G
S
TJ = 25 °C, IS = 5.0 A, VGS = 0 V b
TJ = 25 °C, IF = 5.0 A, dI/dt = 100 A/μs b, d
V
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11)
b. Pulse width ≤ 300 μs; duty cycle ≤ 2 %
c. Coss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80 % VDS
d. Uses SiHF830A data and test conditions
S21-0901-Rev. D, 30-Aug-2021
Document Number: 91062
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ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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Vishay Siliconix
ID, Drain-to-Source Current (A)
102
VGS
15 V
10 V
8.0 V
7.0 V
6.0 V
5.5 V
5.0 V
Bottom 4.5 V
Top
10
1
4.5 V
0.1
20 µs Pulse Width
TJ = 25 °C
10-2
0.1
1
102
10
VDS, Drain-to-Source Voltage (V)
91062_01
RDS(on), Drain-to-Source On Resistance
(Normalized)
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
C, Capacitance (pF)
ID, Drain-to-Source Current (A)
4.5 V
1
1.0
0.5
0.0
- 60 - 40 - 20 0
TJ, Junction Temperature (°C)
Ciss
102
Coss
10
1
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
TJ = 150 °C
TJ = 25 °C
1
20 µs Pulse Width
VDS = 50 V
7.0
VGS, Gate-to-Source Voltage (V)
Fig. 3 - Typical Transfer Characteristics
S21-0901-Rev. D, 30-Aug-2021
VGS, Gate-to-Source Voltage (V)
10
6.0
103
VDS, Drain-to-Source Voltage (V)
91062_05
20
5.0
102
10
1
102
0.1
VGS = 0 V, f = 1 MHz
Ciss = Cgs + Cgd, Cds Shorted
Crss = Cgd
Coss = Cds + Cgd
103
102
10
VDS, Drain-to-Source Voltage (V)
4.0
20 40 60 80 100 120 140 160
Crss
20 µs Pulse Width
TJ = 150 °C
Fig. 2 - Typical Output Characteristics
ID, Drain-to-Source Current (A)
1.5
104
VGS
Top
15 V
10 V
8.0 V
7.0 V
10
6.0 V
5.5 V
5.0 V
Bottom 4.5 V
0.1
91062_03
2.0
Fig. 4 - Normalized On-Resistance vs. Temperature
102
91062_02
ID = 5.0 A
VGS = 10 V
91062_04
Fig. 1 - Typical Output Characteristics
1
2.5
ID = 5.0 A
VDS = 400 V
16
VDS = 250 V
VDS = 100 V
12
8
4
For test circuit
see figure 13
0
0
8.0
91062_06
4
8
12
16
20
24
QG, Total Gate Charge (nC)
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
Document Number: 91062
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THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
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IRF830AS, IRF830AL, SiHF830AS, SiHF830AL
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Vishay Siliconix
5.0
4.0
ID, Drain Current (A)
ISD, Reverse Drain Current (A)
102
10
TJ = 150 °C
1
TJ = 25 °C
3.0
2.0
1.0
VGS = 0 V
0.1
0.2
0.4
0.6
1.0
0.8
0.0
25
1.2
VSD, Source-to-Drain Voltage (V)
91062_07
50
150
RD
VDS
Operation in this area limited
by RDS(on)
VGS
D.U.T.
Rg
10 µs
10
125
Fig. 9 - Maximum Drain Current vs. Case Temperature
102
ID, Drain Current (A)
100
TC, Case Temperature (°C)
91062_09
Fig. 7 - Typical Source-Drain Diode Forward Voltage
75
+
- VDD
10 V
100 µs
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
1 ms
1
Fig. 10a - Switching Time Test Circuit
10 ms
TC = 25 °C
TJ = 150 °C
Single Pulse
0.1
VDS
90 %
102
10
103
104
VDS, Drain-to-Source Voltage (V)
91062_08
10 %
VGS
Fig. 8 - Maximum Safe Operating Area
td(on)
td(off) tf
tr
Fig. 10b - Switching Time Waveforms
Thermal Response (ZthJC)
10
1
D = 0.50
0.20
PDM
0.10
0.1
0.05
t1
t2
0.02
0.01
Notes:
1. Duty Factor, D = t1/t2
2. Peak Tj = PDM x ZthJC + TC
Single Pulse
(Thermal Response)
10-2
10-5
10-4
10-3
10-2
0.1
1
t1, Rectangular Pulse Duration (s)
91062_11
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
S21-0901-Rev. D, 30-Aug-2021
Document Number: 91062
4
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
IRF830AS, IRF830AL, SiHF830AS, SiHF830AL
www.vishay.com
Vishay Siliconix
15 V
QG
VGS
Driver
L
VDS
QGS
D.U.T.
Rg
20 V
VG
+
A
- VDD
IAS
QGD
0.01 Ω
tp
Charge
Fig. 12a - Unclamped Inductive Test Circuit
Fig. 13a - Maximum Avalanche Energy vs. Drain Current
VDS
tp
IAS
EAS, Single Pulse Avalanche Energy (mJ)
Fig. 12b - Unclamped Inductive Waveforms
500
ID
Top
2.2 A
3.2 A
Bottom 5.0 A
400
VDSav, Avalanche Voltage (V)
790
785
780
775
770
0.0
300
2.0
3.0
4.0
5.0
IAV, Avalanche Current (A)
91062_12d
Fig. 12d - Basic Gate Charge Waveform
200
100
Current regulator
Same type as D.U.T.
0
25
50
75
100
125
50 kΩ
150
12 V
91062_12c
1.0
0.2 µF
Starting TJ, Junction Temperature (°C)
0.3 µF
+
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
D.U.T.
-
VDS
VGS
3 mA
IG
ID
Current sampling resistors
Fig. 13b - Gate Charge Test Circuit
S21-0901-Rev. D, 30-Aug-2021
Document Number: 91062
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ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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www.vishay.com
Vishay Siliconix
Peak Diode Recovery dV/dt Test Circuit
+
D.U.T.
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
-
-
Rg
•
•
•
•
+
dV/dt controlled by Rg
Driver same type as D.U.T.
ISD controlled by duty factor “D”
D.U.T. - device under test
+
-
VDD
Driver gate drive
P.W.
Period
D=
P.W.
Period
VGS = 10 Va
D.U.T. lSD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
Inductor current
VDD
Body diode forward drop
Ripple ≤ 5 %
ISD
Note
a. VGS = 5 V for logic level devices
Fig. 14 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91062.
S21-0901-Rev. D, 30-Aug-2021
Document Number: 91062
6
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Package Information
Vishay Siliconix
TO-263AB (HIGH VOLTAGE)
A
(Datum A)
3
A
4
4
L1
B
A
E
c2
H
Gauge
plane
4
0° to 8°
5
D
B
Detail A
Seating plane
H
1
2
C
3
C
L
L3
L4
Detail “A”
Rotated 90° CW
scale 8:1
L2
B
A1
B
A
2 x b2
c
2xb
E
0.010 M A M B
± 0.004 M B
2xe
Plating
5
b1, b3
Base
metal
c1
(c)
D1
4
5
(b, b2)
Lead tip
MILLIMETERS
DIM.
MIN.
MAX.
View A - A
INCHES
MIN.
4
E1
Section B - B and C - C
Scale: none
MILLIMETERS
MAX.
DIM.
MIN.
INCHES
MAX.
MIN.
MAX.
A
4.06
4.83
0.160
0.190
D1
6.86
-
0.270
-
A1
0.00
0.25
0.000
0.010
E
9.65
10.67
0.380
0.420
6.22
-
0.245
-
b
0.51
0.99
0.020
0.039
E1
b1
0.51
0.89
0.020
0.035
e
b2
1.14
1.78
0.045
0.070
H
14.61
15.88
0.575
0.625
b3
1.14
1.73
0.045
0.068
L
1.78
2.79
0.070
0.110
2.54 BSC
0.100 BSC
c
0.38
0.74
0.015
0.029
L1
-
1.65
-
0.066
c1
0.38
0.58
0.015
0.023
L2
-
1.78
-
0.070
c2
1.14
1.65
0.045
0.065
L3
D
8.38
9.65
0.330
0.380
L4
0.25 BSC
4.78
5.28
0.010 BSC
0.188
0.208
ECN: S-82110-Rev. A, 15-Sep-08
DWG: 5970
Notes
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Dimensions are shown in millimeters (inches).
3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the
outmost extremes of the plastic body at datum A.
4. Thermal PAD contour optional within dimension E, L1, D1 and E1.
5. Dimension b1 and c1 apply to base metal only.
6. Datum A and B to be determined at datum plane H.
7. Outline conforms to JEDEC outline to TO-263AB.
Document Number: 91364
Revision: 15-Sep-08
www.vishay.com
1
Package Information
Vishay Siliconix
I2PAK (TO-262) (HIGH VOLTAGE)
A
(Datum A)
E
B
c2
A
E
A
L1
Seating
plane
D1
D
C
L2
C
B
B
L
A
c
3 x b2
E1
A1
3xb
Section A - A
Base
metal
2xe
b1, b3
Plating
0.010 M A M B
c1
c
(b, b2)
Lead tip
Section B - B and C - C
Scale: None
MILLIMETERS
INCHES
MILLIMETERS
INCHES
DIM.
MIN.
MAX.
MIN.
MAX.
DIM.
MIN.
MAX.
MIN.
MAX.
A
4.06
4.83
0.160
0.190
D
8.38
9.65
0.330
0.380
A1
2.03
3.02
0.080
0.119
D1
6.86
-
0.270
-
b
0.51
0.99
0.020
0.039
E
9.65
10.67
0.380
0.420
b1
0.51
0.89
0.020
0.035
E1
6.22
-
0.245
-
b2
1.14
1.78
0.045
0.070
e
b3
1.14
1.73
0.045
0.068
L
13.46
14.10
0.530
0.555
c
0.38
0.74
0.015
0.029
L1
-
1.65
-
0.065
c1
0.38
0.58
0.015
0.023
L2
3.56
3.71
0.140
0.146
c2
1.14
1.65
0.045
0.065
2.54 BSC
0.100 BSC
ECN: S-82442-Rev. A, 27-Oct-08
DWG: 5977
Notes
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm per side. These dimensions are measured at the outmost
extremes of the plastic body.
3. Thermal pad contour optional within dimension E, L1, D1, and E1.
4. Dimension b1 and c1 apply to base metal only.
Document Number: 91367
Revision: 27-Oct-08
www.vishay.com
1
AN826
Vishay Siliconix
RECOMMENDED MINIMUM PADS FOR D2PAK: 3-Lead
0.420
0.355
0.635
(16.129)
(9.017)
(10.668)
0.145
(3.683)
0.135
(3.429)
0.200
0.050
(5.080)
(1.257)
Recommended Minimum Pads
Dimensions in Inches/(mm)
Return to Index
Document Number: 73397
11-Apr-05
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1
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Revision: 01-Jan-2022
1
Document Number: 91000