IRF840LC

IRF840LC www.vishay.com Vishay Siliconix Power MOSFET FEATURES D • • • • • • • TO-220AB G G D S S Note * This datasheet provides information about parts that are RoHS-compliant and / or parts that are non RoHS-compliant. For example, parts with lead (Pb) terminations are not RoHS-compliant. Please see the information / tables in this datasheet for details N-Channel MOSFET PRODUCT SUMMARY VDS (V) RDS(on) (Ω) DESCRIPTION 500 VGS = 10 V Qg max. (nC) 39 10 Qgd (nC) 19 Configuration This new series of low charge power MOSFETs achieve significantly lower gate charge over conventional MOSFETs. Utilizing the new LCDMOS technology, the device improvements are achieved without added product cost, allowing for reduced gate drive requirements and total system savings. In addition, reduced switching losses and improved efficiency are achievable in a variety of high frequency applications. Frequencies of a few MHz at high current are possible using the new low charge MOSFETs. These device improvements combined with the proven ruggedness and reliability that are characteristic of Power MOSFETs offer the designer a new standard in power transistors for switching applications. 0.85 Qgs (nC) Ultra low gate charge Reduced gate drive requirement Available Enhanced 30 V VGS rating Available Reduced Ciss, Coss, Crss Extremely high frequency operation Repetitive avalanche rated Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 Single ORDERING INFORMATION Package TO-220AB Lead (Pb)-free IRF840LCPbF Lead (Pb)-free and halogen-free IRF840LCPbF-BE3 ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted) PARAMETER SYMBOL LIMIT Drain-source voltage VDS 500 Gate-source voltage VGS ± 30 Continuous drain current VGS at 10 V TC = 25 °C TC = 100 °C Pulsed drain current a ID UNIT V 8.0 5.1 A IDM 28 1.0 W/°C Single pulse avalanche energy b EAS 510 mJ Repetitive avalanche current a IAR 8.0 A Repetitive avalanche energy a EAR 13 mJ Linear derating factor Maximum power dissipation TC = 25 °C Peak diode recovery dV/dt c Operating junction and storage temperature range Soldering recommendations (peak temperature) d Mounting torque For 10 s 6-32 or M3 screw PD 125 W dV/dt 3.5 V/ns TJ, Tstg -55 to +150 300 °C 10 lbf · in 1.1 N·m Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11) b. VDD = 50 V, starting TJ = 25 °C, L = 14 mH, Rg = 25 Ω, IAS = 8.0 A (see fig. 12) c. ISD ≤ 8.0 A, dI/dt ≤ 100 A/μs, VDD ≤ VDS, TJ ≤ 150 °C d. 1.6 mm from case S21-0852-Rev. C, 16-Aug-2021 Document Number: 91067 1 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRF840LC www.vishay.com Vishay Siliconix THERMAL RESISTANCE RATINGS PARAMETER SYMBOL TYP. MAX. Maximum junction-to-ambient RthJA - 62 Case-to-sink, flat, greased surface RthCS 0.50 - Maximum junction-to-case (drain) RthJC - 1.0 UNIT °C/W SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static Drain-source breakdown voltage VDS temperature coefficient Gate-source threshold voltage VDS VGS = 0 V, ID = 250 μA 500 - - V ΔVDS/TJ Reference to 25 °C, ID = 1 mA - 0.63 - V/°C VGS(th) VDS = VGS, ID = 250 μA 2.0 - 4.0 V Gate-source leakage IGSS VGS = ± 20 V - - ± 100 nA Zero gate voltage drain current IDSS VDS = 500 V, VGS = 0 V - - 25 VDS = 400V, VGS = 0 V, TJ = 125 °C - - 250 μA - - 0.85 Ω gfs VDS = 50 V, ID = 4.8 A b 4.0 - - S Drain-source breakdown voltage Ciss 1100 - Coss - 170 - Gate-source threshold voltage Crss VGS = 0 V, VDS = 25 V, f = 1.0 MHz, see fig. 5 - VDS temperature coefficient - 18 - Drain-source on-state resistance Forward transconductance RDS(on) ID = 4.8 A b VGS = 10 V Dynamic Gate-source leakage Zero gate voltage drain current Drain-source on-state resistance Forward transconductance Drain-source breakdown voltage Qg Qgs - - 39 - - 10 Qgd - - 19 - 12 - tr td(off) VDS temperature coefficient tf Rg Internal source inductance ID = 8.0 A, VDS = 400 V see fig. 6 and 13 b td(on) Gate input resistance Internal drain inductance VGS = 10 V LD LS pF nC VDD = 250 V, ID = 8.0 A, Rg = 9.1 Ω, RD= 30 Ω see fig. 10 b - 25 - - 27 - - 19 - f = 1 MHz, open drain 0.7 - 3.7 - 4.5 - - 7.5 - - - 8.0 S - - 28 Vb - - 2.0 V - 490 740 ns - 3.0 4.5 μC Between lead, 6 mm (0.25") from package and center of die contact D ns Ω nH G S Drain-Source Body Diode Characteristics Continuous source-drain diode current Pulsed diode forward current a Body diode voltage IS ISM VSD Body diode reverse recovery time trr Body diode reverse recovery charge Qrr Forward turn-on time ton MOSFET symbol showing the integral reverse p - n junction diode D A G TJ = 25 °C, IS = 8.0 A, VGS = 0 TJ = 25 °C, IF = 8.0 A, dI/dt = 100 A/μs b Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD) Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11) b. Pulse width ≤ 300 μs; duty cycle ≤ 2 % S21-0852-Rev. C, 16-Aug-2021 Document Number: 91067 2 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRF840LC www.vishay.com Vishay Siliconix VGS 15 V 10 V 8.0 V 7.0 V 6.0 V 5.5 V 5.0 V Bottom 4.5 V Top ID, Drain Current (A) 101 100 4.5 V 20 µs Pulse Width TC = 25 °C 10-1 10-1 100 101 VDS, Drain-to-Source Voltage (V) 91067_01 RDS(on), Drain-to-Source On Resistance (Normalized) TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 3.0 2.5 2.0 1.5 1.0 0.5 0.0 - 60 - 40 - 20 0 Fig. 4 - Normalized On-Resistance vs. Temperature 2400 VGS 15 V 10 V 8.0 V 7.0 V 6.0 V 5.5 V 5.0 V Bottom 4.5 V VGS = 0 V, f = 1 MHz Ciss = Cgs + Cgd, Cds Shorted Crss = Cgd Coss = Cds + Cgd Top 100 2000 4.5 V 10-1 Capacitance (pF) 101 ID, Drain Current (A) 20 40 60 80 100 120 140 160 TJ, Junction Temperature (°C) 91067_04 Fig. 1 - Typical Output Characteristics, TC = 25 °C 1600 Ciss 1200 20 µs Pulse Width TC = 150 °C 10-1 100 800 Coss 400 Crss 0 101 100 VDS, Drain-to-Source Voltage (V) 91067_02 Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage 150 °C 25 °C 100 20 µs Pulse Width VDS = 50 V VGS, Gate-to-Source Voltage (V) 20 101 101 VDS, Drain-to-Source Voltage (V) 91067_05 Fig. 2 - Typical Output Characteristics, TC = 150 °C ID, Drain Current (A) ID = 8.0 A VGS = 10 V ID = 8.0 A VDS = 400 V 16 VDS = 250 V VDS = 100 V 12 8 4 For test circuit see figure 13 0 4 91067_03 5 6 7 8 9 10 VGS, Gate-to-Source Voltage (V) Fig. 3 - Typical Transfer Characteristics S21-0852-Rev. C, 16-Aug-2021 0 91067_06 8 16 24 32 40 48 QG, Total Gate Charge (nC) Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage Document Number: 91067 3 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRF840LC www.vishay.com Vishay Siliconix ID, Drain Current (A) ISD, Reverse Drain Current (A) 8.0 150 °C 101 25 °C 100 6.0 4.0 2.0 VGS = 0 V 0.6 0.8 1.0 1.2 1.4 0.0 1.6 25 VSD, Source-to-Drain Voltage (V) 91067_07 125 VGS 102 D.U.T. RG + - VDD 5 10 µs 2 10 10 V Pulse width ≤ 1 µs Duty factor ≤ 0.1 % 100 µs 5 150 RD VDS 2 ID, Drain Current (A) 100 Fig. 9 - Maximum Drain Current vs. Case Temperature Operation in this area limited by RDS(on) 5 75 TC, Case Temperature (°C) 91067_09 Fig. 7 - Typical Source-Drain Diode Forward Voltage 103 50 1 ms 2 1 2 0.1 2 1 5 10 2 5 Fig. 10a - Switching Time Test Circuit 10 ms TC = 25 °C TJ = 150 °C Single Pulse 5 VDS 102 2 5 90 % 103 VDS, Drain-to-Source Voltage (V) 91067_08 Fig. 8 - Maximum Safe Operating Area 10 % VGS td(on) td(off) tf tr Fig. 10b - Switching Time Waveforms Thermal Response (ZthJC) 10 1 D = 0.5 PDM 0.2 0.1 0.1 t1 0.05 0.02 0.01 t2 Notes: 1. Duty Factor, D = t1/t2 2. Peak Tj = PDM x ZthJC + TC Single Pulse (Thermal Response) 10-2 10-5 10-4 10-3 10-2 0.1 1 10 t1, Rectangular Pulse Duration (s) 91067_11 Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case S21-0852-Rev. C, 16-Aug-2021 Document Number: 91067 4 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRF840LC www.vishay.com Vishay Siliconix L Vary tp to obtain required IAS VDS QG 10 V D.U.T. RG + - IAS QGS QGD V DD VG 10 V 0.01 Ω tp Charge Fig. 12a - Unclamped Inductive Test Circuit Fig. 13a - Basic Gate Charge Waveform Current regulator Same type as D.U.T. VDS tp VDD 50 kΩ 12 V 0.2 µF 0.3 µF + VDS D.U.T. - VDS VGS IAS 3 mA Fig. 12b - Unclamped Inductive Waveforms EAS, Single Pulse Energy (mJ) 1200 ID Top 3.6 A 5.1 A Bottom 8.0 A 1000 IG ID Current sampling resistors Fig. 13b - Gate Charge Test Circuit 800 600 400 200 0 VDD = 50 V 25 91067_12c 50 75 100 125 150 Starting TJ, Junction Temperature (°C) Fig. 12c - Maximum Avalanche Energy vs. Drain Current S21-0852-Rev. C, 16-Aug-2021 Document Number: 91067 5 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRF840LC www.vishay.com Vishay Siliconix Peak Diode Recovery dv/dt Test Circuit + D.U.T. Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer 3 + 2 - - 4 + 1 Rg • • • • 1 Driver gate drive Period P.W. + V - DD dv/dt controlled by Rg Driver same type as D.U.T. ISD controlled by duty factor “D” D.U.T. - device under test D= P.W. Period V GS = 10 V a 2 D.U.T. ISD waveform Reverse recovery current 3 D.U.T. VDS Body diode forward current di/dt waveform Diode recovery dv/dt Re-applied voltage V DD Body diode forward drop 4 Inductor current Ripple ≤ 5 % ISD Note a. VGS = 5 V for logic level devices Fig. 14 - For N-Channel Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91067. S21-0852-Rev. C, 16-Aug-2021 Document Number: 91067 6 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information www.vishay.com Vishay Siliconix TO-220-1 A E F D H(1) Q ØP 3 2 L(1) 1 M* L b(1) C b e J(1) e(1) MILLIMETERS DIM. INCHES MIN. MAX. MIN. MAX. A 4.24 4.65 0.167 0.183 b 0.69 1.02 0.027 0.040 b(1) 1.14 1.78 0.045 0.070 c 0.36 0.61 0.014 0.024 D 14.33 15.85 0.564 0.624 E 9.96 10.52 0.392 0.414 e 2.41 2.67 0.095 0.105 e(1) 4.88 5.28 0.192 0.208 F 1.14 1.40 0.045 0.055 H(1) 6.10 6.71 0.240 0.264 J(1) 2.41 2.92 0.095 0.115 L 13.36 14.40 0.526 0.567 L(1) 3.33 4.04 0.131 0.159 ØP 3.53 3.94 0.139 0.155 Q 2.54 3.00 0.100 0.118 ECN: E21-0621-Rev. D, 04-Nov-2021 DWG: 6031 Note • M* = 0.052 inches to 0.064 inches (dimension including protrusion), heatsink hole for HVM Document Number: 66542 1 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Revison: 04-Nov-2021 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. 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