IRF840LCS

IRF840LCS, IRF840LCL, SiHF840LCS, SiHF840LCL www.vishay.com Vishay Siliconix Power MOSFET G G D S FEATURES D D2PAK (TO-263) I2PAK (TO-262) • • • • • • • G D S Note * This datasheet provides information about parts that are RoHS-compliant and / or parts that are non RoHS-compliant. For example, parts with lead (Pb) terminations are not RoHS-compliant. Please see the information / tables in this datasheet for details S N-Channel MOSFET PRODUCT SUMMARY VDS (V) DESCRIPTION 500 RDS(on) (Ω) VGS = 10 V Qg max. (nC) This series of low charge power MOSFETs achieve significantly lower gate charge then conventional Power MOSFETs. Utilizing the new LCDMOS (low charge device Power MOSFETs) technology, the device improvements are achieved without added product cost, allowing for reduced gate drive requirements and total system savings. In addition, reduced switching losses and improved efficiency are achievable in a variety of high frequency applications. Frequencies of a few MHz at high current are possible using the new low charge Power MOSFETs. These device improvements combined with the proven ruggedness and reliability that characterize Power MOSFETs offer the designer a new power transistor standard for switching applications. 0.85 39 Qgs (nC) 10 Qgd (nC) 19 Configuration Ultra low gate charge Reduced gate drive requirement Enhanced 30 V VGS rating Available Reduced Ciss, Coss, Crss Extremely high frequency operation Repetitive avalanche rated Available Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 Single ORDERING INFORMATION D2PAK (TO-263) Package Lead (Pb)-free and Halogen-free Lead (Pb)-free I2PAK (TO-262) SiHF840LCS-GE3 SiHF840LCL-GE3 IRF840LCSPbF IRF840LCLPbF IRF840LCSTRRPBF - Note a. See device orientation. ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted) PARAMETER Drain-Source Voltage Gate-Source Voltage VGS at 10 V Continuous Drain Current TC = 25 °C TC = 100 °C Current a, e Pulsed Drain Linear Derating Factor Single Pulse Avalanche Energy b, e Avalanche Current a Repetitive Avalanche Energy a Maximum Power Dissipation LIMIT VDS VGS 500 ± 30 8.0 5.1 28 1.0 510 8.0 13 125 3.1 3.5 -55 to +150 ID IDM EAS IAR EAR TC = 25 °C TA = 25 °C c, e PD dV/dt TJ, Tstg Peak Diode Recovery dV/dt Operating Junction and Storage Temperature Range Soldering Recommendations (Peak temperature) d SYMBOL For 10 s 300 UNIT V A W/°C mJ A mJ W V/ns °C Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11) b. Starting TJ = 25 °C, L = 14 mH, Rg = 25 Ω, IAS = 8.0 A (see fig. 12) c. ISD ≤ 8.0 A, dI/dt ≤ 100 A/μs, VDD ≤ VDS, TJ ≤ 150 °C d. 1.6 mm from case e. Uses IRF840LC, SiHF840LC data and test conditions S21-0901-Rev. D, 30-Aug-2021 Document Number: 91068 1 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRF840LCS, IRF840LCL, SiHF840LCS, SiHF840LCL www.vishay.com Vishay Siliconix THERMAL RESISTANCE RATINGS PARAMETER SYMBOL TYP. MAX. Maximum Junction-to-Ambient (PCB mounted, steady-state) a RthJA - 40 Maximum Junction-to-Case (Drain) RthJC - 1.0 UNIT °C/W Note a. When mounted on 1" square PCB (FR-4 or G-10 material) SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static Drain-Source Breakdown Voltage VDS Temperature Coefficient Gate-Source Threshold Voltage VDS VGS = 0, ID = 250 μA 500 - - V ΔVDS/TJ Reference to 25 °C, ID = 1 mA c - 0.63 - V/°C VGS(th) VDS = VGS, ID = 250 μA 2.0 - 4.0 V Gate-Source Leakage IGSS VGS = ± 20 V - - ± 100 nA Zero Gate Voltage Drain Current IDSS VDS = 500 V, VGS = 0 V - - 25 VDS = 400 V, VGS = 0 V, TJ = 125 °C - - 250 - - 0.85 Ω 4.0 - - S Drain-Source On-State Resistance Forward Transconductance RDS(on) ID = 4.8 A b VGS = 10 V Ab gfs VDS = 50 V, ID = 4.8 VGS = 0 V, VDS = 25 V, f = 1.0 MHz, see fig. 5 c μA Dynamic Input Capacitance Ciss Output Capacitance Coss Reverse Transfer Capacitance Crss Total Gate Charge Qg Gate-Source Charge Qgs Gate-Drain Charge Qgd Turn-On Delay Time td(on) Rise Time Turn-Off Delay Time tr td(off) Fall Time tf Gate Input Resistance Rg VGS = 10 V ID = 8.0 A, VDS = 400 V, see fig. 6 and 13 b, c - 1100 - - 170 - - 18 - - - 39 - - 10 - - 19 - 12 - VDD = 250 V, ID = 8.0 A, Rg = 9.1 Ω, RD = 30 Ω, see fig. 10 b, c - 25 - - 27 - - 19 - f = 1 MHz, open drain 0.7 - 3.7 - - 8.0 - - 28 pF nC ns Ω Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current Pulsed Diode Forward Current a Body Diode Voltage IS ISM VSD Body Diode Reverse Recovery Time trr Body Diode Reverse Recovery Charge Qrr Forward Turn-On Time ton MOSFET symbol showing the integral reverse p - n junction diode D A G TJ = 25 °C, IS = 8.0 A, VGS = 0 S Vb TJ = 25 °C, IF = 8.0 A, dI/dt = 100 A/μs b, c - - 2.0 V - 490 740 ns - 3.0 4.5 μC Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD) Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11) b. Pulse width ≤ 300 μs; duty cycle ≤ 2 % c. Uses SiHF840LC data and test conditions S21-0901-Rev. D, 30-Aug-2021 Document Number: 91068 2 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRF840LCS, IRF840LCL, SiHF840LCS, SiHF840LCL www.vishay.com Vishay Siliconix VGS 15 V 10 V 8.0 V 7.0 V 6.0 V 5.5 V 5.0 V Bottom 4.5 V Top ID, Drain Current (A) 101 100 4.5 V 20 µs Pulse Width TC = 25 °C 10-1 10-1 100 2.5 2.0 1.5 1.0 0.5 0.0 - 60 - 40 - 20 0 20 40 60 80 100 120 140 160 TJ, Junction Temperature (°C) Fig. 4 - Normalized On-Resistance vs. Temperature 2400 VGS 15 V 10 V 8.0 V 7.0 V 6.0 V 5.5 V 5.0 V Bottom 4.5 V VGS = 0 V, f = 1 MHz Ciss = Cgs + Cgd, Cds Shorted Crss = Cgd Coss = Cds + Cgd Top 100 2000 4.5 V 10-1 Capacitance (pF) 101 1600 Ciss 1200 20 µs Pulse Width TC = 150 °C 10-1 100 800 Coss 400 Crss 0 101 100 VDS, Drain-to-Source Voltage (V) 91068_02 101 VDS, Drain-to-Source Voltage (V) 91068_05 Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage Fig. 2 - Typical Output Characteristics 101 150 °C 25 °C 100 20 µs Pulse Width VDS = 50 V VGS, Gate-to-Source Voltage (V) 20 ID, Drain Current (A) ID = 8.0 A VGS = 10 V 91068_04 Fig. 1 - Typical Output Characteristics ID, Drain Current (A) 3.0 101 VDS, Drain-to-Source Voltage (V) 91068_01 RDS(on), Drain-to-Source On Resistance (Normalized) TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) ID = 8.0 A VDS = 400 V 16 VDS = 250 V VDS = 100 V 12 8 4 For test circuit see figure 13 0 4 91068_03 5 6 7 8 9 VGS, Gate-to-Source Voltage (V) Fig. 3 - Typical Transfer Characteristics S21-0901-Rev. D, 30-Aug-2021 10 0 91068_06 8 16 24 32 40 48 QG, Total Gate Charge (nC) Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage Document Number: 91068 3 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRF840LCS, IRF840LCL, SiHF840LCS, SiHF840LCL www.vishay.com Vishay Siliconix ID, Drain Current (A) ISD, Reverse Drain Current (A) 8.0 150 °C 101 25 °C 100 VGS = 0 V 0.6 0.8 1.0 1.2 1.4 2.0 25 50 VGS + - VDD 5 10 µs 2 10 V Pulse width ≤ 1 µs Duty factor ≤ 0.1 % 100 µs 5 150 D.U.T. Rg 102 10 125 RD VDS 2 ID, Drain Current (A) 100 Fig. 9 - Maximum Drain Current vs. Case Temperature Operation in this area limited by RDS(on) 5 75 TC, Case Temperature (°C) 91068_09 Fig. 7 - Typical Source-Drain Diode Forward Voltage 103 4.0 0.0 1.6 VSD, Source-to-Drain Voltage (V) 91068_07 6.0 1 ms 2 Fig. 10a - Switching Time Test Circuit 1 10 ms TC = 25 °C TJ = 150 °C Single Pulse 5 2 0.1 1 2 5 10 2 5 VDS 90 % 102 2 5 103 VDS, Drain-to-Source Voltage (V) 91068_08 10 % VGS Fig. 8 - Maximum Safe Operating Area td(on) td(off) tf tr Fig. 10b - Switching Time Waveforms Thermal Response (ZthJC) 10 1 D = 0.5 PDM 0.2 0.1 0.1 t1 0.05 0.02 0.01 t2 Notes: 1. Duty Factor, D = t1/t2 2. Peak Tj = PDM x ZthJC + TC Single Pulse (Thermal Response) 10-2 10-5 10-4 10-3 10-2 0.1 1 10 t1, Rectangular Pulse Duration (s) 91068_11 Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case S21-0901-Rev. D, 30-Aug-2021 Document Number: 91068 4 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRF840LCS, IRF840LCL, SiHF840LCS, SiHF840LCL www.vishay.com Vishay Siliconix 15 V QG 10 V Driver L VDS Rg D.U.T 0.01 Ω tp QGD VG + A - VDD IAS 20 V QGS Charge Fig. 12a - Unclamped Inductive Test Circuit Fig. 13a - Basic Gate Charge Waveform VDS Current regulator Same type as D.U.T. tp 50 kΩ 12 V 0.2 µF 0.3 µF + D.U.T. IAS - VDS VGS Fig. 12b - Unclamped Inductive Waveforms 3 mA EAS, Single Pulse Energy (mJ) 1200 ID Top 3.6 A 5.1 A Bottom 8.0 A 1000 IG ID Current sampling resistors Fig. 13b - Gate Charge Test Circuit 800 600 400 200 0 VDD = 50 V 25 91068_12c 50 75 100 125 150 Starting TJ, Junction Temperature (°C) Fig. 12c - Maximum Avalanche Energy vs. Drain Current S21-0901-Rev. D, 30-Aug-2021 Document Number: 91068 5 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRF840LCS, IRF840LCL, SiHF840LCS, SiHF840LCL www.vishay.com Vishay Siliconix Peak Diode Recovery dV/dt Test Circuit + D.U.T. Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer + + - - Rg • • • • dV/dt controlled by Rg Driver same type as D.U.T. ISD controlled by duty factor “D” D.U.T. - device under test + - VDD Driver gate drive P.W. Period D= P.W. Period VGS = 10 Va D.U.T. lSD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt Re-applied voltage Inductor current VDD Body diode forward drop Ripple ≤ 5 % ISD Note a. VGS = 5 V for logic level devices Fig. 14 - For N-Channel Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91068. S21-0901-Rev. D, 30-Aug-2021 Document Number: 91068 6 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information Vishay Siliconix TO-263AB (HIGH VOLTAGE) A (Datum A) 3 A 4 4 L1 B A E c2 H Gauge plane 4 0° to 8° 5 D B Detail A Seating plane H 1 2 C 3 C L L3 L4 Detail “A” Rotated 90° CW scale 8:1 L2 B A1 B A 2 x b2 c 2xb E 0.010 M A M B ± 0.004 M B 2xe Plating 5 b1, b3 Base metal c1 (c) D1 4 5 (b, b2) Lead tip MILLIMETERS DIM. MIN. MAX. View A - A INCHES MIN. 4 E1 Section B - B and C - C Scale: none MILLIMETERS MAX. DIM. MIN. INCHES MAX. MIN. MAX. A 4.06 4.83 0.160 0.190 D1 6.86 - 0.270 - A1 0.00 0.25 0.000 0.010 E 9.65 10.67 0.380 0.420 6.22 - 0.245 - b 0.51 0.99 0.020 0.039 E1 b1 0.51 0.89 0.020 0.035 e b2 1.14 1.78 0.045 0.070 H 14.61 15.88 0.575 0.625 b3 1.14 1.73 0.045 0.068 L 1.78 2.79 0.070 0.110 2.54 BSC 0.100 BSC c 0.38 0.74 0.015 0.029 L1 - 1.65 - 0.066 c1 0.38 0.58 0.015 0.023 L2 - 1.78 - 0.070 c2 1.14 1.65 0.045 0.065 L3 D 8.38 9.65 0.330 0.380 L4 0.25 BSC 4.78 5.28 0.010 BSC 0.188 0.208 ECN: S-82110-Rev. A, 15-Sep-08 DWG: 5970 Notes 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Dimensions are shown in millimeters (inches). 3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the outmost extremes of the plastic body at datum A. 4. Thermal PAD contour optional within dimension E, L1, D1 and E1. 5. Dimension b1 and c1 apply to base metal only. 6. Datum A and B to be determined at datum plane H. 7. Outline conforms to JEDEC outline to TO-263AB. Document Number: 91364 Revision: 15-Sep-08 www.vishay.com 1 Package Information Vishay Siliconix I2PAK (TO-262) (HIGH VOLTAGE) A (Datum A) E B c2 A E A L1 Seating plane D1 D C L2 C B B L A c 3 x b2 E1 A1 3xb Section A - A Base metal 2xe b1, b3 Plating 0.010 M A M B c1 c (b, b2) Lead tip Section B - B and C - C Scale: None MILLIMETERS INCHES MILLIMETERS INCHES DIM. MIN. MAX. MIN. MAX. DIM. MIN. MAX. MIN. MAX. A 4.06 4.83 0.160 0.190 D 8.38 9.65 0.330 0.380 A1 2.03 3.02 0.080 0.119 D1 6.86 - 0.270 - b 0.51 0.99 0.020 0.039 E 9.65 10.67 0.380 0.420 b1 0.51 0.89 0.020 0.035 E1 6.22 - 0.245 - b2 1.14 1.78 0.045 0.070 e b3 1.14 1.73 0.045 0.068 L 13.46 14.10 0.530 0.555 c 0.38 0.74 0.015 0.029 L1 - 1.65 - 0.065 c1 0.38 0.58 0.015 0.023 L2 3.56 3.71 0.140 0.146 c2 1.14 1.65 0.045 0.065 2.54 BSC 0.100 BSC ECN: S-82442-Rev. A, 27-Oct-08 DWG: 5977 Notes 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm per side. These dimensions are measured at the outmost extremes of the plastic body. 3. Thermal pad contour optional within dimension E, L1, D1, and E1. 4. Dimension b1 and c1 apply to base metal only. Document Number: 91367 Revision: 27-Oct-08 www.vishay.com 1 AN826 Vishay Siliconix RECOMMENDED MINIMUM PADS FOR D2PAK: 3-Lead 0.420 0.355 0.635 (16.129) (9.017) (10.668) 0.145 (3.683) 0.135 (3.429) 0.200 0.050 (5.080) (1.257) Recommended Minimum Pads Dimensions in Inches/(mm) Return to Index Document Number: 73397 11-Apr-05 www.vishay.com 1 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. 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