IRFBC40LCL

IRFBC40LC www.vishay.com Vishay Siliconix Power MOSFET FEATURES D • Ultra low gate charge • Reduced gate drive requirement • Enhanced 30 V, VGS rating TO-220AB D • Extremely high frequency operation • Repetitive avalanche rated • Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 S S Note * This datasheet provides information about parts that are RoHS-compliant and / or parts that are non RoHS-compliant. For example, parts with lead (Pb) terminations are not RoHS-compliant. Please see the information / tables in this datasheet for details N-Channel MOSFET PRODUCT SUMMARY VDS (V) RDS(on) (Ω) 600 VGS = 10 V Qg max. (nC) DESCRIPTION 1.2 This new series of low charge power MOSFETs achieve significantly lower gate charge over conventional Power MOSFETs. Utilizing the new LCDMOS technology, the device improvements are achieved without added product cost, allowing for reduced gate drive requirements and total system savings. In addition reduced switching losses and improved efficiency are achievable in a variety of high frequency applications. Frequencies of a few MHz at high current are possible using the new low charge power MOSFETs. These device improvements combined with the proven ruggedness and reliability that are characteristic of power MOSFETs offer the designer a new standard in power transistors for switching applications. 39 Qgs (nC) 10 Qgd (nC) 19 Configuration Available • Reduced Ciss, Coss, Crss G G Available Single ORDERING INFORMATION Package Lead (Pb)-free TO-220AB IRFBC40LCPbF Lead (Pb)-free and halogen-free IRFBC40LCPbF-BE3 ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted) PARAMETER Drain-source voltage Gate-source voltage Continuous drain current Pulsed drain current a Linear derating factor Single pulse avalanche energy b Repetitive avalanche current a Repetitive avalanche energy a Maximum power dissipation Peak diode recovery dV/dt c Operating junction and storage temperature range Soldering recommendations (peak temperature) d Mounting torque SYMBOL VDS VGS VGS at 10 V TC = 25 °C TC = 100 °C ID IDM TC = 25 °C For 10 s 6-32 or M3 screw EAS IAR EAR PD dV/dt TJ, Tstg LIMIT 600 ± 30 6.2 3.9 25 1.0 530 6.2 13 125 3.0 -55 to +150 300 10 1.1 UNIT V A W/°C mJ A mJ W V/ns °C lbf · in N·m Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11) b. VDD = 50 V, starting TJ = 25 °C, L = 25 mH, Rg = 25 Ω, IAS = 6.2 A (see fig. 12) c. ISD ≤ 6.2 A, dI/dt ≤ 80 A/μs, VDD ≤ VDS, TJ ≤ 150 °C d. 1.6 mm from case S21-0868-Rev. E, 16-Aug-2021 Document Number: 91114 1 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRFBC40LC www.vishay.com Vishay Siliconix THERMAL RESISTANCE RATINGS PARAMETER SYMBOL TYP. MAX. Maximum junction-to-ambient RthJA - 62 Case-to-sink, flat, greased surface RthCS 0.50 - Maximum junction-to-case (drain) RthJC - 1.0 UNIT °C/W SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT VDS VGS = 0 V, ID = 250 μA 600 - - V ΔVDS/TJ Reference to 25 °C, ID = 1 mA - 0.70 - V/°C Static Drain-source breakdown voltage VDS temperature coefficient VGS(th) VDS = VGS, ID = 250 μA 2.0 - 4.0 V Gate-source leakage IGSS VGS = ± 20 - - ± 100 nA Zero gate voltage drain current IDSS Gate-source threshold voltage Drain-source on-state resistance RDS(on) VDS = 600 V, VGS = 0 V - - 100 VDS = 480 V, VGS = 0 V, TJ = 125 °C - - 500 - - 1.2 Ω - S ID = 3.7 A b VGS = 10 V gfs VDS = 100 V, ID = 3.7 A b 3.7 - Input capacitance Ciss 1100 - Coss - 140 - Reverse transfer capacitance Crss VGS = 0 V VDS = 25 V f = 1.0 MHz, see fig. 5 - Output capacitance - 15 - - - 39 - - 10 Forward transconductance μA Dynamic pF Total gate charge Qg Gate-source charge Qgs Gate-drain charge Qgd - - 19 Turn-on delay time td(on) - 12 - tr - 20 - - 27 - - 17 - - 4.5 - - 7.5 - 0.6 - 3.9 - - 6.2 S - - 25 TJ = 25 °C, IS = 6.2 A, VGS = 0 V b - - 1.5 V - 440 680 ns - 2.1 3.2 μC Rise time Turn-off delay time td(off) Fall time tf Internal drain inductance LD Internal source inductance LS Gate input resistance Rg VGS = 10 V ID = 6.2 A, VDS = 360 V, see fig. 6 and 13 b VDD = 300 V, ID = 6.2 A Rg = 9.1 Ω, RD = 47 Ω, see fig. 10 b Between lead, 6 mm (0.25") from package and center of die contact D nC ns nH G S f = 1 MHz, open drain Ω Drain-Source Body Diode Characteristics Continuous source-drain diode current IS Pulsed diode forward current a ISM Body diode voltage VSD Body diode reverse recovery time trr Body diode reverse recovery charge Qrr Forward turn-on time ton MOSFET symbol showing the integral reverse p - n junction diode D A G TJ = 25 °C, IF = 6.2 A, dI/dt = 100 A/μs b Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD) Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11) b. Pulse width ≤ 300 μs; duty cycle ≤ 2 % S21-0868-Rev. E, 16-Aug-2021 Document Number: 91114 2 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRFBC40LC www.vishay.com Vishay Siliconix VGS 15 V 10 V 8.0 V 7.0 V 6.0 V 5.5 V 5.0 V Bottom 4.5 V Top ID, Drain Current (A) 101 100 4.5 V 10-1 20 µs Pulse Width TC = 25 °C 10-2 10-2 10-1 101 100 102 VDS, Drain-to-Source Voltage (V) 91114_01 RDS(on), Drain-to-Source On Resistance (Normalized) TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 - 60 - 40 - 20 0 VGS = 0 V, f = 1 MHz Ciss = Cgs + Cgd, Cds Shorted Crss = Cgd Coss = Cds + Cgd Top 100 2000 4.5 V Capacitance (pF) ID, Drain Current (A) Fig. 4 - Normalized On-Resistance vs. Temperature 2400 VGS 15 V 10 V 8.0 V 7.0 V 6.0 V 5.5 V 5.0 V Bottom 4.5 V 10-1 1600 Ciss 1200 Coss 800 Crss 400 20 µs Pulse Width TC = 150 °C 10-2 10-2 100 10-1 101 0 102 VDS, Drain-to-Source Voltage (V) 91114_02 100 Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage ID, Drain Current (A) 25 °C 100 20 µs Pulse Width VDS = 100 V 10-1 4 91114_03 5 6 7 8 9 Fig. 3 - Typical Transfer Characteristics ID = 5.2 A VDS = 300 V 16 VDS = 240 V VDS = 180 V 12 8 4 For test circuit see figure 13 0 10 VGS, Gate-to-Source Voltage (V) S21-0868-Rev. E, 16-Aug-2021 VGS, Gate-to-Source Voltage (V) 20 150 °C 101 VDS, Drain-to-Source Voltage (V) 91114_05 Fig. 2 - Typical Output Characteristics, TC = 150 °C 101 20 40 60 80 100 120 140 160 TJ, Junction Temperature (°C) 91114_04 Fig. 1 - Typical Output Characteristics, TC = 25 °C 101 ID = 6.2 A VGS = 10 V 0 91114_06 8 16 24 32 40 QG, Total Gate Charge (nC) Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage Document Number: 91114 3 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRFBC40LC www.vishay.com Vishay Siliconix ISD, Reverse Drain Current (A) 7.0 101 ID, Drain Current (A) 6.0 150 °C 25 °C 5.0 4.0 3.0 2.0 1.0 VGS = 0 V 100 0.6 0.8 1.0 0.0 25 1.4 1.2 VSD, Source-to-Drain Voltage (V) 91114_07 2 125 150 RD VDS VGS 102 ID, Drain Current (A) 100 Fig. 9 - Maximum Drain Current vs. Case Temperature Operation in this area limited by RDS(on) 5 75 TC, Case Temperature (°C) 91114_09 Fig. 7 - Typical Source-Drain Diode Forward Voltage 103 50 D.U.T. Rg 5 + - VDD 10 µs 2 10 10 V 100 µs 5 2 Pulse width ≤ 1 μs Duty factor ≤ 0.1 % 1 ms 1 10 ms 5 2 Fig. 10a - Switching Time Test Circuit 0.1 TC = 25 °C TJ = 150 °C Single Pulse 5 2 10-2 0.1 2 5 1 2 5 10 2 2 5 102 VDS 5 103 2 5 90 % 104 VDS, Drain-to-Source Voltage (V) 91114_08 Fig. 8 - Maximum Safe Operating Area 10 % VGS td(on) td(off) tr tf Fig. 10b - Switching Time Waveforms Thermal Response (ZthJC) 10 1 0 − 0.5 PDM 0.2 0.1 0.1 t1 0.05 t2 0.02 0.01 Notes: 1. Duty Factor, D = t1/t2 2. Peak Tj = PDM x ZthJC + TC Single Pulse (Thermal Response) 10-2 10-5 10-4 10-3 10-2 0.1 1 10 t1, Rectangular Pulse Duration (s) 91114_11 Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case S21-0868-Rev. E, 16-Aug-2021 Document Number: 91114 4 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRFBC40LC www.vishay.com Vishay Siliconix L VDS VDS Vary tp to obtain required IAS tp VDD D.U.T. Rg + - VDD VDS IAS 10 V tp 0.01 Ω IAS Fig. 12a - Unclamped Inductive Test Circuit Fig. 12b - Unclamped Inductive Waveforms EAS, Single Pulse Energy (mJ) 1200 ID 2.8 A 3.9 A Bottom 5.2 A Top 1000 800 600 400 200 0 VDD = 50 V 25 91114_12c 50 75 100 150 125 Starting TJ, Junction Temperature (°C) Fig. 12c - Maximum Avalanche Energy vs. Drain Current Current regulator Same type as D.U.T. 50 kΩ Qg VGS 12 V 0.2 μF 0.3 μF Qgs Qgd + D.U.T. VG - VDS VGS 3 mA Charge IG ID Current sampling resistors Fig. 13a - Basic Gate Charge Waveform S21-0868-Rev. E, 16-Aug-2021 Fig. 13b - Gate Charge Test Circuit Document Number: 91114 5 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRFBC40LC www.vishay.com Vishay Siliconix Peak Diode Recovery dv/dt Test Circuit + D.U.T. Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer 3 + 2 - - 4 + 1 Rg • • • • 1 Driver gate drive Period P.W. + V - DD dv/dt controlled by Rg Driver same type as D.U.T. ISD controlled by duty factor “D” D.U.T. - device under test D= P.W. Period V GS = 10 V a 2 D.U.T. ISD waveform Reverse recovery current 3 D.U.T. VDS Body diode forward current di/dt waveform Diode recovery dv/dt Re-applied voltage V DD Body diode forward drop 4 Inductor current Ripple ≤ 5 % ISD Note a. VGS = 5 V for logic level devices Fig. 14 - For N-Channel Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91114. S21-0868-Rev. E, 16-Aug-2021 Document Number: 91114 6 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information www.vishay.com Vishay Siliconix TO-220-1 A E F D H(1) Q ØP 3 2 L(1) 1 M* L b(1) C b e J(1) e(1) MILLIMETERS DIM. INCHES MIN. MAX. MIN. MAX. A 4.24 4.65 0.167 0.183 b 0.69 1.02 0.027 0.040 b(1) 1.14 1.78 0.045 0.070 c 0.36 0.61 0.014 0.024 D 14.33 15.85 0.564 0.624 E 9.96 10.52 0.392 0.414 e 2.41 2.67 0.095 0.105 e(1) 4.88 5.28 0.192 0.208 F 1.14 1.40 0.045 0.055 H(1) 6.10 6.71 0.240 0.264 J(1) 2.41 2.92 0.095 0.115 L 13.36 14.40 0.526 0.567 L(1) 3.33 4.04 0.131 0.159 ØP 3.53 3.94 0.139 0.155 Q 2.54 3.00 0.100 0.118 ECN: E21-0621-Rev. D, 04-Nov-2021 DWG: 6031 Note • M* = 0.052 inches to 0.064 inches (dimension including protrusion), heatsink hole for HVM Document Number: 66542 1 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Revison: 04-Nov-2021 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. 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