IRFR010TRR

IRFR010, SiHFR010 www.vishay.com Vishay Siliconix Power MOSFET FEATURES D • • • • • • DPAK (TO-252) D G S G S DESCRIPTION N-Channel MOSFET The power MOSFET technology is the key to Vishay’s advanced line of power MOSFET transistors. The efficient geometry and unique processing of this latest “State of the Art” design achieves: very low on-state resistance combined with high transconductance; superior reverse energy and diode recovery dV/dt capability. The power MOSFET transistors also feature all of the well established advantages of MOSFET’S such as voltage control, very fast switching, ease of paralleling and temperature stability of the electrical parameters. Surface mount packages enhance circuit performance by reducing stray inductances and capacitance. The DPAK (TO-252) surface-mount package brings the advantages of power MOSFET’s to high volume applications where PC Board surface mounting is desirable. The surface mount option IRFR9012, SiHFR9012 is provided on 16 mm tape. The straight lead option IRFU9012, SiHFU9012 of the device is called the IPAK (TO-251). They are well suited for applications where limited heat dissipation is required such as, computers and peripherals, telecommunication equipment, dc-to-dc converters, and a wide range of consumer products. PRODUCT SUMMARY VDS (V) RDS(on) (Ω) 50 VGS = 10 V Qg (Max.) (nC) 0.20 10 Qgs (nC) 2.6 Qgd (nC) 4.8 Configuration Low drive current Surface-mount Fast switching Ease of paralleling Excellent temperature stability Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 Single ORDERING INFORMATION Package DPAK (TO-252) DPAK (TO-252) DPAK (TO-252) Lead (Pb)-free and halogen-free SiHFR010-GE3 SiHFR010TR-GE3 SiHFR010TRL-GE3 DPAK (TO-252) IRFR010PbF-BE3 Lead (Pb)-free IRFR010PbF IRFR010TRPbF IRFR010TRLPbF IRFR010TRRPbF ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted) PARAMETER SYMBOL LIMIT Drain-source voltage VDS 50 Gate-source voltage VGS ± 20 Continuous drain current VGS at 10 V TC = 25 °C TC = 100 °C ID Pulsed drain current a IDM Avalanche current b IAS Linear derating factor Maximum power dissipation Peak diode recovery dV/dt c Operating junction and storage temperature range Soldering recommendations (peak temperature) d For 10 s V 8.2 5.2 33 A 1.5 0.20 TC = 25 °C UNIT W/°C PD 25 W dV/dt 2.0 V/ns TJ, Tstg -55 to +150 300 °C Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11) b. VDD = 25 V, starting TJ = 25 °C, L = 100 μH, Rg = 25 Ω c. ISD ≤ 8.2 A, dI/dt ≤ 130 A/μs, VDD ≤ 40 V, TJ ≤ 150 °C d. 1.6 mm from case e. When mounted on 1" square PCB (FR-4 or G-10 material) S21-0466-Rev. C, 17-May-2021 Document Number: 91420 1 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRFR010, SiHFR010 www.vishay.com Vishay Siliconix THERMAL RESISTANCE RATINGS PARAMETER SYMBOL MIN. TYP. MAX. Maximum junction-to-ambient RthJA - - 110 Case-to-sink RthCS - 1.7 - Maximum junction-to-case (drain) RthJC - - 5.0 UNIT °C/W SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT VDS VGS = 0 V, ID = 250 μA 50 - - V Static Drain-source breakdown voltage VGS(th) VDS = VGS, ID = 250 μA 2.0 - 4.0 V Gate-source leakage IGSS VGS = ± 20 V - - ± 500 nA Zero gate voltage drain current IDSS VDS = 50 V, VGS = 0 V - - 250 VDS = 40 V, VGS = 0 V, TJ = 125 °C - - 1000 - 0.16 0.20 Ω VDS ≥ 50 V, ID = 3.6 A 2.1 3.1 - S VGS = 0 V, VDS = 25 V, f = 1.0 MHz, see fig. 10 - 250 - - 150 - - 29 - Gate-source threshold voltage Drain-source on-state resistance Forward transconductance RDS(on) gfs ID = 4.6 Ab VGS = 10 V μA Dynamic Input capacitance Ciss Output capacitance Coss Reverse transfer capacitance Crss Total gate charge Qg Gate-source charge Qgs VGS = 10 V ID = 7.3 A, VDS = 40 V, see fig. 6 and 13b - 6.7 10 - 1.8 2.6 Gate-drain charge Qgd - 3.2 4.8 Turn-on delay time td(on) - 11 17 tr - 33 50 - 12 18 - 23 35 - 4.5 - - 7.5 - - - 8.2 - - 33 Rise time Turn-off delay time Fall time Internal drain inductance Internal source inductance td(off) VDD = 25 V, ID = 7.3 A, Rg = 24 Ω, RD = 3.3 Ω, see fig. 10b tf LD LS Between lead, 6 mm (0.25") from package and center of die contactc pF nC ns D nH G S Drain-Source Body Diode Characteristics Continuous source-drain diode current Pulsed diode forward current a Body diode voltage IS ISM VSD Body diode reverse recovery time trr Body diode reverse recovery charge Qrr Forward turn-on time ton MOSFET symbol showing the integral reverse p - n junction diode D A G TJ = 25 °C, IS = 8.2 A, VGS = 0 S Vb TJ = 25 °C, IF = 7.3 A, dI/dt = 100 A/μsb - - 1.6 V 41 86 190 ns 0.15 0.33 0.78 μC Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD) Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11) b. Pulse width ≤ 300 μs; duty cycle ≤ 2 % S21-0466-Rev. C, 17-May-2021 Document Number: 91420 2 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRFR010, SiHFR010 www.vishay.com Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) Fig. 1 - Typical Output Characteristics Fig. 1 - Typical Output Characteristics S21-0466-Rev. C, 17-May-2021 Fig. 2 - Typical Transfer Characteristics Fig. 3 - Normalized On-Resistance vs. Temperature Document Number: 91420 3 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRFR010, SiHFR010 www.vishay.com Fig. 4 - Typical Capacitance vs. Drain-to-Source Voltage Fig. 5 - Typical Gate Charge vs. Gate-to-Source Voltage S21-0466-Rev. C, 17-May-2021 Vishay Siliconix Fig. 6 - Typical Source-Drain Diode Forward Voltage Fig. 7 - Maximum Safe Operating Area Document Number: 91420 4 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRFR010, SiHFR010 www.vishay.com Vishay Siliconix VDS VGS RD D.U.T. RG + - VDD 10 V Pulse width ≤ 1 µs Duty factor ≤ 0.1 % Fig. 10a - Switching Time Test Circuit VDS 90 % Fig. 8 - Maximum Drain Current vs. Case Temperature 10 % VGS td(on) tr td(off) tf Fig. 10b - Switching Time Waveforms Fig. 9 - Breakdown Voltage vs. Temperature Fig. 10 - Maximum Effective Transient Thermal Impedance, Junction-to-Case S21-0466-Rev. C, 17-May-2021 Document Number: 91420 5 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRFR010, SiHFR010 www.vishay.com Vishay Siliconix L Vary tp to obtain required IAS VDS VDS tp VDD D.U.T RG + - I AS V DD VDS 10 V 0.01 Ω tp Fig. 12a - Unclamped Inductive Test Circuit IAS Fig. 12b - Unclamped Inductive Waveforms Fig. 12c - Typical Transconductance vs. Drain Current Current regulator Same type as D.U.T. 50 kΩ QG VGS 12 V 0.2 µF 0.3 µF QGS QGD + D.U.T. VG - VDS VGS 3 mA Charge IG ID Current sampling resistors Fig. 13a - Basic Gate Charge Waveform S21-0466-Rev. C, 17-May-2021 Fig. 13b - Gate Charge Test Circuit Document Number: 91420 6 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRFR010, SiHFR010 www.vishay.com Vishay Siliconix Peak Diode Recovery dV/dt Test Circuit + D.U.T. Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer + + - - Rg • • • • dV/dt controlled by Rg Driver same type as D.U.T. ISD controlled by duty factor “D” D.U.T. - device under test + - VDD Driver gate drive P.W. Period D= P.W. Period VGS = 10 Va D.U.T. lSD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt Re-applied voltage Inductor current VDD Body diode forward drop Ripple ≤ 5 % ISD Note a. VGS = 5 V for logic level devices Fig. 11 - For N-Channel Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91420. S21-0466-Rev. C, 17-May-2021 Document Number: 91420 7 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information www.vishay.com Vishay Siliconix TO-252AA Case Outline VERSION 1: FACILITY CODE = Y E A C2 H D D1 L3 b3 e b2 e1 L gage plane height (0.5 mm) L4 b L5 E1 C A1 MILLIMETERS DIM. MIN. A 2.18 MAX. 2.38 A1 - 0.127 b 0.64 0.88 b2 0.76 1.14 b3 4.95 5.46 C 0.46 0.61 C2 0.46 0.89 D 5.97 6.22 D1 4.10 - E 6.35 6.73 E1 4.32 - H 9.40 10.41 e 2.28 BSC e1 4.56 BSC L 1.40 1.78 L3 0.89 1.27 L4 - 1.02 L5 1.01 1.52 Note • Dimension L3 is for reference only Revision: 03-Oct-2022 Document Number: 71197 1 For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information www.vishay.com Vishay Siliconix VERSION 2: FACILITY CODE = N E e A b3 E1 E1/2 c2 θ e L4 L5 L6 H D L3 D1 θ 0.25 (3°) DETAIL "B" C A B (3°) DETAIL "B" A1 C L (L1) b1 SEATING C PLANE θ L2 GAUGE PLANE H C (b) c1 3x b 2x e c 2x b2 MILLIMETERS MILLIMETERS DIM. A MIN. 2.18 MAX. DIM. MIN. 2.39 L 1.50 A1 - 0.13 L1 b 0.65 0.89 L2 MAX. 1.78 2.74 ref. 0.51 BSC b1 0.64 0.79 L3 b2 0.76 1.13 L4 - 1.02 b3 4.95 5.46 L5 1.14 1.49 c 0.46 0.61 L6 0.65 0.85 c1 0.41 0.56  0° 10° 1 0° 15° 2 25° 35° c2 0.46 0.60 D 5.97 6.22 D1 5.21 - E 6.35 6.73 E1 4.32 e H 2.29 BSC 9.94 0.89 1.27 Notes • Dimensioning and tolerance confirm to ASME Y14.5M-1994 • All dimensions are in millimeters. Angles are in degrees • Heat sink side flash is max. 0.8 mm • Radius on terminal is optional 10.34      ECN: E22-0399-Rev. R, 03-Oct-2022 DWG: 5347 Revision: 03-Oct-2022 Document Number: 71197 2 For technical questions, contact: pmostechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Application Note 826 Vishay Siliconix RECOMMENDED MINIMUM PADS FOR DPAK (TO-252) 0.224 0.243 0.087 (2.202) 0.090 (2.286) (10.668) 0.420 (6.180) (5.690) 0.180 0.055 (4.572) (1.397) Recommended Minimum Pads Dimensions in Inches/(mm) Return to Index Return to Index APPLICATION NOTE Document Number: 72594 Revision: 21-Jan-08 www.vishay.com 3 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. 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